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Date Created: 02/27/15
operating system E mail Music WEE reader player browser 1 User mode User interface program E m am Kernel mode peratin system Figure 11 Either the pirating system ts in It is a software program that manages the computer hardware It acts as an interface between users and peripheral devices It runs on a kernel modeprivi1eged Kernel Mode In Kernel mode the executing code has complete and unrestricted access to the underlying hardware It can execute any CPU instruction and reference any memory address like RAMcritical data structure direct hardware INOUT or memory mapped direct memory IRQ DMA and so on Kernel mode is generally reserved for the lowestlevel most trusted functions of the operating system Crashes in kernel mode are catastrophic they will halt the entire PC A good example of this would be device drivers A device driver must tell the kernel exactly how to interact with a piece of hardware so it must be run in kernel mode Kernel types monolithicmicrokerne and so on When bug occurs entire pc will crash Eg Set value of timertimer mgmt clear memory turn off interruptsinterrupt mgmt modify entries in devicestatus table access IO device User Mode In User mode the executing code has no ability to directly access hardware or reference memory They don39t interact directly with the kernel instead they just give instructions on what needs to be done and the kernel takes care of the rest Code running in user mode must delegate to system APIs to access hardware or memory Due to the protection afforded by this sort of isolation crashes in user mode are always recoverable Most of the code running on your computer will execute in user mode When in User Mode some parts of RAM cannot be addressedimit6d memory space that is allocated to the user program some instructions can t be executed User mode programs Web browsers calculators read clock GtC It s function 1 To abstract the resources so that it can hide the messy hardware from applications a That is it provides set of resources like api s to user mode non privileged access egdrivers control disks OS abstracts using disks Via file access hiding how the hardware works applicatinn programs eautitlul inte rl ase L 3 t Ugllyinterl acs H ardw rs Figure 12 Spawning systsms tum ugly l l l i t if into hesuti tl abstractions 2 Resource management a It controls the resource allocation b 2 ways multiplexing them Via time and space c Time multiplexing programs take turns in execution OS needs to decide how long a program can run before the next program takes control This is done in a round robin function Say os decides 5 min for all its process This means each process will run for 5 min Some process may require only 3 minutes to complete since 5 min is allocated the cpu will stay idle for 2 min and then take up the next process this is a disadvantage as other process is made waiting d Space multiplexing each one gets part of resource Main memory is shared among different programs Even disks can hold files of different users at the same time EVOLUTION 1 First generation 1945 1955Vaccum tubes a Programmers block time to use machine room signing the sheet insert plug boards and start working hoping vacuum tubes will not burn 2 Second generation 1955 l965Transistors and batch systems a In 1950 came punch cards Program using FORTRAN is punched onto the cards This card deck then is sent to input room where it is processed the printed outputs are taken to output room where it is punched on the card decks This is time consuming b Evolved are batch systems which use IBM 1401 Jobs are collected and written onto magnetic tapes It is then loaded onto tape drives in a machine room each job is processed and output is written onto the next tape drive when the first job has completed processing the second job starts processing while first job output is loaded on to a tape drive The output tape is bought after all jobs have finished for printing Tape System drive HrquotHillHi tape Dutput Card I I r ND I reader 9 I quota I x I I39 Ilsa 39 39 r A 1 g E I Iquot I r LTh j L 1quotJ I 1431 I I r94 W 1401 If laxity I if I LL ag I 39 all by in lid l9 339 Figure LII3 Elm early batch system a Prograrmners bring 23de to lil l ib m1 reads batch of jobs onto tape e Upwamr calTies niput tape to 71394 de TU94 tloee computing e peratof carries output tape to 14m f 14m priuits output 3 Third generation l965 l980lC s and multiprogramming a Ibm 360 s used IC that is built upon a collection of transistors it supported multiprogramming that is memory is partitioned into areas to be used for various programs This is known as spoolingsimultaneous peripheral operation on line b Then came ctsscompatible time sharing systems c Followed by multicsmultiplexed information and computing service 4 Fourth generation 1980 present personal computers a Large scale integration circuits Where used that contains 1000 s of transistors on a square centimeter of silicon 5 Fifth generation 1990 Present mobile computers COMPUTER HARDWARE A modern general purpose computer system consists of one or more CPUs and a number of device controllers connected through a common bus that provides access to shared memory Figure 12 Each device controller is in charge of a specific type of device for example disk drives audio devices or video displays The CPU and the device controllers can execute in parallel competing for memory cycles To ensure orderly access to the shared memory a memory controller synchronizes access to the memory Monitor Ha Keyboard U3 primer dialt dl IJIJIJIJIII CPU ween Hayward LIE W centrollr CWEWHEF eunrtrll er mmm ller Ems Memor Figure 16 Some of the components of a sample personal computer Memory management unit It is a computer hardware component that handles all memory and caching operations associated with the processor In other words the MMU is responsible for all aspects of memory management It is usually integrated into the processor although in some systems it occupies a separate IC integrated circuit chip Primarily performing the translation of Virtual memory addresses to physical addresses PROCESS CPU The CPU or Central Processing Unit is the quotbrainquot of the computer it is the 39compute39 in computer Without the CPU you have no computer Computer CPU s processors is composed of thin layers of thousands of transistors A computer CPU is composed of millions and soon billions of transistors Because CPU39s are so small they are often referred to as microprocessors So the terms processor microprocessor and CPU are interchangeable AMD IBM Intel Motorola SGI and Sun are just a few of the companies that make most of the CPU39s used for various kinds of computers including home desktops office computers mainframes and supercomputers Modern CPU39s are What are called 39integrated chips39 The idea behind an integrated chip is that several types of components are integrated into a single piece of silicon a single CPU such as one or more execution cores arithmetic logic unit ALU or 39 oating point39 processor registers instruction memory cache memory and the inputoutput controller bus controller The transistors within the CPU transition from being a non conductor resist the electricity to a conductor they conduct electricity when the electrical charge is strong enough Each transistor receives a set of inputs and produces output When one or more of the inputs receive electricity the combined charge changes the state of the transistor internally and you get a result out the other side This simple effect of the transistor is what makes it possible for the computer to count and perform logical operations all of which we call processing Physica ll Add FE EEIE39E llLdicall Add 3335 rganis Central rummaging IlJn it E LI M Esman ti H Gengral RI Adan egsners H1 an EHW R2 quot11 r M Hal Address unsu m n I H I mput Input Hie isflier 1 F HEIEtEr m Input Hegiater 2 31 I quot V Data Bus Fm ram Enum39liar I E quotIi I I Instruction egis ter Instruction annuall i ll h E ntml Buns am I T EiFE I Enntml Unit Hectwnte 3FF CPU fetches instructions from memory and executes them The memory is a main memory which uses dynamic ramDRAM technology other forms of memory are ROMEEPROM Memory is a stream of bytes Each of them has address The instructions that cpu execute are specific Thus an X86 processor cannot execute ARM programs and an ARM processor cannot execute x86 programs Because accessing memory to get an instruction or data word takes much longer than executing an instruction Thus the instruction set generally contains instructions to load a word from memory into a register and store a word from a register into memory Other instructions combine two operands from registers memory or both into a result such as adding two words and storing the result in a register or in memory A typical instruction execution cycle as executed on a system with Von Neumann architecture first fetches an instruction from memory and stores that instruction in the instruction register The instruction is then decoded and may cause operands to be fetched from memory and stored in some internal register After the instruction on the operands has been executed the result may be stored back in memory Execute Limit Fetish j Degrade 7 unit Llrilllt A 1 Execute Fetish icicle Execute H ldmg I I Lmnit unit quot Lillrlll unlit F h D m Elli an E unit 4 unit quot Execute Lillrlit a til Figure 11 a 351 time stage pipeline b A supersc ar CPU SUPER SCALAR CPU In this design multiple execution units are present for example one for integer arithmetic one for oatingpoint arithmetic and one for Boolean operations Two or more instructions are fetched at once decoded and dumped into a holding buffer until they can be executed As soon as an execution unit becomes available it looks in the holding buffer to see if there is an instruction it can handle and if so it removes the instruction from the buffer and executes it An implication of this design is that program instructions are often executed out of order The Program Counter PC is a special register that holds the address of the next instruction to be fetched from Memory for execution The Instruction Register IR is a special register that holds each instruction after it is fetched from main memory The Control Unit is the CPU component that co ordinates all actiVity Within the CPU The Arithmetic amp Logic Unit ALU is the CPU component that carries out arithmetic and logical operations eg addition comparison boolean ANDOWNOT The ALU Input Registers l amp 2 are special registers that hold the input operands for the ALU The ALU Output Register is a special register that holds the result of an ALU operation The General Purpose Registers R0 R1 R2 R3 are available for the programmer to use in hisher programs Typically the programmer tries to maximize the use of these registers in order to speed program execution Stack pointer register points to the top of the current stack in memory The stack contains one frame for each procedure that has been entered but not yet exited PSW Program Status Word register contains the condition code bits like the mode user l or kernel 0 bit The Buses serve as communication highways for passing information within the CPU CPU internal bus and between the CPU and the main memory the address bus the data bus and the control bus The address bus is used to send addresses from the CPU to the main memory these addresses indicate the memory location the CPU wishes to read or write Unlike the address bus the data bus is bi directional for writing the data bus is used to send a word from the CPU to main memory for reading the data bus is used to send a word from main memory to the CPU Most CPUs have two modes kernel mode and user mode as mentioned earlier Usually a bit in the PSW controls the mode When running in kernel mode the CPU can execute every instruction in its instruction set and use every feature of the hardware On desktop and server machines the operating system normally runs in kernel mode giving it access to the complete hardware User programs always run in user mode which permits only a subset of the instructions to be executed and a subset of the features to be accessed Generally all instructions involving U0 and memory protection are disallowed in user mode Setting the PSW mode bit to enter kernel mode is also forbidden of course To obtain services from the operating system a user program must make a system call which traps into the kernel and invokes the operating system The TRAP instruction switches from user mode to kernel mode and starts the operating system It is a software generated interrupt caused either by an error for example division by zero or invalid memory access or by a specific request from a user program that an operating system service be performed At system boot time the hardware starts in kernel mode The operating system is then loaded and starts user applications in user mode Whenever a trap or interrupt occurs the hardware switches from user mode to kernel mode that is changes the state of the mode bit to O MEET Fif GEEE ere er melee ueer preeee ezrreeeting e eelle eyetem eell return firm eye39rem eellr Ime m E H l r39 1r J H I trep reterrr erne mede hit El mede tilt l r 1 here elj merle mede bit 2 Er exeeute eyerem eell Figure 11 Treneiitien trem ueer te kernel rmer e Single Core Single Processor In the case of a computer with a single CPU core only one task runs at any point in time meaning that the CPU is actively executing instructions for that task Multitasking solves this problem by scheduling which task may run at any given time and when another waiting task gets a turn ElleCore l CPU chip T 5r3 l i i v a a main 1 bus Interface M mmg memmy 7 L ii L quotMG bug I Expansion Shirts for J 39 other devices such USE grapahmeg ligk as network adapters 7 c ztr ll r adapter controller Tl l 39 momseHayboard monitor g J 1 Eli 1552113 3 an quotn w d f l w i Jar l E H 1 i g V lEllTIEII V 7 Antmrus Processor runaway 1 E 2 Hal EH u EH E E E E E E E E F7 7 77 777W 7 7 if 7 7 if 7quot Upf tlng Systm CFU Zara Multiprocessors A multiprocessor system contains more than one CPU allowing them to work in parallel This is called SMP The most common systems use symmetric multiprocessing SMP in which each processor performs all tasks within the operating system SMP means that all processors are peers Each processor has its own set of registers as well as a private or local cache However all processors share physical memory The benefit of this model is that many processes can run simultaneously N processes can run if there are N CPUs without causing performance to deteriorate significantly Also since the CPUs are separate one may be sitting idle while another is overloaded resulting in inefficiencies These inefficiencies can be avoided if the processors share certain data structures sung GUI 1 GPth registers registers registers serene same same ii l lEiii39l lDl f Figure 116 Emmeiiris multiprocessing smehiieeture Multicore A multi core CPU has multiple execution cores on one CPU This is called CMP Chip level Multiprocessing L1 We care Km Gama a M lETigm39e 13 a E chip mm a shared cache Eh quad em ehip wim septa enema Core 391 Core 2 Core 3 Core 4 register l ille register fiile ragliieler file register le Ti quotiiALu f T E a H hue nterfaee 6 mini lt When running on a multicore system multitasking OSs can truly execute multiple tasks concurrently The multiple computing engines work independently on different tasks The core run lln parallel thread 1 thread 2 Thread tlhlread 4 llEEK I quotD quotG quotD m m m Within each core threads are timesliced just like on a uniproeessor several several several several threads threads threads threads 0 e e e d d e d r r r r e e e e 2 3 4 For example on a dual core system four applications such as word processing e mail Web browsing and antiVirus software can each access a separate processor core at the same time You can multitask by checking e mail and typing a letter simultaneously thus improving overall performance for applications 1 Email 1 wgh Ant tivilms wardquot rnwser lPirnEesanr L FREE I F m i 39 i FREE perating sygtgm l 1 1 EFL Ema ESEPU t2an Figure 2 Dual core systems enable multitasking operating systems to execute two tasks simultaneously Memory Programs and data cannot reside in main memory permanently This arrangement usually is not possible for the following two reasons 1 Main memory is usually too small to store all needed programs and data permanently 2 Main memory is a volatile storage device that loses its contents when power is turned off or otherwise lost Thus most computer systems provide secondary storage as an extension of main memory The main requirement for secondary storage is that it be able to hold large quantities of data permanently The most common secondary storage device is a magnetic disk which provides storage for both programs and data Most programs system and application are stored on a disk until they are loaded into memory Many programs then use the disk as both the source and the destination of their processing The higher levels are expensive but they are fast registers aIL n it A main memory i II H J V if gt Flash memory mildstare duh an d eeprom f H magnetic disk 7 ii optical diisk w 1 g magnetic tapes Figure 14 Etoigeidevice hierarchy Storage is of 2 types Volatile storage loses its contents when the power to the device is removed Non volatile storage data is retained after power loss as well In the absence of eXpensive battery and generator backup systems data must be written to non volatile storage for safekeeping Registers The top layer consists of the registers internal to the CPU They are made of the same material as the CPU and are thus just as fast as the CPU Consequently there is no delay in accessing them Cache Cache located inside or very close to the CPU When the program needs to read a memory word the cache hardware checks to see if the line needed is in the cache If it is called a cache hit the request is satisfied from the cache and no memory request is sent over the bus to the main memory Cache hits normally take about two clock cycles Cache misses have to go to memory with a substantial time penalty Cache memory is limited in size due to its high cost In any caching system several questions come up fairly soon including 1 When to put a new item into the cache 2 Which cache line to put the new item in 3 Which item to remove from the cache when a slot is needed 4 Where to put a newly evicted item in the larger memory You can have many levels of cache It begins from smaller in size to larger in size as the level progresses Caches are such a good idea that modern CPUs have two of them The first level or L1 cache is always inside the CPU The L1 caches are typically 16 KB each In addition there is often a second cache called the L2 cache that holds several megabytes of recently used memory words The difference between the L1 and L2 caches lies in the timing Access to the L1 cache is done without any delay ROM Read Only Memory is programmed at the factory and cannot be changed afterward It is fast and ineXpensive EEPROM Electrically Erasable PROM and ash memory are also non volatile but in contrast to ROM can be erased and rewritten Yet another kind of memory is CMOS which is volatile Many computers use CMOS memory to hold the current time and date CMOS memory can also hold the configuration parameters such as which disk to boot from Disks A disk contains more than 1 metal platters that rotate 54007200 and 10800 RPM or more At any given arm position each of the heads can read an annular region called a track Together all the tracks for a given arm position form a cylinder Each track is divided into some number of sectors typically 512 bytes per sector Spindle Head Pllatter Actuator Arrn Actuator Axis Power Connector Jumper Block Actuator IDE Connector i rireln io devices The CPU and memory are not the only resources that the operating system must manage IO devices also interact heavily with the operating system lO devices generally consist of two parts a controller and the device itself The controller is a chip or a set of chips that physically controls the device It accepts commands from the operating system for example to read data from the device and carries them out In many cases the actual control of the device is complicated and detailed so it is the job of the controller to present a simpler but still very compleX interface to the operating system A device controller maintains some local buffer storage and a set of special purpose registers The device controller is responsible for moving the data between the peripheral devices that it controls and its local buffer storage If you take controllers for hard disk The controller then has to convert this linear sector number to a cylinder sector and head This conversion may be complicated by the fact that outer cylinders have more sectors than inner ones and that some bad sectors have been remapped onto other ones Then the controller has to determine which cylinder the disk arm is on and give it a command to move in or out the requisite number of cylinders It has to wait until the proper sector has rotated under the head and then start reading and storing the bits as they come off the drive removing the preamble and computing the checksum Finally it has to assemble the incoming bits into words and store them in memory To do all this work controllers often contain small embedded computers that are programmed to do their work that is device driver Typically operating systems have a device driver for each device controller to perform these jobs There are three ways the driver can be put into the kernel The first way is to relink the kernel with the new driver and then reboot the system Many older UNIX systems work like this The second way is to make an entry in an operating system file telling it that it needs the driver and then reboot the system At boot time the operating system goes and finds the drivers it needs and loads them Windows works this way The third way is for the operating system to be able to accept new drivers while running and install them on the y without the need to reboot This device driver understands the device controller and provides the rest of the operating system with a uniform interface to the device To start an U0 operation the device driver loads the appropriate registers within the device controller The device registers are mapped into the operating system s address space the addresses it can use pci configuration space so they can be read and written like ordinary memory words Like memory mapped io or io mapped io ie this memory is actually in device only but it gives a virtual effect as if in ram The device controller in turn examines the contents of these registers to determine what action to take such as read a character from the keyboard The controller starts the transfer of data from the device to its local buffer Once the transfer of data is complete the device controller informs the device driver via an interrupt or polling mechanism that it has finished its operation The device driver then returns control to the operating system Programmed IO Programmed U0 PIO refers to data transfers initiated by a CPU under driver software control to access registers or memory on a device The CPU issues a command then waits for U0 operations to be complete As the CPU is faster than the IO module the problem with programmed U0 is that the CPU has to wait a long time for the U0 module of concern to be ready for either reception or transmission of data The CPU while waiting must repeatedly check the status of the U0 module and this process is known as Polling As a result the level of the performance of the entire system is severely degraded Programmed U0 basically works in these ways CPU requests U0 operation U0 module performs operation U0 module sets status bits CPU checks status bits periodically U0 module does not inform CPU directly IO module does not interrupt CPU IO module updates the status bit Interrupt The CPU issues commands to the IO module then proceeds with its normal work until interrupted by 10 device on completion of its work Although Interrupt relieves the CPU of having to wait for the devices but it is still inefficient in data transfer of large amount because the CPU has to transfer the data word by word between 10 module and memory Below are the basic operations of Interrupt CPU issues read command IO module gets data from peripheral to controller s buffer whilst CPU does other work IO module interrupts CPU o CPU must initialize transfer from controllers buffer to MM This form of interrupt driven U0 is fine for moving small amounts of data but can produce high overhead when used for bulk data movement such as disk IO Procedure 1 The driver tells the controller what to do by writing into its device registers The controller then starts the device 2 When the controller has finished reading or writing the number of bytes it has been told to transfer it signals the interrupt controller chip using certain bus lines 3 If the interrupt controller is ready to accept the interrupt which it may not be if it is busy handling a higher priority one it asserts a pin on the CPU chip telling it 4 The interrupt controller puts the number of the device on the bus so the CPU can read it and know which device has just finished many devices may be running at the same time 5 Once the CPU has decided to take the interrupt the program counter and PSW are typically then pushed onto the current stack and the CPU switched into kernel mode The device number may be used as an indeX into part of memory to find the address of the interrupt handler for this device This part of memory is called the interrupt vector Once the interrupt handler part of the driver for the interrupting device has started it removes the stacked program counter and PSW and saves them then queries the device to learn its status When the handler is all finished it returns to the previously running user program to the first instruction that was not yet executed Direct Memory Access DMA Direct Memory Access DMA means CPU sets up the DMA chip telling it how many bytes to transfer the device and memory addresses involved and the direction and lets it go When the DMA chip is done it causes an interrupt and grants UO module authority to read from or write to memory without involvement DMA module controls exchange of data between main memory and the U0 device Because of DMA device can transfer data directly to and from memory rather than using the CPU as an intermediary and can thus relieve congestion on the bus CPU is only involved at the beginning and end of the transfer and interrupted only after entire block has been transferred Direct Memory Access needs a special hardware called DMA controller DMAC that manages the data transfers and arbitrates access to the system bus The controllers are programmed with source and destination pointers where to readwrite the data counters to track the number of transferred bytes and settings which includes U0 and memory types interrupts and states for the CPU cycles DMA increases system concurrency by allowing the CPU to perform tasks while the DMA system transfers data via the system and memory busses Here DMA transfers data from controller buffer to MM and raises interrupt Each controller manufacturer has to supply a driver for each operating system it supports 1 inatruat an aaaaut an 1 a a atla f M I y matruatuana thraad at EKEGUEIGH V quoty am alata mauamam p 7 A data EPU N p 3 E j quot Flquot 39c 39 a a g HE mamaw aquot daaaa 2 p cm Figura 1 Haw a maarn aararautiarquot ayatam war39Iaa Buses This system has many buses e g cache memory PCIe PCI USB SATA and DMI each with a different transfer rate and function The operating system must be aware of all of them for configuration and management The main bus is the PCIe Peripheral Component Interconnect Express bus The PCIe bus was invented by Intel as a successor to the older PCI bus which in turn was a replacement for the original ISA Industry Standard Architecture bus Capable of transferring tens of gigabits per second PCIe is much faster than its predecessors Buses were parallel and shared A shared bus architecture means that multiple devices use the same wires to transfer data Thus when multiple devices have data to send you need an arbiter to determine who can use the bus A parallel bus architecture as used in traditional PCI means that you send each word of data over multiple wires For instance in regular PCI buses a single 32 bit number is sent over 32 parallel wires PCIe uses a serial bus architecture and sends all bits in a message through a single connection known as a lane much like a network Packet The USB Universal Serial Bus was invented to attach all the slow IO devices such as the keyboard and mouse to the computer Like usb lO20 and 30 The SCSI Small Computer System Interface bus is a highperformance bus intended for fast disks scanners and other devices needing considerable bandwidth The structure of a large X86 system 1331 rel GnuEB Beebe Game Shared cache PEI I EPFLJ bres I EI Eraphiea I HS Memory Memoryeo trollera HHS Memory EM PIEIa slot EMA F Ele slot Pla r m 115 20 parts E r li l39 lf F39Ele shot Hub Lia as parts I P Gle Eliot I FEIEI Eigebit Ethernet More F Ele devices Figure L11 The a i ne nrre of large 3E5 Harem How to switch to OS control is switched to the operating system via an interrupt a trap or a system call System calls provide the means for a user program to ask the operating system to perform tasks reserved for the operating system on the user program s behalf A system call usually takes the form of a trap to a specific location in the interrupt vector This trap can be executed by a generic trap instruction although some systems such as MIPS have a specific syscall instruction to invoke a system call When a system call is executed it is typically treated by the hardware as a software interrupt Control passes through the interrupt vector to a service routine in the operating system and the mode bit is set to kernel mode The system call service routine is a part of the operating system OPERATING SYSTEM ZOO Mainframe operating systems These computers differ from personal computers in terms of their lO capacity A mainframe with 1000 disks and millions of gigabytes of data is not unusual The operating systems for mainframes are heavily oriented toward processing many jobs at once most of which need prodigious amounts of U0 They typically offer three kinds of services batch transaction processing and timesharing Server Operating Systems They run on servers which are very large personal computers workstations or even mainframes They serve multiple users at once over a network and allow the users to share hardware and software resources Multiprocessor Operating Systems Get majorleague computing power is to connect multiple CPUs into a single system Depending on precisely how they are connected and what is shared these systems are called parallel computers multicomputers or multiprocessors They need special operating systems Personal Computer Operating Systems Their job is to provide good support to a single user They are widely used for word processing spreadsheets games and Internet access Modern ones all support multiprogramming Handheld Computer Operating Systems A handheld computer originally known as a PDA Personal Digital Assistant is a small computer that can be held in your hand during operation Smartphones and tablets are the best known examples Embedded Operating Systems Embedded systems run on the computers that control devices that are not generally thought of as computers and which do not accept userinstalled software Typical examples are microwave ovens TV sets cars DVD recorders traditional phones and MP3 players The main property which distinguishes embedded systems from handhelds is the certainty that no untrusted software will ever run on it SensorNode Operating Systems These nodes are tiny computers that communicate with each other and with a base station using wireless communication Sensor networks are used to protect the perimeters of buildings guard national borders detect res in forests The sensors are small batterypowered computers with builtin radios They have limited power and must work for long periods of time unattended outdoors frequently in environmentally harsh conditions The network must be robust enough to tolerate failures of individual nodes Each sensor node is a real computer with a CPU RAM ROM and one or more environmental sensors It runs a small but real operating system usually one that is event driven responding to external events RealTime Operating Systems Another type of operating system is the realtime system These systems are characterized by having time as a key parameter Often there are hard deadlines that must be met For example if a car is moving down an assembly line certain actions must take place at certain instants of time If for example a welding robot welds too early or too late the car will be ruined hard real time systems A soft realtime system is one where missing an occasional deadline while not desirable is acceptable and does not cause any permanent damage Smart Card Operating Systems The smallest operating systems run on smart cards which are creditcardsized devices containing a CPU chip They have very severe processing power and memory constraints Some smart cards are Java oriented This means that the ROM on the smart card holds an interpreter for the Java Virtual Machine JVM Java applets small programs are downloaded to the card and are interpreted by the JVM interpreter PROCESS A process is basically a program in execution Eg A word processing program being run by an individual user on a PC A system task such as sending output to a printer Associated with each process is its address space a list of memory locations from O to some maximum which the process can read and write The address space contains the executable program the program s data and its stack Also associated with each process is a set of resources commonly including registers including the program counter and stack pointer Only one process will run at one time Lets say multiple process are running The user may have started a Video editing program and instructed it to convert a one hour Video to a certain format something that can take hours and then gone off to surf the Web Meanwhile a background process that wakes up periodically to check for incoming email may have started running Thus we have at least three active processes the Video editor the Web browser and the email receiver Periodically the operating system decides to stop running one process and start running another based on time or space multiplexing A process is suspended temporarily like this it must later be restarted in exactly the same state it had when it was stopped This means that all information about the process must be explicitly saved somewhere during the suspension In many operating systems all the information about each process other than the contents of its own address space is stored in an operating system table called the process table which is an array of structures one for each process currently in existence Creation and termination of processes Consider a typical example A process called the command interpreter or shell reads commands from a terminal The user has just typed a command requesting that a program be compiled The shell must now create a new process that will run the compiler When that process has finished the compilation it executes a system call to terminate itself If a process can create one or more other processes referred to as child processes and these processes in turn can create child processes This communication is called interprocess communication Figure 113 A prooess tree Prooess orested two ohild prooesses B and E Process B crested three prooes ses I E 211411 Each person authorized to use a system is assigned a UID User IDentification by the system administrator Every process started has the UID of the person who started it A child process has the same UID as its parent Users can be members of groups each of which has a GID Group IDentification One UID called the superuser in UNIX or Administrator in Windows has special power and may override many of the protection rules A pipe is a sort of pseudofile that can be used to connect two processes as shown in Fig 1 16 If processes A and B wish to talk using a pipe they must set it up in advance When process A wants to send data to process B it writes on the pipe as though it were an output file Process 7 39 Pipe Figure 116 Two processes connected by a pipe PROTECTION Files in UNIX are protected by assigning each one a 9 bit binary protection code The protection code consists of three 3 bit fields one for the owner one for other members of the owner s group users are diVided into groups by the system administrator and one for everyone else Each field has a bit for read access a bit for write access and a bit for execute access These 3 bits are known as the rwx bits For example the protection code rwxrxx means that the owner can read write or execute the file other group members can read or execute but not write the file and everyone else can execute but not read or write the file For a directory x indicates search permission A dash means that the corresponding permission is absent SYSTEM CALL A dm39es xFFFFFFFF HEtUll39l l in caller Turaw In the Heml l Put Lila lnr mail inn regi ter lg Lier pr c um39e l mail 1 Llama Ep i llrmm39ement SFquot 11 Gall read FUEl ll f 3 USEquot mgram l lli lg Had I F Hamel 31333 3 33m can arming ay t m lt3 handler iquot Figure 111 quotElla 11 maps in making 533E111 gall f l d Hiram Ii 7 m POSIX Portable OS Interface management lEall eeeriptien pie tart Ereate a child preeeee itllentieal tn the parent pie waitpilpitl etatlee eptiene Wait fer a ehile te terrninate e eaeeveiname argtr ennitenp Fiepllaee a preeeee eelre image eaitietatue Terminate preeeee eneeutien anal return etatue File management l ail eeeri ptien fa epeni ille haw m pen a le ter reaing writing er bath e eleeeife Elleee an epen lille n manna buffer nbyteel Fieatl ate item a tile inte a batter n write better nbytee Write data trern a buffer inte a tile peeitien leeeltltal etfeet whenee Metre the tile peinter e etatlnai39ne abut Get a tile39e etatue intermatien ireetergr and tileeyetem management tall leaverip tien e mitiriname mee Ereate a new l39lirer39tinilr 5 Fmeirlnaime Hemeee an errietoglr directer e linkinarnet narneE Ereate a new entry nameE painting te nai39net 5 ll l i amei Fiemene a ElireIteIr3r entryr e meentiepeeiat narne tlag Meant a tile eyetern e urnenntepeeial Unmeunt a file eyetern Mieeellaneeue Ball eeeriptien a aheiileirnaine Ehange the wanking tillt39EClZ t39y e ehrneeiname mee Change a tile39e preteetien bite e killlpitl eignal Send a eignall te a preeeee eeeentlle tirnel eeeenaie Get the elapeeel tirne ein Jan 1 1 9 These calls are explained in the book go through net to know them Ll NIX Wi n33 e riptie n llerlt GreetelPreeeee Ereete e mew preeeee weilpid WeitFerEinglebjeet Ben 1irreit ller e preeeee te exit eeeeve neme EreeteF reeeee ferk exeeve exit Exithreeeee Terminate eeeeutien epen Greete lle Ereete e le er epen en eatieting le eleee IEileeeHelntzllle Eleee e ller reed FleedFile Heed tilete frern e llile wn e WriteFile Write date te e le leeek SetlFillePeinter the le peinter etet EetlFilleAtltributeeEx Get uerieue le etltributee mlkidir lET39lireeteE reeltse qr Create e mew Elllr li ry rlrndir Fllelr11e1rle ireeterillr Hemeve en erirlpgr tjlF eliret jtiarfs lr linlk nehe Win32 deee net euppert nite unlinlk eleteFille Deetrey en eeieting le meulnt nene Win32 deee net euppert rntrunt urneunt nelne Win32 deee net euppert rntrunt ee ne ulrneunt ehtllir Setl ulrrentireeterjalir Ehenge the Current werlting tllireeteryr ehmed nelne Win32 deee net euppert eeetiritglr eltheugh NT deee llllll nene Win32 deee net euppert eignele tirne EetLeeeWime Get the current time OPERATING SYSTEM STRUCTU RES Monolithic Entire operating system runs as a single program in kernel mode The operating system is written as a collection of procedures linked together into a single large executable binary program Being able to call any procedure you want is very ef cient but having thousands of procedures that can call each other without restriction may lead to a crash To construct the actual object program of the operating system when this approach is used one rst compiles all the individual procedures or the les containing the procedures and then binds them all together into a single executable le using the system anec In addition to the core operating system that is loaded when the computer is booted many operating systems support loadable extensions such as lO device drivers and le systems These components are loaded on demand In UNIX they are called shared libraries In Windows they are called DLLs DynamicLink Libraries They have le extension o land the C I Windo wslsystem32 d i recto ry on Windows systems has well over 1000 of them Layered Approach The operating system is divided into a number of layers levels each built on top of lower layers The bottom layer layer 0 is the hardware the highest layer N is the user interface A layered design of the operating system architecture attempts to achieve robustness by structuring the architecture into layers with different privileges The most privileged layer would contain code dealing with interrupt handling and context switching the layers above that would follow with device drivers memory management le systems user interface and nally the least privileged layer would contain the applications Layer lFuine39tieIn The epereter fl Lleer pregireme 3 Inpiutfeuiput management 2 pereteepreeeee eemmiuniieeiien 1 MElm ll39y39 and drum imeinegieimenil Preeeeeer elleeetiien einld imiuliiipregiremmiing l l Mitt393 j If Walnut 955 J g 7 ML E Egg i f rl 1 ilkv A i V J gun re 1 39 Eli 1114613quot 1 ll rates litEl a I l Elli PM i L ii m TllEE Jt l 4339 ii i u n aria llllt l ii I l ile lillrlllrigtliimil E lfljjljgre Mgnll lliira nlclint I we Sultanatit Si39 w Listenquot Eli furr 39i l or if 39 quot quot N Exlf llll i we HEWEI Subsystem j wnhyer l a Processucrlsl N Main il39rliemurjr Devices MULTICS is a prominent example of a layered operating system designed with eight layers formed into protection rings whose boundaries could only be crossed using specialized instructions MULTICS was described as having a series of concentric rings with the inner ones being more privileged than the outer ones which is effectively the same thing When a procedure in an outer ring wanted to call a procedure in an inner ring it had to make the equivalent of a system call that is a TRAP instruction whose parameters were carefully checked for validity before the call was allowed to proceed Although the entire operating system was part of the address space of each user process in MULTICS the hardware made it possible to designate individual procedures memory segments actually as protected against reading writing or executing MICROKERNEL The basic idea behind the microkernel design is to achieve high reliability by splitting the operating system up into small wellde ned modules only one of which the microkernel runs in kernel mode and the rest run as relatively powerless ordinary user processes In particular by running each device driver and le system as a separate user process a bug in one of these can crash that component but cannot crash the entire system Thus a bug in the audio driver will cause the sound to be garbled or stop but will not crash the computer In contrast in a monolithic system with all the drivers in the kernel a buggy audio driver can easily reference an invalid memory address and bring the system to a grinding halt instantly The bene ts of the microkernel are as follows o Extending the operating system becomes much easier o Any changes to the kernel tend to be fewer since the kernel is smaller o The microkernel also provides more security and reliability reeeee Lieem lpregreme Deer mede 1 Sewers Dmivere figmre 11215 Simp ed etmemre ef the eyetem ClientServer Model two classes of processes the servers each of which provides some service and the clients which use these services This model is known as the clientserver model Communication between clients and servers is often by message passing To obtain a service a client process constructs a message saying what it wants and sends it to the appropriate service The service then does the work and sends back the answer An obvious generalization of this idea is to have the clients and servers run on different computers connected by a local or widearea network requests are sent and replies come back Thus the clientserver model is an abstraction that can be used for a single machine or for a network of machines Machine 1 Machine 2 Machine 3 Machine 4 Client 4 4 File eeiwer Preceee eem39eer 39ll39eil39minl SEWEI I Kernel J Kernel Kernel lliernel lll39sletwerlt Meeeage frem client in server Figure ll12 quotI39llc client settler me cl ever a netwerik VIRTUAL MACHINES Virtual machines allow you to run other operating systems within your current operating system the operating systems will run as if they re just another program on your computer Virtual machines are ideal for testing out the products in other operating systems The computer on which virtual machine is running is called host OS the OS in virtualbox is called guest OS the quothostquot operating system provides virtual hardware to guest operating systems The guest operating system runs normally as if it were running on a physical computer from the guest operating system s perspective the virtual machine appears to be a real physical computer Virtual machines provide their own virtual hardware including a virtual CPU memory hard drive network interface and other devices The virtual hardware devices provided by the virtual machine are mapped to real hardware on your physical machine For example a virtual machine s virtual hard disk is stored in a le located on your hard drive A hypervisor also called a virtual machine manager is a program that allows multiple operating systems to share a single hardware host Each operating system appears to have the host39s processor memory and other resources all to itself However the hypervisor is actually controlling the host processor and resources allocating what are needed to each operating system in turn and making sure that the guest operating systems called virtual machines cannot disrupt each other Eg A hypervisor is software that exists outside of a guest operating system to intercept the commands sent to the computer hardware
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