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# UIUC - ECE 120 - Class Notes - Week 7

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UIUC - ECE 120 - Class Notes - Week 7

##### Description: Notes from week 7
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##### Description: Notes from week 7
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• Notes, Study Guides, Flashcards + More!

Unformatted text preview: Skading A Bit Combinations output Input where do these come from? Switches thesocother Citwits Sequential Logic stones bits as statos its behavis depends on Value of the stored bats the Outpute flinput, State What does this count ? The outputs serve as inputs Lohen Q2 Ply the state is stable biu these values do not continue to change forums.co P ro is also a stable State But how do we set Lets andd ar put the values for Q ? 51 P Q 1! 2 X Oli Posao TO . We Say 2 S sets the 614 LO to 1 The 3 achon induced by Ster) the bit Q - Ours when 3 0 Sinething happeng wien Signal 5 is low) We Sou3 ismeretive low cuorewhat if R0.05 Pel! Lane Qre, Sou Brebes the bit Q to o This circuit is called 2-5 latchi Meta stabve - loop may not get the info digital Voltages Rexp changing between SO, *DO NOT Low BOTH INPUTS AT ONCEK to la To prevent setting both entregates... 5 ...... clobal Now only I input tohto the gute Q De Now Garte lopies Dushen Wellcircuit stores last volve from D. cathed A GATED D- LATCH OUTelow Notice has been replaced by Q gated D. Latch -D WE < Clock Abstraction A_et_otwithus serves as inputs to combinational logie, and the outportare stored in latenus SOOBCombinatie DBQ A clock signal is used to drive the WE imports of the latches; ideallya Square wiane We combine consecutive sets of latches into "flip flops - Master stare implementation - Positive -edge triggered D_Flip_flop? ative

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