Limited time offer 20% OFF StudySoup Subscription details

UIUC - ECE 120 - Class Notes - Week 7

Created by: Megh Shah Elite Notetaker

UIUC - ECE 120 - Class Notes - Week 7

School: University of Illinois at Urbana-Champaign
Department: Electrical Engineering
Course: Introduction to Computing
Professor: Suma Bhat
Term: Fall 2018
Tags: ECE, Engineering, and Computer
Name: ECE120 Week 7 Notes
Description: Notes from week 7
Uploaded: 10/17/2018
This preview shows pages 1 - 2 of a 2 page document. to view the rest of the content
Scanned by CamScanner
Scanned by CamScanner

This is the end of the preview. Please to view the rest of the content
Join more than 18,000+ college students at University of Illinois at Urbana-Champaign who use StudySoup to get ahead
2 Pages 50 Views 40 Unlocks
  • Better Grades Guarantee
  • 24/7 Homework help
  • Notes, Study Guides, Flashcards + More!
Join more than 18,000+ college students at University of Illinois at Urbana-Champaign who use StudySoup to get ahead
School: University of Illinois at Urbana-Champaign
Department: Electrical Engineering
Course: Introduction to Computing
Professor: Suma Bhat
Term: Fall 2018
Tags: ECE, Engineering, and Computer
Name: ECE120 Week 7 Notes
Description: Notes from week 7
Uploaded: 10/17/2018
2 Pages 50 Views 40 Unlocks
  • Better Grades Guarantee
  • 24/7 Homework help
  • Notes, Study Guides, Flashcards + More!

Unformatted text preview: Skading A Bit Combinations output Input where do these come from? Switches thesocother Citwits Sequential Logic stones bits as statos its behavis depends on Value of the stored bats the Outpute flinput, State What does this count ? The outputs serve as inputs Lohen Q2 Ply the state is stable biu these values do not continue to change forums.co P ro is also a stable State But how do we set Lets andd ar put the values for Q ? 51 P Q 1! 2 X Oli Posao TO . We Say 2 S sets the 614 LO to 1 The 3 achon induced by Ster) the bit Q - Ours when 3 0 Sinething happeng wien Signal 5 is low) We Sou3 ismeretive low cuorewhat if R0.05 Pel! Lane Qre, Sou Brebes the bit Q to o This circuit is called 2-5 latchi Meta stabve - loop may not get the info digital Voltages Rexp changing between SO, *DO NOT Low BOTH INPUTS AT ONCEK to la To prevent setting both entregates... 5 ...... clobal Now only I input tohto the gute Q De Now Garte lopies Dushen Wellcircuit stores last volve from D. cathed A GATED D- LATCH OUTelow Notice has been replaced by Q gated D. Latch -D WE < Clock Abstraction A_et_otwithus serves as inputs to combinational logie, and the outportare stored in latenus SOOBCombinatie DBQ A clock signal is used to drive the WE imports of the latches; ideallya Square wiane We combine consecutive sets of latches into "flip flops - Master stare implementation - Positive -edge triggered D_Flip_flop? ative

Join StudySoup for FREE
Get Full Access to UIUC - Class Notes - Week 7
Join with Email
Already have an account? Login here
×
Log in to StudySoup
Get Full Access to UIUC - Class Notes - Week 7

Forgot password? Reset password here

Forgot password? Reset your password here

I don't want to reset my password

Need help? Contact support

Need an Account? Is not associated with an account
Sign up
We're here to help

Having trouble accessing your account? Let us help you, contact support at +1(510) 944-1054 or support@studysoup.com

Got it, thanks!
Password Reset Request Sent An email has been sent to the email address associated to your account. Follow the link in the email to reset your password. If you're having trouble finding our email please check your spam folder
Got it, thanks!
Already have an Account? Is already in use
Log in
Incorrect Password The password used to log in with this account is incorrect
Try Again

Forgot password? Reset it here