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Introd to Digital Logic Design

by: Melissa Metz

Introd to Digital Logic Design EECS 140

Marketplace > Kansas > Elect Engr & Computer Science > EECS 140 > Introd to Digital Logic Design
Melissa Metz
GPA 3.74

James Sterbenz

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James Sterbenz
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This 2 page Study Guide was uploaded by Melissa Metz on Monday September 7, 2015. The Study Guide belongs to EECS 140 at Kansas taught by James Sterbenz in Fall. Since its upload, it has received 45 views. For similar materials see /class/184022/eecs-140-kansas in Elect Engr & Computer Science at Kansas.

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Date Created: 09/07/15
Prof James PG Sterbenz KU EECS 140 Exam 2 Study Guide 25 November 2008 Brown and Vranesic Chap 475 Chapter 3 Implementation Technology 388 Tristate buffers 0 implementation function and symbols 0 multiplexor construction 39 Transmission gates 0 implementation function and symbols 0 multiplexor construction Chapter 4 Optimized Implementation of Logic Functions 41 Karnaugh maps 0 2 3 4 and 5 variable SOP maps 42 Minimization strategy 0 terminology literal implicant prime implicant cover cost 0 procedure circle primeimplicant groups of minterms to cover 43 Productofsums 0 minimization procedure circle group of maXterms and invert each literal 44 Incompletely speci ed functions 0 minimization procedure circle don t care terms as needed to optimize cover 45 Multiple outputs 0 minimization procedure match covers across multiple maps 46747 Multilevel synthesis 0 factoring to reduce fanin and increase levels 0 functional decomposition 0 multilevel NAND and NOR circuits 0 add bubble pairs 0 add input and output inverters when necessary 0 multilevel analysis of subfunctions 48 Cubical representation 0 cubes and hypercubes 0 minterms as ve1tices 0 functions as sets of shaded ve1tices segments planes and hyperplanes Prof James PG Sterbenz KU EECS 140 Exam 2 Study Guide Chapter 5 Number Representation and Arithmetic Circuits 51 Number representation 0 unsigned integers representation and binardeecimal conversion 0 octal and hexadecimal representation and conversion 52 Addition of unsigned numbers 0 singlebit addition sum and carry bits 0 halfadder truth table and logic circuit 0 singlebit addition with carryin quickly derive or memorize O Si xi 9 93 Ci CH1 xiyi xiCi ini 0 full adder truth table and logic circuit 0 construction from two half adders 0 multibit addition ripplecarry adder 53 Signed numbers 0 signmagnitude representation sign bit 0 l s complement representation complement bits 0 2 s complement representation l s complement l 0 rule for fast computation copy all BS and first 1 from right invert rest l s complement and 2 s complement addition 2 s complement subtraction adder symbol W with inputs and outputs including carryin and over ow adder and subtractor construction from adder with XOR gates arithmetic over ow performance problems of ripplecarry 54 Fast adders 0 carry propagate and generate quickly derive or memorize 0 CH1 gi PiCi gi xiyi Pi xi H4 0 carrylookahead adder logic circuit 57 Other representations 0 fixed point numbers radix point and alignment oating point numbers iM XRie 0 single precision format memorize BCD representation and conversion ASCII representation 0 letters numbers punctuation and control symbols you do not need to memorize ASCII values for these 0 parity generation and checking of even and odd parity


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