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Computer Architecture

by: Nick Rowe

Computer Architecture CS 25000

Nick Rowe
GPA 3.68


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This 8 page Study Guide was uploaded by Nick Rowe on Saturday September 19, 2015. The Study Guide belongs to CS 25000 at Purdue University taught by Staff in Fall. Since its upload, it has received 102 views. For similar materials see /class/208100/cs-25000-purdue-university in ComputerScienence at Purdue University.

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Date Created: 09/19/15
PURDUE 08250 Computer Architecture Review Prof Chris Clifton Apr2327 2007 Grading L 10 Written assignments equally weighted lowest score drop ed 33 Labs equally weighted lowest score dro ped 16 Midterm Exam t 1 quot3 J 2 m 9 N 2 Evaluation of instructors based on in classlab contributions discussions and overall performance 2525 spring mm r Pu r39 r 9 9quot Old Conventional Wisdom Reliable internally errors at pins Power free transistors expensive Multiples slow loads fast Instructionlevel parallelism 2l15 years improvement UniprocessorCluster Sea Change in Architecture Patterson 2002 New Conventional Wisdom lt65NM softhard error rates Transistors free power expensive Loads slow Multiplies 200 cycles to DRAM 4 for PP mult Diminishing returns from lLP 2l5 years improvement Multicore 08250 Spring 2007 Gates Andorxornot Multiinput andor FlipFlops Digital Hardware Transistors RTL and TTL logic Recognizeconstruct basic gates Schematic representation Recognizeunderstand feedback circuits Construct simple circuits eg SR latch 08250 Spring 2007 Digital Logic Truth Table Karnaugh Map Boolean Algebra Basic properties DeMorgan s Theorem Understanding Feedback Clocked Circuits 08250 Spring 2007 Data Representation Binary Hex Decimal 7 Integer Representations Unsigned Approaches to signed Implications for arithmetic Character Representations ASCII chart might be handy IEEE Floating Point ltsigngt x 2lt8 bi eXP emgt39127 x 1lt23bit mantissagt Recognizing in Memory Dump 08250 Spring 2007 Processor Organization Von Neumann Architecture Processormemory Stored Program Computer 39 CPU Register ALU controller Microcode Processor modes protection CS250 Spring 2007 CPU ALU Operations Registers Banks windows special purpose Instruction processing FetchExecute Cycle Pipelines Instruction Set Arithmetic Logical Memory Control Flow Floating Point Processor Control CS250 Spring 2007 Assembly Language r39 9 w s p Instruction format Label Instruction Operands Register Immediate Memory Addressing Modes Specified vs Computed Register Registeroffset Direct vs Indirect 08250 Spring 2007 Assembly Language cont Flow of control Branch vs jump Conditional branches and condition codes Subroutines Argument passing Function results Return address handling 08250 Spring 2007 a Assembly Language cont 7 e Data Data vs code sections Alignment issues Macros Microcoded Architectures Instruction setquot directly mapped to hardware Horizontal vs Vertical microcode 08250 Spring 2007 Memory Types of memory hardware issues Static vs dynamic ram Performance characteristics Addressing Processor vs Memory word How this affects alignment Memory Controller Banks interleaving 08250 Spring 2007 Virtual Memory Virtual vs Physical address Basebound Page table Translation Lookaside Buffer Paging disk storage Cache and interaction with Virtual Memory Performance Estimating performance of multilevel memory CS250 Spring 2007 13 lO Devices and Drivers Interface types Parallel Serial Bus Architectures Fetchstore operations Memorymapped lO Interrupts vs Polling Buffers CS250 Spring 2007 14 Parallelism Parallel architectures Multicore Multiprocessor Cluster Pipelining Instructionlevel As a paradigm for using parallel architectures Performance Assessment 08250 Spring 2007 Exam Hints Be There 430 190021 00 SC239 Open Book Open Note No electronic aids Time will be tight You won t be able to look everything up need to know it Don t get stuck do what you know well first If something doesn39t make sense speak up Read last year s final exam at the web site 08250 Spring 2007


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