Design of Complex Digital Systems
Design of Complex Digital Systems ECE 406
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This 4 page Study Guide was uploaded by Miracle Jaskolski on Thursday October 15, 2015. The Study Guide belongs to ECE 406 at North Carolina State University taught by William Davis in Fall. Since its upload, it has received 49 views. For similar materials see /class/223890/ece-406-north-carolina-state-university in ELECTRICAL AND COMPUTER ENGINEERING at North Carolina State University.
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Date Created: 10/15/15
NC State University ECE 406 Spring 2008 ECE Department Design of Complex Digital Systems W Rhett Davis Exam 2 Study Guide The exam will be 75 minutes You may either a bound set of notes in a binder or a textbook into the exam not both Loose sheets of paper or multiple bound sets of notes will not be allowed No communication devices are allowed laptops PDA s cellphones The exam will cover the material from Lectures 814 and Homeworks 46 I will expect you to be able to do the following on the midterm Draw a circuit to match a given Verilog behavior HW 4 problem 2 Draw the waveforms for a given Verilog behavior HW 4 problem 4 Identify Errors in code and correct them Synthesis Tutorial Q5 0 Incorrect use of nets wire amp reg o Incomplete sensitivity lists 0 Unintentional wiredOr Logic multiple assignments to the same signal 0 Unintentional Latches Recognize when a synchronous reset signal is needed for correct simulation and be able to implement it HW4 problem 3 clear Write a Verilog description for a simple module from a speci cation HW4 problem 3 HW5 problem 2 Create the machinecode for an LC3 instruction from an assemblylanguage instruction and viceversa HW6 problems 1 amp 2 Execute an LC3 assemblylanguage program and tell the state of the registers and memory at the end of the program HW6 problem 2 Report the number of ip ops speci ed by a segment of Verilog code and suggest the minimum number of ip ops needed to implement a certain function Synthesis Tutorial Q2 Explain the difference between a latch and a ip op The best possible preparation for this exam is to spend 75 minutes taking the Spring 2007 or 2006 Exam 2 sample test and then check your answers with the solution NC State University ECE 406 Spring 2008 ECE Department Design of Complex Digital Systems W Rhett Davis Exam 1 Study Guide The exam will be 75 minutes You may either a bound set of notes in a binder or a textbook into the exam not both Loose sheets of paper or multiple bound sets of notes will not be allowed No communication devices are allowed laptops PDA s cellphones The exam will cover the material from Lectures l7 not including ip ops and Homeworks 13 There will be four main types of questions 0 Short answer Questions 0 Drawing waveforms to match a behavior 0 Drawing a schematic to match code or behavior 0 Write code to match a schematic or behavior Grading Scheme The goal in grading is to determine if you are able to design hardware which includes drawing schematics writing code and comprehending or correcting existing schematics and code with the following three key qualities 0 Lack of signi cant schematic syntactical or behavioral errors Examples of such errors include the following 0 Using a bus when only a single wire is appropriate 0 Drawing a waveform that evolves with the clock when there is no clock present 0 Writing code that does not correspond to any real hardware 0 Writing code that represents latches unintentional or otherwise Completeness that is the ability to draw schematics or write code that has no major parts missing Examples of incompleteness include the following 0 Missing input and output ports 0 Forgetting to declare reg variables for assignments made in always blocks 0 Leaving blocks of hardware unconnected in a schematic o Omitting signals from an always sensitivity list 0 Not implementing a large section of the required functionality Matches the desired functionality Examples of incorrect functionality would include the following o A counter that counts up when it should count down 0 Implementing a receiver when you were asked to implement a transmitter o A state machine that never reaches some of its states 0 Incorrect interpretation of the order of blocking or nonblocking assignments My intention in grading is that if demonstrate all three of these are clearly demonstrated then you will get an A 90 100 two out ofthree is a B 8090 1 out of3 is a C7080 and none will be a D or lower less than 70 In addition there are the following two criteria 0 Lack of careless errors If a certain error represents carelessness rather than a lack of understanding my intention is that it will affect the grade rather than the letter grade However a large number of aggregated careless errors can pull your score down by a letter grade 0 Clarity neatness If I can t read it I ll assume that it s wrong NC State University ECE Department ECE 406 Design of Complex Digital Systems Spring 2008 W Rhett Davis Covered Material I will expect you to be able to do the following on the midterm Explain what Hardware Description Languages are and why we use them Lec 1 Identify ports nets symbols and instances in a schematic Lec 1 Declare variables of various types and assign literal values Lec 2 Identify a value in a circuit schematic as being 0 lx or 2 Lec 2 Explain the difference between a reg variable and a wire variable Lec 2 Identify errors in code in which the port connection rules are violated Lec 3 Write expressions to assign or access individual bits in vectors Lec 3 Write a complete Verilog module when given a functiondescription or a blockdiagram 0 at a gatelevel using primitives Lec 3 0 using module hierarchy Lec 3 0 at a data ow level using expressions Lec 45 0 at a procedural level using always blocks Lec 6 Write Verilog descriptions using the operators discussed in Lec 5 including bitwisereduction and or xor not ampl logical shift ltltgtgt arithmetic conditional logical andornot ampampH relational and equalityinequality gtgtltlt concatenation and replication You may ignore the following arithmetic shifts ltltltgtgtgt and case equalityinequality Draw a schematic for a module when given its Verilog description or a specification Lec 57 Avoid the common pitfalls of procedural design Lec 6 o Unintentional Latches o Incomplete sensitivity lists Explain the differences between Verilog code written for synthesizable modules and test bench modules Write down the output of simulation when given a module description and testbench Lec 4 Be familiar with MUXes Lec 3 0 Draw logic diagrams at the gatelevel 0 Draw more complex circuits that use MUX blocks 0 Do these for different sizes of MUXes 2tol 4tol etc 0 Do these also for different bitwidths lbit 2bit 4bit etc Be familiar with adders and multipliers o Correctly evaluate verilog expressions even when the operands have mis matching vector sizes Lec 56 0 Draw a circuit to generate the 2 s complement of a binary number Write the code to model a ripplecarry adder complete with carryout bit which can be thought of as unsigned over ow Lec 56 0 Write the code to model signed over ow Lec 7 0 Practice Problems Work through the suggested problems from Examl in 20042007 along with the GateLevel Design Practice problems under the Exams section of the course webpage NC State University ECE 406 Spring 2008 ECE Department Design of Complex Digital Systems W Rhett Davis Final Exam Study Guide The exam will be 3 hours open book and open notes You may either a bound set of notes in a binder or a textbook into the exam not both Loose sheets of paper or multiple bound sets of notes will not be allowed No communication devices are allowed laptops PDA s cell phones The Exam will be held in 1005 EBl l4pm on Tues Apr 29 Sit so that there is at least one seat vacant seat between each person in the back two rows Roughly half of the exam will be on material covered on the previous two exams while the other half will focus on new material This includes Lectures 1520 and Homeworks 78 including the LC3 microarchitecture but not the Uni ed Cache microarchitecture I will expect you to be able to do the following on the nal exam 0 Modify the LC3 Microcontroller Data Path and or Controler StateMachine to implement a new instruction and explain how to set the control signals HW7 NOTE The schematics and statemachine for the LC3 will be reprinted on the exam but they will be very small If you need larger diagrams be sure to bring copies with you 0 Identify initiator response and control level of an interface Also be able to identify the responsive pairs 0 Given a description of an interface and protocol draw the diagram waveforms and state diagram and write the partial Verilog code for that interface HW8 problems 13 0 For a given address and cache architecture in terms of mainmemory size cache size and blocksize identify the offset index and tagbits for that address Also be able to identify the size of CacheRAM that is needed 0 Execute a short LC3 program and show the cacheoperations that occur readhit read miss writehit or writemiss and give the contents of the CacheRAM and Valid Array after execution HW8 problem 4 The best possible preparation for this exam is to spend 3 hours taking the Spring 2007 Final Exam sample test and then check your answers with the solution In addition the Spring 2006 final is also representative of this exam
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