VLSI Systems Design
VLSI Systems Design ECE 546
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This 6 page Study Guide was uploaded by Miracle Jaskolski on Thursday October 15, 2015. The Study Guide belongs to ECE 546 at North Carolina State University taught by William Davis in Fall. Since its upload, it has received 30 views. For similar materials see /class/223891/ece-546-north-carolina-state-university in ELECTRICAL AND COMPUTER ENGINEERING at North Carolina State University.
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Date Created: 10/15/15
NC State University ECE Department ECE 546 VLSI Systems Design Final Exam Study Guide Fall 2008 W Rhett Davis The following rules will be enforced during the exam The nal exam will be closedbook closednotes You may not have any articles on the table except writing implements a calculator and two cribsheets two single sheets of paper with notes two sided It is expected that the first cribsheet will be the one you used for the midterm exam The exam will be 3 hours and no extra time will be given Only one person will be allowed to go to the restroom at a time Please come to the front of the room and ask for an escort There will be assigned seating Please refer to the seating chart at the end of this study guide and the email that is sent to you with your seat location Photos of the room will be taken during the exam to ensure that seat assignments are observed Combinational Logic 61634 Be able to connect the clock to a dynamic gate and identify the precharge and evaluate phases Be able to compute the change in output voltage AVout due to chargesharing for a dynamic gate and be able to determine if complete or partial charge sharing has occurred Be able to nd the input sequence that causes the worstcase chargesharing drop in Vout Sequential Circuits 71733 75752 1011033 Be able to identify a memorycircuit as edgetriggered levelsensitive static dynamic loop breaking or loopforcing Be able to draw the waveforms for the internal nodes of a static or dynamic ip op from a circuit diagram Be able to design a latchbased pipeline so that it is insensitive to clockoverlap by using CZMOS latches with alternating phases and noninverting logic between them Be able to determine the timing constraints for a synchronous circuit with a singlephase clock in terms of setup time hold time clock skew propagation criticalpath delay and contamination shortestpath delay Be able to determine the minimum clock period and the maximum skew before races occur Arithmetic Circuits 1111133 Be able to recognize the following arithmetic circuits and identify the main advantagesdisadvantages in terms of speed and area of each one o Adders ripple carry carrybypass carryskip carryselect carrylookahead carrysave compressor 0 Multipliers array carryskip Be able to estimate the criticalpath delay for a circuit given a transistorlevel circuit and equivalent R and C values to model each transistor a gatelevel circuit and delay values to model each gate NC State University ECE Department ECE 546 VLSI Systems Design Fall 2008 W Rhett Davis Memory 1211221 1223 1231231 Be able to draw the waveforms for a read operation in a ROM and both read and write operations in an SRAM 3TDRAM and lTDRAM Be able to compute the time needed for a ROM SRAM or 3TDRAM cell to cause a certain voltage drop on its bitline Be able to calculate the time needed for a decoder to raise or lower a wordline including both the static and dynamic decoder structures discussed in class Be able to calculate the time needed for an SRAM cell to raise or lower a bitline modeled as a lumped capacitor or through a column decoder as discussed in class Be able to set up the equations to determine if an SRAM cell is susceptible to a readupset and if a write operation will be successful Be able to compute the voltage drop or rise on a bitline in a ltransistor DRAM cell The following problems will best help prepare you for the midterm 2007 Final 2006 Final 2006 Midterm Problem 5 only 2005 Final 2005 Midterm Problem 5 only 2004 Final Problems 1 2 amp 4 2004 Midterm Problem 5 only 2003 Final Problems 2 3 part c only amp 4 2003 Midterm Problems 3 amp 5 NC State University ECE Department Seating Diagram of 1011 EB1 ECE 546 Back of classroom VLSI Systems Design Fall 2008 W Rhett Davis H1 H2 H3 H 4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 H23 H24 rolling chair G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F 13 F14 F15 F16 F17 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 rolling chair Front of classroom rolling chair rolling chair NC State University ECE 546 Fall 2008 ECE Department VLSI Systems Design W Rhett Davis Midterm Study Guide The following rules will be enforced during the exam 0 The midterm will be closedbook closednotes 0 You may not have any articles on the table except writing implements a calculator and a cribsheet a single sheet of paper with notes two sided See the sample cribsheet for an example of what is expected though it is suggested that you make your own 0 The exam will be 75 minutes and no extra time will be given Restroom breaks will not be allowed Please use the restroom before the exam There will be assigned seating Please refer to the seating chart at the end of this study guide and the email that is sent to you with your seat location 0 Photos of the room will be taken during the exam to ensure that seat assignments are observed The exam will have 45 questions drawn from the major areas listed below I will expect you to be able to do the following covered sections of the textbook are in parentheses Device Models 323332 0 Be able to use the Unified Transistor Model with HandAnalysis Parameters to compute drain current ID for a transistor Be able to identify the region of operation of a transistor in terms of the Unified Model cutoff linear triode saturation velocity saturation Be able to compute Req in terms of R0 and Rmid Be able to compute the change in VT due to the body effect andor DIBL Be able to calculate CGS CGD CGB CSB amp CDB for a transistor using simplified equations such as laFnm of gate width as in HW4 Probl the complete equations will not be expected Be able to extract As AD PS amp PD values from a layout Wires 41432 44444 452 Be able to extract Rwire and Cwire in terms of cam Cfringe cup cdown cadj RD and Rmmm Be able to draw a complex wire as an RCtree of combined 11 models and compute Elmoredelay Be able to compute the delay using an equivalent capacitance of a victim wire when an aggressor wire is switching with a known risefall time Lecture 6 Inverters 51532 54543 55554 0 Be able to identify VM VIL VIH VOH and VOL on a Voltage Transfer Characteristic VTC Plot Be able to compute propagation delay tp of a circuit in terms of Req Be able compute the total power of a circuit P101 Pay PS PM CLVDD2 VDDIpemscfo1VDDIIeak NC State University ECE 546 Fall 2008 ECE Department VLSI Systems Design W Rhett Davis 0 Be able to compute the effective load capacitance CL for an inverter loaded with an identical inverter 0 Be able to explain why an inverter sized for minimum and equal propagation delay tp will have different values of l WpWn 0 Be able to size a chain of inverters to drive a large load with minimum delay and be able to compute the delay F CLCin for chain f N F CLCin for stage Wnext stage wmv stage tp tpo 1 fy for each stage Combinational Logic 61634 0 Be able to draw the circuit diagram for a Complementary CMOS gate from a Logic Function and vice versa 0 Be able to compute the propagation delay for a Complementary CMOS gate 0 Be able to suggest ways to arrange and size Complementary CMOS gates for less delay 0 Be able to size a chain of Complementary CMOS gates to drive a large load with minimum delay using the method of Logical Effort 0 Be able to identify a gate from a plot of fanout vs delay by identifying the different values from the Logical Effort delay formulation tpo p and g 0 Be able to find the voltage swing of a passtransistor logic gate 0 Be able to find the delay of passtransistor gates 0 Be able to recognize the VTdrop problem in passtransistor gates compute the associated static power consumption and suggest circuit modifications to fix the problem 0 Be able to determine the logic function of a passtransistor gate Layout Appendix D 0 Be able to find the dual of a PDN with a logic diagram 0 Be able to find consistent Euler Paths from a logic diagram and draw the stickdiagram for its layout The following problems will best help prepare you for the midterm 2007 Midterm 2006 Midterm Problems 14 2005 Midterm Problems 14 2004 Midterm Problems 14 2004 Final Problem 3 only 2003 Midterm Problems 12 and 4 NC State University ECE 546 Fall 2008 ECE Department VLSI Systems Design W Rhett Davis Seating Diagram of 1011 EB1 Back of classroom H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 H23 H24 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11G12 G13 G14G15 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 r quot39rTg E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 r quot39rTg chalr chalr D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 rollin rollin 9 Front of classroom 9 chalr chair
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