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Digital Integ Circuits

by: Cassidy Effertz

Digital Integ Circuits ECE 4420

Cassidy Effertz

GPA 3.64

Jeffrey Davis

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Jeffrey Davis
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This 0 page Study Guide was uploaded by Cassidy Effertz on Monday November 2, 2015. The Study Guide belongs to ECE 4420 at Georgia Institute of Technology - Main Campus taught by Jeffrey Davis in Fall. Since its upload, it has received 18 views. For similar materials see /class/233869/ece-4420-georgia-institute-of-technology-main-campus in ELECTRICAL AND COMPUTER ENGINEERING at Georgia Institute of Technology - Main Campus.



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Date Created: 11/02/15
VLSI Processing Study Guidef T These terms and de nition were taken verbatim from two smrces I Uyemura J Introduction to VZSI Circu its and Systems John Wiley amp Sons New York 2002 2 The glossary of the online publication Semicontimes which is mnd at wwwsemicontimescomcommonglossaryasp wafer starts per weekor month This is a measure of the capacity of chip factory and is equal to the number of fresh wafers that are introduced into the fabrication sequence each week Typically takes a few weeks to nish a batch Typical wafer starts per week for a highvolume fabrication facility is 5000 per week or 20000 per month TSMC 39w Semiconductor Manufacturing Company Fab 6 190000 square feet has 50000 wafer starts per month on 8inch wafers FYI Fab 6 is a 2 billion dollar plant Yield The yield ofis de ned as the percentage ofthe die on a wafer that are knowngood die KGD TSMC 130nm wafers 20K wafer starts per month Started at 50 yield early 2002 and reached 70 yield by the end of the year Motorola used TSMC to make DSP processor claimed to reach 90 yields NVIDIA GeForce FX yield was rumored to be low Dec 192003 NVIDIA GeForce FX 5700 at IBM plant 130nm 65 days production NVIDIA GeForce FX 5960 Ultra at TSMC 130nm 80 days prodcution 20 higher yield Defect density This is the average number of defects per cm2 on the wafer This is due to the random imperfections that occur in every crystal wafer Thermal Oxide Silicon Dioxide layer grown with heat as a catalyst to combine oxygen and silicon With pure oxygen this is a slow reaction but can result in a very highquality oxide quotWet Oxidation can be used to grow a thick layer of oxide quickly Native Oxide This is an oxide layer that occurs naturally on the silicon surface The Thermal Oxide is a native oxide Typical value of8501100 C are used to grow this oxide Chemical Vapor Deposition CVD A vapor transport mechanism in which the gaseous reactants decompose and recombine to form some desired thin lm Decomposition and reaction are helped by having a heated substrate CVD is a process whereby a lm is deposited by reacting chemicals together in the gaseous or vapor phase to form a lm The gases or vapors utilized for CVD are compounds that contain the element to be deposited and that may be induced to react with a substrate or other gases to deposit a lm The CVD reaction may be thermally activated plasma induced plasma enhanced CVD or activated by light in photon induced CVD See also Atmospheric Chemical Vapor Deposition Low Pressure Chemical Vapor Deposition Metal Organic Chemical Vapor Deposition Photo Enhanced Chemical Vapor Deposition CVD Oxide There are oxide layers deposited well above the wafer surface These are deposited using silane SiH4 deposited with oxygen Because these reactions can occur at low temperatures these oxides are also referred to as LTO lowtemperature oxides Silicon Nitride Si3N4 This is often called nitride Nitrides are unique in that they act as strong barrier to atom The dielectric constant is higher that oxide It has a relative dielectric constant of 78 They are used as onchip capacitors esp DRAMs overglass This layer which is usually silicon nitride is put as a protective coating over the entire chip electromigration The migration of atoms in a metal interconnect line due to momentum transfer from conduction electrons The metal atoms migrate in the direction of current ow and can lead to failure of the metal Line Electromigration depends on the metal in use with a fairly good correlation to the melting temperature of the metal higher me 39ng temperatures generally correspond to higher electromigration resistance temperature higher is worse and current density higher is worse Electromigration may be due to diffusion in the bulk of the material the grain boundaries or on the surface Aluminum electromigration is primarily grain boundary due to the higher grain boundary diffusivity over the bulk diffusivity and the excellent surface Passivation effect of aluminum oxide that forms on the aluminum surface when exposed to oxygen Copper on the other hand has lower bulk and grain boundary electromigration and primarily exhibits electromigration on the surface due to poor copper oxide passivation properties voids Pits formed in metals due to electromigration hillocks Mounds of metal ions that can form on a conductor due to electromigration refractory metal T itaniumCT i Tungsten W platinum Pt A metal with a very high melting point such as tungsten molybdenum tantalum niobium chromium vanadium and rheniurn silicide A combination of poly silicon coated or just silicon with a refractory metal Used to decrease the resistance of the gate electrode Poly has sheet resistance of 2550 Ohms Silicides may be easily formed by thermally reacting a variety of metal with silicon and are widely used as contacts to silicon and conductors Ion implantation Ionized atoms are accelerated to high energies in a particle accelerator The ionized beam is passed through a magnetic eld to select the desired species using a magnetic eld The ions crash into the substrate to dope the material Annealing is used to repair the damage to the xtal during the implantation process particle diffusion Movement of particles due to thermal energies that cause particles to move from a higher concentration area to a lower concentration areas projected range This is the average depth of an implanted ion straggle This represents the standard deviation of the ion implantation ChemicalMechanical Polishing CMP This process uses a combination of etching and mechanical quotsandingquot to produce planar surface on silicon wafers This is used for building up multiple layers of metal wires and is used in the damascene process A process whereby a chemical reaction increases the mechanical removal rate of a material CMP is commonly used to polish off high spots on wafers or films deposited on wafers attening the lm or wafer referred to as planarization The chemical reaction that increases the mechanical removal rate is commonly tailored to provide a higher removal rate of one material versus another material The chemical action in CMP helps to achieve higher selectivity39s of one material to another than a strictly mechanical process would provide cluster tool a piece of equipment that utilizes a central robot to feed multiple process chambers Cluster tools are commonly used to perform multiple process steps on a single piece of equipment and may improve process control and e cycle tim Capacitance Voltage Plot CV Plot A technique used to characterize the amount of electrically active defects and mobile contaminants in a dielectric Oxide xed charge oxide trapped charge interface trapped charges number of interface traps and mobile charge may all be measured The technique may also be used to measure the pro le of impurities in silicon Capital Items with a useful life ofgreater than one year and with a cost above some threshold value Capital items are written off over a set period Depreciation related to the useful life ofthe item and accounting rules Critical Dimension The width of a line or space that has been identi ed as critical to the device being fabricated operating properly Critical dimensions are frequently measured some or all wafers followin an photolithography or etching process in which the dimensions are critical Deionized DI Water Water from which the majority of ions have been removed Tap water has resistivity of lt50 kiloohms deionized water may have resistivity as gt18 megaohms The term deionized water has been largely replaced by ultrapure water to indicate that more than just low ions counts are required Epitaxial Layer A single crystal layer formed on top of a single crystal substrate An epitaxial layer will typically have a different doping level and or type than the substrate upon which the epitaxial layer is formed In some cases the epitaxial layer may be a completely different type of material than the substrate upon which it is grown If the substrate and the epitaxial layer are both the same element or compound then the process is homoepitaxy and if the epitaxial layer and the substrate are different elements or compounds then the process if hetroepitaxy Gross Die Per Wafer The number of whole die on a wafer Hard Bake A bake performed to photoresist a er develop Hard e is performed at a higher temperature than soft bake sense photoresist photosensitivity is no longer required exposure and develop are already done and the pattern is formed Hard bake stabilizes the photoresist prior to subsequent processing Four Point Probe A piece of metrology equipment used to measure sheet resistance A four point probe forces a current through the two outside probes and measures the resulting voltage drop across two inside probes Photolithography Carving through use of light O en a photosensitive surface a photoresist is selectively exposed to light using a template The exposed areas are subsequently etched carved by chemical means Reticle or Mask This plate is typically 510x larger than the size of the actual chip It contains two types of regions transparent and opaque This are typically made of glass with chromium Photoresist This is a viscous polymer resin containing photochemical active polymerPAC There are positive and negative photoresists Spin coating is the most common method of putting photoresist on a wafer polymer A substance made of many repeating chemical units or molecules The term polymer is o en used in place ofplastic rubber or elastomer A polymer which is formed om the fusion of two nomers which join completely without losing any small molecules A monomer is a simple molecular unit such as ethylene or styrene from which a polymer can be made Photoresist Stripper A organic solvent blend which is used to remove photoresist Stripping The process of removing photoresist Stripping may be accomplished by acid or solvent based wet strippers or by dry ashing Beading effect When spun onto a wafer the surface tension causes a bead to form around the edge of the wafer xposure step The resist is exposed to ultraviolet light as a step in the development Positive photoresist The exposure to ultraviolet light weakens polymer bonds and a chemical rinse with a photoresist stripper takes the exposed regions away Negative photoresist The exposed regions are hardened and the un exposed regions are removed with a chemical rinse Etching Etching is the process of removing material from the die during the fabrication process ReactiveIonEtching RIE The surface of the wafer is subjected to a gaseous plasma that is formed from an inert gats such as Argon and has reactance chemical in it The chemicals and the plasma are chosen to attach and remove the material s layer not shield by the hardened photoresist The resist can withstand the etching chemicals This technique can be used to pattern any material layer above the wafer surface including polysilicon CVD oxides and metals NOT Cu A technique whereby radio frequency radiation is coupled into a low pressure gas to ionize e gas producing disassociation of the gas molecules into more reactive specie and the substrate being etched is biased to induce ion bombardment Compounds containing carbon C and halogens such as uorine F chlorine C1 or Bromine Br are typically used as gases When the compounds disassociate in the plasma both highly reactive halogen atoms or halogen compounds and polymers that may deposit on the substrate blocking the highly reactive species are generated Ions accelerated towards the substrate being etched by the applied or induced bias remove polymers on substrate surfaces oriented normal to the direction of ion motion polymers coat substrate surfaces that are oriented parallel to the ion motion and block etching of those surfaces Ion bombardment may also activate or accelerate chemical etching reactions RIE therefore has the capability to etch surfaces normal to the direction of ion motion at a higher relative rate and surfaces parallel to the ion motion at a lower relative rate resulting in anisotropic etching Typical RlE conditions are low pressure low ionization levels and high ion energies relative to other dry etch techniques Lateral doping This is the diffusion of doping atoms under the resistoxide shielding layers This occurs during the annealing step after ionimplantation Wafer stepper This is an apparatus that is used to hold the wafer and accurately aligns the wafer so that each die can be exposed by ultraviolet light through a single reticle during the quotstep and repeater process Wafer Fabrication Facility A facility where the wafer fabrication process is performed Fabs include a high quality clean r om a e support systems such as ultrapure water gas and chemical generation and delivery systems wastewater treatment extension HVAC equipment as well as s other support function Argon Fluoride Laser In the semiconductor industry generally used to refer to an excimer laser that uses argon an uorine gases to produce an output of 193 nanometers Expected to be the light source of choice for critical levels at 130nm and 100mm minimum linewidths Ashing The process of removing photoresist using an oxygen plasma or ultraviolet light generated ozone Ashing produces no chemical waste photoresist is volatilized into N2 02 CO and C02 gases Test sites A wafer contains many die sites but some test sites This test sites holds test structures and circuits such as MOS capacitors doped regions of silicon MOSFETS and simple circuits These are electrically test during various phases of the manufacturing process Wafer probes This small metallic probes can contact regions on the wafer to allow the tests to the Test sites Electrical parameters for circuit design are extracted Wafer Probe the test step where each individual die on a wafer surface is tested and bad die are marked as bad Also called wafer test or wafer sort Registration Target Accurate alignment of each masking layer is vital for a function chip The registration targets are geometrical patterns that are created on a base layer to help align later masking steps For more layers more registration marks are needed Clean Room This is a space that is used to fabricate integrated circuits These rooms must be free of particles in the air so as to not produce defects on the die HighEf ciency Particulate Air HEPA lers are used to remove dust particles from the air Class X This clean room designation class 1000 class 100 class 10 means that there are less than X 100010010 particles per cubic foot with diameters greater than 05 microns Modem facilities have Class 1 or better rating in critical working areas pellicle A thin transparent layer stretched over a frame above the surface of a mask or reticle Pellicles are used to block particles from reaching the mask or reticle surface where the particle would be in the focal plane Any particles on the pellicle surface are out of the focal plane and should not form and image on the wafer being exposed Net Die Per Wafer The number of good die on a wafer after wafer test Pinhole A small undesired hole in a photoresist lm deposited or grown lm or opaque area on a photomask Flat Zone The region in a furnace where the temperature is controlled within some speci c tolerance for example or degree centigrade Plasma A gas weekly ionized to produce electron ion pairs and neutral chemically reactive specie Large Scale Integration Integrated circuits containing gt1000 but lt100000 transistors Post Exposure Bake PEB A bake performed after exposure but prior to develop on chemically ampli ed photoresists PEB aids in the exposure induced photo reaction Emulsion Mask A transparent glass plate with light blocking pattems formed on it by silver salts in suspension in a gelatin or colloidal Emulsion masks are relatively low cost and were widely used when contact aligners were popular The quality of emulsion masks is not suf cient for submicron photolithography and their use largely faded away when projection aligners became o ular Projection Aligner An alignment system in which a mask and wafer are separated by a signi cant distance and the mask pattern is focused onto the wafer aligned and exposed Projection printing was invented in 1973 and by the mid 1970s had largely replaced contact and proximity aligners Lowk Dielectric A dielectric material with a dielectric constant less than the dielectric constant of silicon dioxide klt4 The propagation delay of a signal through an interconnect layer is related to the resistance and capacitance of the conductor Lowk dielectric materials surrounding the conductor reduce capacitance and propagation delay Hot Lot A lot that is given priority and typically processed immediately upon reaching each step during fabrication Plasma Etch A technique whereby radio or microwave equency radiation is coupled into a low pressure gas to ionize the gas producing disassociation of the gas molecules into more reactive specie Compounds containing halogens such as uorine F chlorine C1 or bromine Br are typ39c used as etch gases en the compounds disassociate in the plasma the resulting highly reactive halogen atoms or halogen compounds perform chemical etching in a generally isotropic manner Typical plasma etching conditions are high pressure low ionization levels and low ion energies relative to other dry etch techniques Salacide Self Aligned Silicide A silicide process where an oxide or nitride layer with opening down to silicon is used to allow silicide to only form in selected areas SC1 Standard Clean 1 The rst cleaning step in the original RCA clean SCl is a heated ammonium hydroxide NH4OH hydrogen peroxide HZOZ bath used to remove organic residues and particles Frequently performed in a Megasonic bath to improve particle remov SC2 Standard Clean 2 The second cleaning step in the original RCA clean SC2 is a heated hydrochloric acid HCl hydrogen peroxide H202 bath primarily used to remove metal contaminants Silane The chemical formula is SiH4 silane is a pyrophoric toxic gas with a TLV of 5ppm and is combustible in the range of N196 Silane is widely used to deposit silicon containing lms in a variety of CVD reactions Silicon On Insulator SOI A substrate that has a layer of single crystal silicon on top of an insulating layer on top of additional silicon 01 is used to reduce stray capacitance for highspeed and or lowpower CMOS and may also be used for high voltage applications Probe Card A card that hold a number of tiny needles with speci c spacings designed to make contact with bond pads so that die can be tested in wafer form Ion An atom that has either gained or lost an Electron making it either positively or negatively Charged Slice Another term for wafer most often used during wafer manufacture where wafers are sliced om an ingot Minienvironment A localized clean environment created around a tool or only within a tool where wafers will be exposed to the atmosphere Wafers are moved from one minienvironrnent equipped tool to the next minienvironrnent equipped tool in sealed containers and only exposed to the atmosphere inside of the clean environment created inside the tool Semicustom an integrated circuit that has been designed either by using existing blocks of design elements or is made on an existing array of gates which are just connected together to form a new circuit See also Standard Cell and Gate Array Furnace A type of semiconductor manufacturing equipment used to heat up groups ofwafers to temperatures gt200 C and lt1300 C with precise temperature control Furnaces have quartz tubes sufficiently large to hold a wafer boat and the tube is surrounded by resistance heating elements The quartz tube has one end connected to a gas controller that allows various gases to ow through the tube the would also commonly have the ability to change peratures in a controlled manner and insert and withdraw the wafer boat all under computer control Computer programs may then 39nsert the wafer boat into a controlled atmosphere increase the temperature make changes in the gases owing and then reduce the temperature and withdraw the wafer boat to accomplish oxidation diffusion alloying or annealing Standard furnace typically rampup at 510 Cmin and rampdown at 23 Cmin Soft Bake A bake performed a er photoresist coating but prior to exposure So bake dries the photoresist lm and improves photoresist adhesion to the wafer Step Coverage The ratio of the thickness of a lm over a step edge to the thickness in a at area Most metalization processes result in a thinner metal layer over a step than in a at area Most people require or at least target gt50 step coverage Scanning Electron Microscope SEM A microscope that uses a nely focused electron beam scanned across a sample to produce high resolution images A SEM can resolve much smaller feature than a standard microscope down to approximately 2 nanometers SSI Small Scale Integration ICs with fewer than 30 transistors MSI Medium Scale Integration An integrated circuit consisting ofgt30 and lt1000 transistors VLSI Very Large Scale Integration Integrated circuits with greater than 100000 transistors ULSI Ultra Large Scale Integration Integrated circuits containing greater than 10 million transistors Boat A carrier made to hold wafers Most commonly a boat has 25 slots and is made of quartz polysilicon or silicon carbide for use in a furnace polypropylene for general wafer transport or Te on for use in a wet process Some furnace boats have 50 slots


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