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# Intro to Computer Engr ECE 2030

GPA 3.64

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This 0 page Study Guide was uploaded by Cassidy Effertz on Monday November 2, 2015. The Study Guide belongs to ECE 2030 at Georgia Institute of Technology - Main Campus taught by Yalamanchili in Fall. Since its upload, it has received 18 views. For similar materials see /class/233895/ece-2030-georgia-institute-of-technology-main-campus in ELECTRICAL AND COMPUTER ENGINEERING at Georgia Institute of Technology - Main Campus.

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Date Created: 11/02/15

Yalamanchili N 0 September 10 2008 ECE 2030 Study Guide Computing Systems Be able to state Moore s Law and its basic consequences read the web page Conversion between decimal octal hexadecimal and binary number systems Basic components of a computing system Abstraction hierarchy from transistors switches to data paths 0 You should know what the components are at each level Switch Design Can you distinguish between shorts and oats From a switch diagram 0 What does high impedance or oat mean Translate between Boolean expressions and switch level implementations Be able to design a pullup network or pulldown network from a Boolean expression Be able to produce the dual of a switch network built with ntype ptype switches Produce switch implementations of all of the basic gates AND NAND NOR OR INVERTER XOR XNOR 0 Including gates with more than two inputs Understand the physical properties of transistor devices 0 Propagation delay fanin fanout concept of load 0 Relationship between load and propagation delay 0 What is switching power and leakage power Be able to draw basic timing diagrams for small combinational logic circuits Boolean Logic 0 Be able to translate between Boolean expressions and gate level designs not using mixed logic Simplify Boolean expressions algebraically using the principal Boolean identities Understand the concept of universal gates and be able to demonstrate algebraically that NANDs and NORs are universal gates Understand standard forms for Boolean expressions 0 Be able to write the sum of minterms or product of maxterms form of a Boolean expression from its truth table representation 0 Be able to convert between sum of minterms form and product of maxterms form for an expression algebraically o Algebraically simplify the sum of minterms or product of maxterms form Understand sum of product SOP and product of sum POS forms of Boolean expressions Yalamanchili September 10 2008 o How do these forms differ from sum of minterms and product of maxterms forms 0 Understand the dual of a Boolean function and be able to compute it 0 Note taking the dual and complementing each literal is a short cut to computing the complement of a Boolean function I Using the preceding observation compute the dual of Boolean expression 0 Compare two Boolean expressions and comment on the relative complexity of the gate level or transistor level implementation 0 Complexity is defined as the number of gatesswitchesliterals required to compute the function 4 Gate Design 0 Understand the terminology of inverting gates and noninverting gates o What is negative logic 0 What is a mixed logic gate 0 Understand the difference between activelow and active high signals 0 Be able to write the truth table for a basic gate using 0 1 if one of the inputs is active low 0 Know all pairs of DeMorgan s equivalent gates and DeMorgan s square reference ECE 2030 Reading page handout on mixed logic 0 Using mixed logic translate from a Boolean expression to a gate level implementation based on only 0 NOR gates o NAND gates 0 NOT and Inverter gates o NAND and inverter gates 0 AND gates inverter gates not something we usually want to do in practice 0 OR Gates and inverter gates not something we usually want to do in practice 0 Be able to read the Boolean expression given a mixed logic design 0 Be able to include active low signals in the translations between Boolean expressions and gate designs using mixed logic notation 0 Determine the number of transistors required to implement a gate level design specified in mixed logic notation 0 Understand why we use mixed logic 5 Simplifying Expressions 0 Understand 0 Mapping from minterms and maxterms to the 23 and 4 variable Kmap 0 Be able to write the minterm and maxterms expressions for each entry in a Kmap 0 Mapping from the truth table to the 23 and 4 variable Kmap and vice versa Yalamanchili 039 N September 10 2008 0 Mapping from a truth table with don t care symbols X to the 2 3 and 4 variable Kmap 0 From an arbitrary Boolean expression create the 23 and 4 variable Kmap Be able to identify and understand the differences between an implicant prime implicant and essential prime implicant From any Kmap including one with don t care entries write 0 The optimized Boolean SOP expression 0 The optimized Boolean POS expression Given the preceding skills now from an arbitrary Boolean expression you should be able to o Simplify this expression using kmaps o Create a NAND or NOR implementation of the optimized expression using mixed logic 0 Create a switch level implementation of the optimized expression using n and ptype switches Building Blocks Understand the operation of Multiplexers and Demultiplexors Be able to implement both with basic gates or pass gates Understand the operation and implementation of decoders and priority encoders Be able to implement arbitrary priorities of the inputs Demonstrate ability to implement arbitrary truth tables with multiplexors decoders Given a network of interconnected building blocks be able to o analyze the connectivity given the value of the control signals 0 determine the values of the control signals to realize a certain connectivity between inputs and outputs Construct larger building blocks from smaller building blocks Given a PLNPAL and a Boolean expression to be implemented show the connections to be blown to realize this connectivity Be able to draw a small PLNPALROM and in the case of a ROM be able to identify the connections to be made to initialize the contents to a given value Be able to create a memory based implementation of a truth table or simple gate level or switch level circuit ie be able to implement the truth table The implementation can be a ROM or RAM based implementation Number Systems Be able to translate between binary octal decimal and hexadecimal notations Be able to translate between fixedpoint binary and decimal notations Know the ranges and precision of nbit unsigned integer sign two s complement xed and oating point representations Translate between oating point and decimal representations Know both single and double precision formats as well as ranges Yalamanchili on 0 September 10 2008 How do you compare two oating point numbers for less than or greater than using only an integer ALU Which of these laws apply to oating point arithmetic associatively and commutatively Be able to provide examples Given a signi cant number of digits be able to compute the error for oating point addition or multiplication of two numbers Given a byte stream and the ASCII table be able to decode the byte stream Arithmetic Additionsubtraction and over ow detection for two complement and sign magnitude arithmetic Over ow detection condition and hardware implementation Be able to draw the gate level implementations of a full adder De ne and implement the behavior of a full adder and subtractor Cascade to a wordwide design Implement a wordwide addersubtractor using only full adders Be able to draw an implementation of a multiplier using gates and a full adder Detection for over ow negative and nonzero in a nbit addersubtractor Calculate the delay in gate delays for an nbit ripple carry addersubtractor Latches and Registers Implement a transparent latch using basic gates and pass gates Implement a register with read and write enables using a twophase non overlapping clock Understand the difference between a latch and a register Be able to draw the timing diagrams for groups of latches or registers Be able to draw the implementation of a shift register capable of left and right shifts left and right rotate operations and parallelserial load You can use gates and registers as building blocks Be able to draw a 10 transistor DLatch Draw a register with basic gates that includes asynchronous set and preset Raw the implementation of a register le using multibit registers building blocks and basic gates Understand twophase vs edge triggered designs Be able to draw examples of both using basic gates Counters Be able to draw a toggle cell and use it to build counters o Initialize counters to specific values 0 Construct modulok counters Design of synchronous updown counters State diagrams for various types of counters o Countbyk Yalamanchili September 10 2008 0 Ring counter 0 Design of these counters using state machine approaches Use register design approaches for serialparallel load for initialization State Machines Be able to draw a state diagram from a problem speci cation this is admittedly dependent on the problem description Get in the habit about thinking of the operation of systems as a sequence of states and transitions between states Speci cally from a problem description be able to 0 De ne the states 0 De ne the state transitions and draw them Describe the conditions for a transition in terms of Boolean variables state transitions depend on input values and the current state De ne the values for each output variable associated with each state transition Label the state transitions with values of inputoutput variables in the case of a Moore machine there are no output variables 0 Pick a binary encoding for the states 0 Pick a binary encoding for the input variables Understand the difference between a Moore and a Mealy state machine Translate between state diagrams and state transition tables Implement the combinational logic for each output variable from the state transition table and for the next value of each state element Draw the gate level implementation of the state machine 0 Gate level description of the combinational logic 0 Use latches ip ops for the state elements Given a state machine diagram be able to gure out what it does ie given an initial state what are the outputs at each clock cycle and what is the state at each clock cycle 0 Create the state transition table from the state machine diagram What is the difference between asynchronous and synchronous state machines What is the impact of different state encodings Handling unde ned states and initialization Memory Understand memory cell behavior and how it is different from a register cell Understand static 6transistor and dynamic ltransistor implementations of memory cell Know the organization of a memory chip as an array of memory cells row and column addressing decoding bidirectional data bus What do the terms RAS and CAS mean Yalamanchili September 10 2008 Use memory chips eg 4 M addresses by 4 bits address to build larger memory systems Given a target system design number of addresses number of bits per address and a memory chip building block de ne the implementation in terms of number organization and operation of chips with the addition of external building blocks as necessary eg decoders Identify chips responsible for a speci ed memory location in a memory system 0 Given a multichip design and an address what locations addresses in which chips are accessed Know byte halfword word double word and 2k byte boundaries 0 What does alignment mean Given a set of memory directives provide the contents of memory encoded in hex Given a memory system designed with multiple chips for example a 2M addresses x 16 bits using 1M address x 4 bit chips and a set ofmemory directives provide the hex contents of speci c locations in a speci c chip Given the memory contents and an interpretation such as little endian or big endian ordering provide the values that are accessed from memory as a word half word or double word Datapath Units Implement a register le from wordwide registers and decoders Implement a wordwide logical unit using multiplexers How is the meaning of all 16 possible logical operations de ned Implement a 1bit 2bit and 4bit leftright shifter from multiplexers Cascade to a 32 bit barrel shifter Show how magnitude and direction can be extracted from a sixbit shift value Understand the difference between logical arithmetic and rotate shifts Understand the operation of simple three bus datapath that may contain register les arithmetic units addersubtractor multiplierdivider logical units shift units and memory Be able to translate simple programs into sequences of operations on a single cycle datapath Define all control signals for each cycle Understand and employ immediate values in programs that require them Be able to translate sequences of operations into microcode Controllers amp Instructions Explain operation of a controller including the instruction pointers code memory instruction decode and next instruction computation Explain how an instruction set architecture separates issues of programming from issues of system implementation Know how elds associated with opcode register operands and immediate operands can be decoded into control signals for the single cycle datapath Using a MIPSlike ISA be able to write simple straightline assembly code sequences using the expanded single cycle datapath Yalamanchili N 0 April 9 2008 Study Guide ECE 2030 Spring 2008 Computing Systems Be able to state Moore s Law and its basic consequences read the web page Conversion between decimal and binary number systems Basic components of a computing system Abstraction hierarchy from transistors switches to data paths 0 You should know what the components are at each level Switch Design 0 Can you distinguish between shorts and oats From a switch diagram 0 What does high impedance or oat mean Translate between Boolean expressions and switch level implementations Be able to design a pullup network or pulldown network from a Boolean expression Be able to produce the dual of a switch network built with ntype ptype switches Produce switch implementations of all of the basic gates AND NAND NOR OR INVERTER XOR XNOR 0 Including gates with more than two inputs Understand the physical properties of transistor devices 0 Propagation delay fanin fanout concept of load 0 Relationship between load and propagation delay 0 What is switching power and leakage power Boolean Logic 0 Be able to translate between Boolean expressions and gate level designs not using mixed logic Simplify Boolean expressions algebraically using the principal Boolean identities Understand the concept of universal gates and be able to demonstrate algebraically that NANDs and NORs are universal gates Understand standard forms for Boolean expressions 0 Be able to write the sum of minterms or product of maxterms form of a Boolean expression from its truth table representation 0 Be able to convert between sum of minterms form and product of maxterms form for an expression algebraically o Algebraically simplify the sum of minterms or product of maxterms form Yalamanchili P 01 April 9 2008 Understand sum of product SOP and product of sum POS forms of Boolean expressions 0 How do these forms differ from sum of minterms and product of maxterms forms Understand the dual of a Boolean function and be able to compute it 0 Note taking the dual and complementing each literal is a short cut to computing the complement of a Boolean function I Using the preceding observation compute the dual of Boolean expression Compare two Boolean expressions and comment on the relative complexity of the gate level or transistor level implementation 0 Complexity is defined as the number of gatesswitchesliterals required to compute the function Gate Design Understand the terminology of inverting gates and noninverting gates o What is negative logic 0 What is a mixed logic gate Understand the difference between activelow and active high signals 0 Be able to write the truth table for a basic gate using 01 if one of the inputs is active low Know all pairs of DeMorgan s equivalent gates and DeMorgan s square reference ECE 2030 Reading page handout on mixed logic Using mixed logic translate from a Boolean expression to a gate level implementation based on only 0 NOR gates NAND gates NOT and Inverter gates NAND and inverter gates AND gates inverter gates not something we usually want to do in practice 0 OR Gates and inverter gates not something we usually want to do in practice Be able to read the Boolean expression given a mixed logic design Be able to include active low signals in the translations between Boolean expressions and gate designs using mixed logic notation Determine the number of transistors required to implement a gate level design specified in mixed logic notation Understand why we use mixed logic 0 O O O Simplifying Expressions Understand 0 Mapping from minterms and maxterms to the 23 and 4 variable Kmap 0 Be able to write the minterm and maxterms expressions for each entry in a Kmap Yalamanchili 039 N April 9 2008 Mapping from the truth table to the 23 and 4 variable Kmap and vice versa Mapping from a truth table with don t care symbols X to the 2 3 and 4 variable Kmap 0 From an arbitrary Boolean expression create the 23 and 4 variable Kmap Be able to identify and understand the differences between an implicant prime implicant and essential prime implicant From any Kmap including one with don t care entries write 0 The optimized Boolean SOP expression 0 The optimized Boolean POS expression Given the preceding skills now from an arbitrary Boolean expression you should be able to o Simplify this expression using kmaps o Create a NAND or NOR implementation of the optimized expression using mixed logic Create a switch level implementation of the optimized expression using n and ptype switches O O O Building Blocks Understand the operation of Multiplexers and Demultiplexors Be able to implement both with basic gates or pass gates Understand the operation and implementation of decoders and priority encoders Be able to implement arbitrary priorities of the inputs Demonstrate ability to implement arbitrary truth tables with multiplexors decoders Given a network of interconnected building blocks be able to o analyze the connectivity given the value of the control signals 0 determine the values of the control signals to realize a ce1tain connectivity between inputs and outputs Construct larger building blocks from smaller building blocks Given a PLNPAL and a Boolean expression to be implemented show the connections to be blown to realize this connectivity Be able to draw a small PLNPALROM and in the case of a ROM be able to identify the connections to be made to initialize the contents to a given value Be able to create a memory based implementation of a truth table or simple gate level or switch level circuit ie be able to implement the truth table The implementation can be a ROM or RAM based implementation Number Systems Be able to translate between binary octal decimal and hexadecimal notations Be able to translate between xedpoint binary and decimal notations Know the ranges and precision of nbit unsigned integer sign two s complement xed and oating point representations Yalamanchili on CD April 9 2008 Translate between oating point and decimal representations Know both single and double precision formats as well as ranges How do you compare two oating point numbers for less than or greater than using only an integer ALU Which of these laws apply to oating point arithmetic associatively and commutatively Be able to provide examples Given a signi cant number of digits be able to compute the error for oating point addition or multiplication of two numbers Given a byte stream and the ASCII table be able to decode the byte stream Arithmetic Additionsubtraction and over ow detection for two complement and sign magnitude arithmetic Over ow detection condition and hardware implementation Be able to draw the gate level implementations of a full adder Define and implement the behavior of a full adder and subtractor Cascade to a wordwide design Implement a wordwide addersubtractor using only full adders Be able to draw an implementation of a multiplier using gates and a full adder Detection for over ow negative and nonzero in a nbit addersubtractor Calculate the delay in gate delays for an nbit ripple carry addersubtractor Latches and Registers Implement a transparent latch using basic gates and pass gates Implement a register with read and write enables using a twophase non overlapping clock Understand the difference between a latch and a register Be able to draw the timing diagrams for groups of latches or registers Be able to draw the implementation of a shift register capable of left and right shifts left and right rotate operations and parallelserial load You can use gates and registers as building blocks Be able to draw a 10 transistor DLatch Draw a register with basic gates that includes asynchronous set and preset Raw the implementation of a register file using multibit registers building blocks and basic gates Understand twophase vs edge triggered designs Be able to draw examples of both using basic gates Counters Be able to draw a toggle cell and use it to build counters o Initialize counters to specific values 0 Construct modulok counters Design of synchronous updown counters Yalamanchili April 9 2008 State diagrams for various types of counters o Countbyk 0 Ring counter 0 Design of these counters using state machine approaches Use register design approaches for serialparallel load for initialization State Machines Be able to draw a state diagram from a problem speci cation this is admittedly dependent on the problem description Get in the habit about thinking of the operation of systems as a sequence of states and transitions between states Speci cally from a problem description be able to 0 De ne the states 0 De ne the state transitions and draw them Describe the conditions for a transition in terms of Boolean variables state transitions depend on input values and the current state De ne the values for each output variable associated with each state transition Label the state transitions with values of inputoutput variables in the case of a Moore machine there are no output variables 0 Pick a binary encoding for the states 0 Pick a binary encoding for the input variables Understand the difference between a Moore and a Mealy state machine Translate between state diagrams and state transition tables Implement the combinational logic for each output variable from the state transition table and for the next value of each state element Draw the gate level implementation of the state machine 0 Gate level description of the combinational logic 0 Use latches ip ops for the state elements Given a state machine diagram be able to gure out what it does ie given an initial state what are the outputs at each clock cycle and what is the state at each clock cycle 0 Create the state transition table from the state machine diagram What is the difference between asynchronous and synchronous state machines What is the impact of different state encodings Handling unde ned states and initialization Memory Understand memory cell behavior and how it is different from a register cell Understand static 6transistor and dynamic ltransistor implementations of memory cell Yalamanchili April 9 2008 Know the organization of a memory chip as an array of memory cells row and column addressing decoding bidirectional data bus What do the terms RAS and CAS mean Use memory chips eg 4 M addresses by 4 bits address to build larger memory systems Given a target system design number of addresses number of bits per address and a memory chip building block de ne the implementation in terms of number organization and operation of chips with the addition of external building blocks as necessary eg decoders Identify chips responsible for a speci ed memory location in a memory system 0 Given a multichip design and an address what locations addresses in which chips are accessed Know byte halfword word double word and 2k byte boundaries 0 What does alignment mean Given a set of memory directives provide the contents of memory encoded in hex Given a memory system designed with multiple chips for example a 2M addresses x 16 bits using 1M address x 4 bit chips and a set ofmemory directives provide the hex contents of speci c locations in a speci c chip Given the memory contents and an interpretation such as little endian or big endian ordering provide the values that are accessed from memory as a word half word or double word Datapath Units Implement a register le from wordwide registers and decoders Implement a wordwide logical unit using multiplexers How is the meaning of all 16 possible logical operations de ned Implement a 1bit 2bit and 4bit leftright shifter from multiplexers Cascade to a 32 bit barrel shifter Show how magnitude and direction can be extracted from a sixbit shift value Understand the difference between logical arithmetic and rotate shifts Understand the operation of simple three bus datapath that may contain register les arithmetic units addersubtractor multiplierdivider logical units shift units and memory Be able to translate simple programs into sequences of operations on a single cycle datapath Define all control signals for each cycle Understand and employ immediate values in programs that require them Be able to translate sequences of operations into microcode Controllers amp Instructions Explain operation of a controller including the instruction pointers code memory instruction decode and next instruction computation Explain how an instruction set architecture separates issues of programming from issues of system implementation

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