Intro to Computer Engr
Intro to Computer Engr ECE 2030
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0 Semiconguctor Corporation MachXO Family Handbook HB1002 Version 020 November 2007 39 MachXO Family Handbook Table of Contents Corporation November 2007 Section I MachXO Family Data Sheet Introduction Features 1 t A 1 Architecture Architecture Overview 2 1 P U Blocks 2 3 Slice 2 3 Rniifinn 2 6 ClockControl Distribution Network 2 7 sysCLOCK Phase Locked Loops PLLs 2 9 sysMEM Memory 2 10 PO Groups 2 14 PIO 2 14 syle Buffer 2 15 syle Buffer Banks 2 18 Hot Socketing 220 Sleep Mode 2 21 SLEEPN Pin Characteristics 2 21 Oscillator 2 21 Configuration and Testing 2 21 EEE 11491Compliant Boundary Scan Testability 2 21 Device f quotg 39 2 22 Density Shifting 2 23 DC and Switching Characteristics Absolute Maximum Ratings 31 Recommended Operating Conditions 31 MachX0256 and MachX064O Hot Socketing I 31 MachXOlZOO and MachX02280 Hot Socketing I 3 DC Electrical f 39 39 32 Supply Current Sleep Mnr lm 33 Supply Current Standbyl 33 Initialization Supply Current 34 Programming and Erase Flash Supply Current 35 syle Recommended Operating Conditions 35 syle SingleEnded DC Electrical f 39 37 syle Differential Electrical Characteristics 38 LVDS 38 LVDS Fmiilafinn 38 BLVDS 39 LVPECL 310 RSDS 311 Typical Building Block Function Performance 312 RegistertoRegister Performance 312 Derating Logic Timing 312 MachXO External Switching f 313 MachXO Internal Timing Parameter 314 MachXO Family Timing Adders 315 2007 Lattice Semiconductor Corp All Lattice trademarks registered trademarks patents and disclaimers are as listed atwwwlatticesemi comlegal All other brand or product names are trademarks or their r k M T r quotPquot 39to change wrthout notice wwwlatticesemicom 1 Table of Contents Lattice Semiconductor MachXO Family Handbook sysCLOCK PLL Timing 316 Flash Download Time 317 JTAG Port Timing Specifications 317 Switching Test Conditions 318 Pinout Information Signal Descriptions Pin Information Summary Power Supply and NC Power Supply and NC Cont LCMX0256 and LCMX064O Logic Signal Connections 100 TQFP LCMXOIZOO and LCMX02280 Logic Signal Connections 100 TQFP LCMX0256 and LCMX064O Logic Signal Connections 100 csBGA LCMX0640 LCMXOIZOO and LCMX02280 Logic Signal F quot 132 csBGA 414 LCMX0640 LCMXOIZOO and LCMX02280 Logic Signal F quot 144 TQFP 417 LCMX0640 LCMXOIZOO and LCMX02280 Logic Signal F quot 256 ftBGA 420 LCMX02280 Logic Signal Connections 324 ftBGA 426 Thermal 39 436 For Further Information 436 Ordering Information Part Number Description 51 Ordering Information 51 Conventional Packaging 52 Conventional Packaging 55 LeadFree Packaging 57 LeadFree Packaging 510 Supplemental Information For Further Information 61 Revision History Section II MachXO Family Technical Notes MachXO sysO Usage Guide 81 sysIO Buffer Overview 81 Supported sysIO Standards 81 sysIO Banking Scheme 82 VCCIO 12V15V18V25V33V 84 VCCAUX 33V 84 Mixed Voltage Support in a Rank 84 sysIO Standards Supported in Each Rank 85 LVCMOS Buffer Configurations 85 Programmable PULLUPPULLDOWNBUSKEEPEFI 85 Programmable Drive 86 Programmable Slew Rate 86 OpenDrain Control 86 Programmable PCICLAMP 86 5V Input Interface Using the PCI Clamp Diode 86 Software sysIO Attributes 88 IOTYPF 88 OPENDFIAIN 89 FIIVE 89 PULLMODE 89 PCICLAMP 89 SLEWFIATE 810 LOC 810 Design Considerations and llsane 810 Table of Contents Lattice Semiconductor MachXO Family Handbook Banking Rules Zero Hold Time Fast Output Path Dedicated Pins Differential IO 39 I Technical Support A i 14 Revision History Appendix A HDL Attributes for Synplify and Precision RTL Synthesis VHDL SynplifyPrecision RTL Synthesis Verilog Synpilfy Verilog Precision RTL Synthesis Appendix B sysIO Attributes Using the Preference Editor User Interface 817 Appendix C sysIO Attributes Using Preference File ASCII File 818 IOBUF 818 818 Memory Usage Guide for MachXO Devices Memories in MachXO Devices Utilizing IPexpress IPexpress Flow True Dual Port RAM RAMiDPiTRUE EBR Based Pseudo Dual Port RAM RAMDP EBR Based Read Only Memory ROM EBR Based First In First Out FIFO FIFODC EBR Based Distributed Single Port RAM Distributed78PRAM PFU Based Distributed Dual Port RAM DistributediDPRAM PFU Based Distributed ROM DistributediROM PFU Based Initializing Memo Initialization File Formats Technical Support A i 14 Revision History Appendix A Attribute Definitions MachXO sysCLOCK Design and Usage Guide 101 MachXO Top Level View 101 sysCLOCK PLL 101 Features 102 Functional Description 102 PLL Divider and Delay Blocks 102 PLL Inputs and Outputs 103 Dynamic Delay Control IO Ports 103 PLL Affrihiifns 104 MachXO PLL Primitive Definitions 104 PLL Attributes Definitions 105 Dynamic Delay quot 39 107 MachXO PLL Usage in IPexpress 108 Configuration Tah 109 Mode 109 Frequency Programming in Divider Mode for Advanced Users 1011 Oscillator 0800 1013 ClockControl Distribution Network 1013 Primary Clock Mux C 39 39 1014 Secondary CIockCELSR Mux 39 39 1015 Primary Clock and Secondary CIockCELSR Distribution Network 1015 Table of Contents Lattice Semiconductor MachXO Family Handbook Maximum Number of Secondary Clocks Available Post Map Preference Editor llsane PCB Layout Recommendations for VCCPLL and GNDPLL if Separate Pins are Available Technical Support A 39 Revision History Power Estimation and Management for MachXO Devices 1016 1016 1017 1017 1017 Power Supply Sequencing and Hot Socketinn Recommended Powerup Sequence Power Calculator Hardware quot Power Calculator Power Calculator Equations Power Calculations Starting the Power Calculator Creating a Power Calculator Project Power Calculator Main Window Power Calculator Wi7ard Power Calculator Creating a New Project Without the NCD File Power Calculator Creating a New Project with the NCD File Power Calculator Open Existing Project Power Calculator Importing Simulation File VCD to the Project Power Calculator Importing Trace Report File TWR to the Project Activity Factor and Toggle Rate Ambient and Junction Temperature and Air ow Managing Power Consumption Power Calculator Assumptions Technical Support A Revision History MachXO JTAG Programming and Configuration User s Guide 121 Programming Overview 121 ispJTAG 122 TDO 122 TDI 122 TMQ 122 TCK 123 VCC Supply for JTAG 123 Download Cable PinoHt 123 BSDL Files 123 Device Wake Up 123 Software Options 123 Preference Options 123 Configuring SRAM or Programming Flash 124 Technical Support A i 14 124 Revision History 125 HDL Synthesis Coding Guidelines for Lattice Semiconductor FPGAs 39 39 quot 131 General Coding Styles for FPGA 131 quot quot 39 ndinn 13 1 Design Partitioning 132 State Encoding Methodologies for State Machines 133 Coding Styles for FSM 135 Using Pipelines in the Designs 136 Comparing IF statement and CASE statement 137 Table of Contents Lattice Semiconductor MachXO Family Handbook Avoiding Nonintentional atr hns HDL Design with Lattice Semiconductor FPGA Devices Lattice Semiconductor FPGA Synthesis Library Implementing Multiplexers Clock Dividers Register Control Signals Use PIC antiirns Implementation of Memories Preventing Logic Replication and Limited Fanollt Use ispLEVER Project Navigator Results for Device Utilization and Performance Technical Support A 39 PCB Layout Recommendations for BGA Packages 1317 Advantages and Disadvantages of BGA Packaging PCB Layout Plated Through Hole Via Placement BGA Board Layout Recommendations BGA Package Types Further39 39 Technical Support A Revision History Section III MachXO Family Handbook Revision History Revision History Revision History 0 Semiconguctor Corporation Section MachXO Family Data Sheet D81002 Version 027 November 2007 Lattice 39 Semiconductor Corporation MachXO Family Data Sheet Introduction August 2006 Data Sheet DS1002 Feat u res I Nonvolatile Infinitely Reconfigurable Instanton powers up in microseconds Single chip no external configuration memory e uired Excellent design security no bit stream to intercept Reconfigure SFlAM based logic in milliseconds SFlAM and nonvolatile memory programmable through JTAG port Supports background programming of nonvolatile memory Sleep Mode Allows up to 100x static current reduction TransFRT39V39 Reconfiguration TFR lnfield logic update while system operates High IIO to Logic Density 256 to 2280 LUT4s 73 to 271 lOs with extensive package options Density migration supporte Lead freeFloHS compliant packaging Embedded and Distributed Memory Up to 276 Kbits sysMEMT39V39 Embedded Block RAM Up to 75 Kbits distributed RAM Dedicated FIFO control logic Table 11 MachXO Family Selection Guide Flexible IIO Buffer Programmable syleT39V39 buffer supports wide range of interfaces LVCMOS 3325181512 LVTTL PCI LVDS BusLVDS LVPECL RSDS I sysCLOCKT39V39 PLLs Up to two analog PLLs per device Clock multiply divide and phase shifting I System Level Support EEE Standard 11491 Boundary Scan Onboard oscillator Devices operate with 33V 25V 18V or 12V power supply EEE 1532 compliant insystem programming Introduction The MachXO is optimized to meet the requirements of applications traditionally addressed by CPLDs and low capacity FPGAs glue logic bus bridging bus interfac ing powerup control and control logic These devices bring together the best features of CPLD and FPGA devices on a single chip 2006 Lattice Semiconductor Corp All Lattice trademarks registered trademarks patents and disclaimers are as listed atwwwlatticesemi comlegal All other brand or product names are trademarks or their wwwlatticesemicom quotPquot l to change Without notice DS1002 Introduction7013 Introduction Lattice Semiconductor MachXO Family Data Sheet The devices use lookup tables LUTs and embedded block memories traditionally associated with FPGAs for flex ible and efficient logic implementation Through nonvolatile technology the devices provide the singlechip high security instanton capabilities traditionally associated with CPLDs Finally advanced process technology and careful design will provide the high pintopin performance also associated with CPLDs The ispLEVEFl design tools from Lattice allow complex designs to be efficiently implemented using the MachXO family of devices Popular logic synthesis tools provide synthesis library support for MachXO The ispLEVEFl tools use the synthesis tool output along with the constraints from its floor planning tools to place and route the design in the MachXO device The ispLEVEFl tool extracts the timing from the routing and backannotates it into the design for timing verification MachXO Family Data Sheet 39 39 Semiconductor 39 COrporation ArCh IteCture February 2007 Data Sheet DS1002 Architecture Overview The MachXO family architecture contains an array of logic blocks surrounded by Programmable IO PIO Some devices in this family have sysCLOCK PLLs and blocks of sysM EMT39V39 Embedded Block RAM EBFts Figures 2 1 2 2 and 2 3 show the block diagrams of the various family members The logic blocks are arranged in a twodimensional grid with rows and columnsThe EBFl blocks are arranged in a column to the left of the logic array The PIO cells are located at the periphery of the device arranged into Banks The PIOs utilize a flexible IO buffer referred to as a sysIO interface that supports operation with a variety of inter face standards The blocks are connected with many vertical and horizontal routing channel resourcesThe place and route software tool automatically allocates these routing resources There are two kinds of logic blocks the Programmable Functional Unit PFU and the Programmable Functional unit without RAM PFFThe PFU contains the building blocks for logic arithmetic RAM ROM and register func tions The PFF block contains building blocks for logic arithmetic ROM and register functions Both the PFU and PFF blocks are optimized for flexibility allowing complex designs to be implemented quickly and effectively Logic blocks are arranged in a twodimensional array Only one type of block is used per row In the MachXO family the number of sysIO Banks varies by device There are different types of IO Buffers on dif ferent Banks See the details in later sections of this document The sysMEM EBFls are large dedicated fast mem ory blocks these blocks are found only in the larger devices These blocks can be configured as RAM ROM or FIFO FIFO support includes dedicated FIFO pointer and flag hard control logic to minimize LUT use The MachXO architecture provides up to two sysCLOCKT39V39 Phase Locked Loop PLL blocks on larger devices These blocks are located at either end of the memory blocks The PLLs have multiply divide and phase shifting capabilities that are used to manage the frequency and phase relationships of the clocks Every device in the family has a JTAG Port that supports programming and configuration of the device as well as access to the user logic The MachXO devices are available for operation from 33V 25V 18V and 12V power supplies providing easy integration into the overall system 2007 Lattice Semiconductor Corp All Lattice trademarks registered trademarks patents and disclaimers are as listed atwwwlatticesemi comlegal All other brand or product names are trademarks or their r h M T r quotPquot 39to change Without notice wwwlatticesemicom 2 1 D81 002 Architecture014 Architecture Lattice Semiconductor MachXO Family Data Sheet Figure 21 Top View of the MachXO 1200 Device PIOs Arranged into X sysIO Banks iliiiiliii EE2Tad lis sysMEM Embedded I Wlth RAM PFUS llllllllll Programmable DDDDDDDDDD DDDDDDDDDD stOCK 7 JTAG PortEl 1Top View of the MachX02280 device is similar but with higher LUT count two PLLs and three EBR blocks Figure 22 Top View of the MachX0640 Device PIOs Arranged into Programmable DEED DD Function Units without RAM PFFs Programmable Function Units with RAM PFUs DDDDDDDD mamE S Architecture Lattice Semiconductor MachXO Family Data Sheet Figure 23 Top View of the MachX0256 Device Programmable Function Units without RAM PFFs JTAG Port PlOs Arranged into syle Banks Programmable Function Units with RAM PFUs PFU Blocks The core of the MachXO devices consists of PFU and PFF blocks The PFUs can be programmed to perform Logic Arithmetic Distributed RAM and Distributed ROM functions PFF blocks can be programmed to perform Logic Arithmetic and Distributed ROM functions Except where necessary the remainder of this data sheet will use the term PFU to refer to both PFU and PFF blocks Each PFU block consists of four interconnected Slices numbered 03 as shown in Figure 24 There are 53 inputs and 25 outputs associated with each PFU block Figure 24 PFU Diagram From Rau ng Slice 0 Slice 1 Slice 2 Slice 3 n n FF FF Latch Latch it it it it it it it it To Slice Each Slice contains two LUT4 lookup tables feeding two registers programmed to be in FF or Latch mode and some associated logic that allows the LUTs to be combined to perform functions such as LUT5 LUT6 LUT7 and LUT8 There is control logic to perform setreset functions programmable as synchronousasynchronous clock select chipselect and wider RAMROM functions Figure 25 shows an overview of the internal logic of the Slice The registers in the Slice can be configured for positivenegative and edgelevel clocks Architecture Lattice Semiconductor MachXO Family Data Sheet There are 14 input signals 13 signals from routing and one from the carrychain from the adjacent SlicePFU There are 7 outputs 6 to the routing and one to the carrychain to the adjacent SlicePFU Table 21 lists the sig nals associated with each Slice Figure 25 Slice Diagram ToAdjaceniSlicePFU OFX1 A1 F1 g1 Fast Connection D1 to Ho Cell Q1 From To Routing Rounng OFXO Fast Connection to Ho Cell F0 Q0 Control Signals CE selected and CLK inverted per LSR Slice in routing From Adjacent SlicePFU Some interSlice signals are not shown 1 Only PFUs at the edges have last connections to the lO cell Table 21 Slice Signal Descriptions 2 Requires two PFUs Architecture Lattice Semiconductor MachXO Family Data Sheet Modes of Operation Each Slice is capable of four modes of operation Logic Ripple RAM and ROM The Slice in the PFF is capable of all modes except RAM Table 22 lists the modes and the capability of the Slice blocks Table 22 Slice Modes l Logic l Ripple RAM l ROM l lPFU Slice l LUT 4x2 or LUT 5x1 l 2bit Arithmetic Unit l SP 16x2 l ROM 16x1 x 2 l lPFF Slice l LUT 4x2 or LUT 5x1 l 2bit Arithmetic Unit l NA l ROM 16x1 x 2 l Logic Mode In this mode the LUTs in each Slice are configured as 4input combinatorial lookup tables LUT4 A LUT4 can have 16 possible input combinations Any logic function with four inputs can be generated by program ming this lookup table Since there are two LUT4s per Slice a LUT5 can be constructed within one Slice Larger lookup tables such as LUT6 LUT7 and LUT8 can be constructed by concatenating other Slices Ripple Mode Ripple mode allows the efficient implementation of small arithmetic functions In ripple mode the fol lowing functions can be implemented by each Slice Addition 2bit Subtraction 2bit AddSubtract 2bit using dynamic control Up counter 2bit Down counter 2bit Ripple mode multiplier building block Comparator functions of A and B inputs A greaterthanorequalto B A notequalto B A lessthanorequalto B Two additional signals Carry Generate and Carry Propagate are generated per Slice in this mode allowing fast arithmetic functions to be constructed by concatenating Slices RAM Mode In this mode distributed RAM can be constructed using each LUT block as a 16X2 bit memory Through the combination of LUTs and Slices a variety of different memories can be constructed The ispLEVER design tool supports the creation of a variety of different size memories Where appropriate the software will construct these using distributed memory primitives that represent the capabilities of the PFU Table 23 shows the number of Slices required to implement different distributed RAM primitives Figure 26 shows the distributed memory primitive block diagrams Dual port memories involve the pairing of two Slices One Slice functions as the readwrite port while the other companion Slice supports the readonly port For more information on RAM mode in MachXO devices please see details of additional technical documentation at the end of this data sheet Table 23 Number of Slices Required For Implementing Distributed RAM SPR16X2 DPR16X2 Number of Slices l 1 l 2 l Note SPR Single Port RAM DPR Dual Port RAM Architecture Lattice Semiconductor MachXO Family Data Sheet Figure 26 Distributed Memory Primitives SPR16X2 DPR16X2 A00 AD1 WA00 RADO A02 WAD1 r RAD1 AD3 DOO WA02 RAD2 DIO D01 WAD3 RAD3 0n WRE 0o RDOO OK 011 RDO1 WCK w000 WRE w001 ROM16X1 A00 AD1 Am 000 AD3 ROM ModeThe ROM mode uses the same principal as the RAM modes but without the Write port Preloading is accomplished through the programming interface during configuration PFU Modes of Operation Slices can be combined within a PFU to form larger functions Table 24 tabulates these modes and documents the functionality possible at the PFU level Table 24 PFU Modes of Operation 39 9i Ripple RAM ROM NIiLLJJ Siif39s 2bit Add X 4 323133 i Home x 8 W332 WSW Siglg ii ROM16x2x4 2bit Counterx4 SPR16X8X1 ROM16x4x2 MLULJT176 11r1 2bit Comp x 4 ROM16X8 x 1 Routing There are many resources provided in the MachXO devices to route signals individually or as buses with related control signals The routing resources consist of switching circuitry buffers and metal interconnect routing seg ments The interPFU connections are made with three different types of routing resources X1 spans two PFUs X2 spans three PFUs and X6 spans seven PFUsThe X1 X2 and X6 connections provide fast and efficient connec tions in the horizontal and vertical directions Architecture Lattice Semiconductor MachXO Family Data Sheet The ispLEVEFt design tool takes the output of the synthesis tool and places and routes the design Generally the place and route tool is completely automatic although an interactive routing editor is available to optimize the design ClockControl Distribution Network The MachXO family of devices provides global signals that are available to all PFUs These signals consist of four primary clocks and tour secondary clocks Primary clock signals are generated from four 161 muxes as shown in Figure 27 and Figure 28 The available clock sources for the MachX0256 and MachX064O devices are four dual function clock pins and 12 internal routing signals The available clock sources for the MachXO1200 and MachX02280 devices are four dual function clock pins up to nine internal routing signals and up to siX PLL out puts Figure 27 Primary Clocks for MachX0256 and MachX0640 Devices 12 4 Pads Architecture Lattice Semiconductor MachXO Family Data Sheet Figure 28 Primary Clocks for MachXO 1200 and MachX 02280 Devices Up 106 4 Primary Clock1 Roulirg Four secondary clocks are generated from four 161 muxes as shown in Figure 29 Four of the secondary clock sources come from dual function clock pins and 12 come from internal routing Figure 29 Secondary Clocks for MachXO Devices 12 4 Secondary Controi Ciocks Pads Architecture Lattice Semiconductor MachXO Family Data Sheet sysCLOCK Phase Locked Loops PLLs The MachXOlZOO and MachX02280 provide PLL support The source of the PLL input divider can come from an external pin or from internal routing There are four sources of feedback signals to the feedback divider from CLKINTFB internal feedback port from the global clock nets from the output of the post scalar divider and from the routing or from an external pinThere is a PLLiLOCK signal to indicate that the PLL has locked on to the input clock signal Figure 210 shows the sysCLOCK PLL diagram The setup and hold times of the device can be improved by programming a delay in the feedback or input path of the PLL which will advance or delay the output clock with reference to the input cockThis delay can be either pro grammed during configuration or can be adjusted dynamically In dynamic mode the PLL may lose lock after adjustment and not relock until the tLOCK parameter has been satisfied Additionally the phase and duty cycle block allows the user to adjust the phase and duty cycle of the CLKOS output The sysCLOCK PLLs provide the ability to synthesize clock frequencies Each PLL has four dividers associated with it input clock divider feedback divider post scalar divider and secondary clock dividerThe input clock divider is used to divide the input clock signal while the feedback divider is used to multiply the input clock signalThe post scalar divider allows the VCO to operate at higher frequencies than the clock output thereby increasing the fre quency rangeThe secondary divider is used to derive lower frequency outputs Figure 210 PLL Diagram Dynamic Delay Adjustment l l l l 4b LOCK RST T Input clock Post Scalar PhaseDuty Divider Delay Divider 40 Select 74gt CLKOS cLKI Adjust CLKOP 7 Oscillator from routing or external pin 7 CLKOP Feedback seamer CLKFB 7 Divider a Diva der fa CLKOK from Post Scalar CLKFB CLKOK Divtder output clock net routingexternal gt CLKINTFB pin tor CLKINTFB internal feedback r Figure 211 shows the available macros for the PLL Table 25 provides signal description of the PLL Block Figure 21 1 PLL Primitive RST 4 CLKI a a CLKOP CLKFB a a CLKOS DDAMODE a EHXPLLC 4 CLKOK DDAIZR a A LOOK DDAILAG a a CLKINTFB DDAIDEL20 a Architecture Lattice Semiconductor MachXO Family Data Sheet Table 25 PLL Signal Descriptions source For more information on the PLL please see details of additional technical documentation at the end of this data sheet sysMEM Memory The MachXOiZOO and MachX02280 devices contain sysMEM Embedded Block RAMs EBRs The EBR consists of a 9Kbit RAM with dedicated input and output registers sysMEM Memory Block The sysMEM block can implement single port dual port pseudo dual port or FIFO memories Each block can be used in a variety of depths and widths as shown in Table 26 Table 26 sysMEM Block Configurations Memory Mode Configurations 8192x1 4096X2 2048x4 1024X9 512x18 256x36 8192x1 4096x 2 True Dual Port 2048 x 4 1024x 9 512 x 18 8192x1 4096X2 2048x4 1024X9 512x18 256x36 8192x1 4096X2 2048x4 1024X9 512x18 256x36 Single Port Pseudo Dual Port FIFO Architecture Lattice Semiconductor MachXO Family Data Sheet Bus Size Matching All of the multiport memory modes support different widths on each of the portsThe RAM bits are mapped LSB word 0 to MSB word 0 L88 word 1 to MSB word 1 and so on Although the word size and number of words for each port varies this mapping scheme applies to each port RAM Initialization and ROM Operation If desired the contents of the RAM can be preIoaded during device configuration By preloading the RAM block during the chip configuration cycle and disabling the write controls the sysMEM block can also be utilized as a ROM Memory Cascading Larger and deeper blocks of RAMs can be created using EBR sysMEM Blocks Typically the Lattice design tools cascade memory transparently based on specific design inputs Single Dual PseudoDual Port and FIFO Modes Figure 212 shows the five basic memory configurations and their inputoutput names In all the sysMEM RAM modes the input data and address for the ports are registered at the input of the memory array The output data of the memory is optionally registered at the memory array output Figure 2 12 sysMEM Memory Primitives ADUZO AD1 3 ADB120 DIBB 0 DB17 0 CLK CEB CEA CLKB CE DOBS 0 RSTA EBR RSTB RST WEA WEB WE CSA2 0 CSB2 0 CS2 0 DOA17 0 DOB17 0 Singe port RAM True Dual Port RAM ADW12 0 AD12 0 D35 0 4 39 ADR12 0 CLK CLKW CE DOBS 0 CEW DO35 0 RST F g CER CS2 0 CS 0 CLKR ROM PseudoDual Port RAM DO35 0 D35 0 gt CLKW RE RSWTE 1 a ROE CEW 4 FF I4 AF 4 EF AE FIFO Architecture Lattice Semiconductor MachXO Family Data Sheet The EBFl memory supports three forms of write behavior for single or dual port operation Normal data on the output appears only during the read cycle During a write cycle the data at the current address does not appear on the output This mode is supported for all data widths 2 WriteThrough a copy of the input data appears at the output of the same portThis mode is supported for all data widths 3 ReadBeforeWrite when new data is being written the old contents of the address appears at the output This mode is supported for X9 X18 and X36 data widths FIFO Configuration The FIFO has a write port with Datain CEW WE and CLKW signals There is a separate read port with Dataout ROE RE and CLKFl signals The FIFO internally generates Almost Full Full Almost Empty and Empty FIagsThe Full and Almost Full flags are registered with CLKWThe Empty and Almost Empty flags are registered with CLKFl The range of programming values for these flags are in Table 27 Table 27 Programmable FIFO Flag Ranges The FIFO state machine supports two types of reset signals RSTA and RSTB The RSTA signal is a global reset that clears the contents of the FIFO by resetting the readwrite pointer and puts the FIFO flags in their initial reset stateThe RSTB signal is used to reset the read pointerThe purpose of this reset is to retransmit the data that is in the FIFO In these applications it is important to keep careful track of when a packet is written into or read from the FIFO Memory Core Reset The memory array in the EBFl utilizes latches at the A and B output portsThese latches can be reset asynchro nously RSTA and RSTB are local signals which reset the output latches associated with Port A and Port B respec tively The Global Reset GSFlN signal resets both ports The output data latches and associated resets for both ports are as shown in Figure 213 Architecture Lattice Semiconductor MachXO Family Data Sheet Figure 213 Memory Core Reset Pon A170 Port B170 Programmable Disable For further information on the sysMEM EBFl block see the details of additional technical documentation at the end of this data sheet EBR Asynchronous Reset EBFl asynchronous reset or GSFl if used can only be applied if all clock enables are low for a clock cycle before the reset is applied and released a clock cycle after the reset is released as shown in Figure 214 The GSFl input to the EBFl is always asynchronous Figure 214 EBFI Asynchronous Reset Including GSFI Timing Diagram Reset Clock Clock 7 Enable If all clock enables remain enabled the EBFl asynchronous reset or GSFl may only be applied and released after the EBFl read and write clock inputs are in a steady state condition for a minimum of 1fMAX EBFl clock The reset release must adhere to the EBFl synchronous reset setup time before the next active read or write clock edge If an EBFl is preloaded during configuration the GSFl input must be disabled or the release of the GSFl during device Wake Up must occur before the release of the device lOs becoming active These instructions apply to all EBFl RAM ROM and FIFO implementations For the EBFl FIFO mode the GSFl sig nal is always enabled and the WE and RE signals act like the clock enable signals in Figure 214 The reset timing rules apply to the FlPFleset input vs the RE input and the HST input vs the WE and RE inputs Both RST and FlPFleset are always asynchronous EBFl inputs Note that there are no reset restrictions if the EBFl synchronous reset is used and the EBFl GSFl input is disabled Architecture Lattice Semiconductor MachXO Family Data Sheet PIO Groups On the MachXO devices PIO cells are assembled into two different types of PIO groups those with four PIO cells and those with six PIO cells PIO groups with four lOs are placed on the left and right sides of the device while PIO groups with siX lOs are placed on the top and bottom The individual PIO cells are connected to their respective syle buffers and PADs On all MachXO devices two adjacent PlOs can be joined to provide a complementary Output driver pair The lO pin pairs are labeled as quotTquot and quotCquot to distinguish between the true and complement pins The MachXOlZOO and MachX02280 devices contain enhanced lO capability All PIO pairs on these larger devices can implement differential receivers In addition half of the PIO pairs on the left and right sides of these devices can be configured as LVDS transmitreceive pairs PlOs on the top of these larger devices also provide PCI support Figure 215 Group of Four Programmable 0 Cells This structure is used on the left and right of MachXO devices PIo A I PIO B PADB 0 Four PlOs PIO c PADC T Figure 216 Group of Six Programmable 0 Cells This structure is used on the top and bottom of MachXO devices PIO A PADA T PIO B PADB C PIO C PADC T Six PlOs PIO E PADE T PIO F PADF C PIO The PIO blocks provide the interface between the syle buffers and the internal PFU array blocks These blocks receive output data from the PFU array and a fast output data signal from adjacent PFUsThe output data and fast Architecture Lattice Semiconductor MachXO Family Data Sheet output data signals are multiplexed and provide a single signal to the IO pin via the syle buffer Figure 217 shows the MachXO PIO logic The tristate control signal is multiplexed from the output data signals and their complements In addition a global signal TSALL from a dedicated pad can be used to tristate the syle buffer The PIO receives an input signal from the pin via the syle buffer and provides this signal to the core of the device In addition there are programmable elements that can be utilized by the design tools to avoid positive hold times Figure 217 MachXO PIO Block Diagram From Routing 0 T5 TSALL From Routing Fast Output Data signal V V V npu Data Signal Programmable Delay Elements Nole39 Buffer 1 tracks wnh VOCAUX Buffer 2 tracks wnh V 0 0 From Complementary Buffer 3 tracks wnh internal 1 2V VREF Pad Buffer 4 IS available in MachX01200 and MachX02280 deVIces only syle Buffer Each IO is associated with a flexible buffer referred to as a syle buffer These buffers are arranged around the periphery of the device in groups referred to as Banks The syle buffers allow users to implement the wide variety of standards that are found in today s systems including LVCMOS TTL BLVDS LVDS and LVPECL In the MachXO devices singleended output buffers and ratioed input buffers LV I39I39L LVCMOS and PCI are pow ered using VCCIO In addition to the Bank VCCIO supplies the MachXO devices have a VCC core logic power supply and a VCCAUX supply that powers up a variety of internal circuits including all the differential and referenced input buff ers MachX0256 and MachX064O devices contain singleended input buffers and singleended output buffers with complementary outputs on all the IO Banks MachXOlZOO and MachX02280 devices contain two types of syle buffer pairs 1 Top and Bottom syle Buffer Pairs The syle buffer pairs in the top and bottom Banks of the device consist of two singleended output drivers and two sets of singleended input buffers for ratioed or absolute input IevelsThe IO pairs on the top and bottom 215 Architecture Lattice Semiconductor MachXO Family Data Sheet of the devices also support differential input buffers PCI clamps are available on the top Bank IO buffersThe PCI clamp is enabled after VCC VCCAUX and VCCIO are at valid operating levels and the device has been con figured The two pads in the pair are described as true and comp where the true pad is associated with the positive side of the differential input buffer and the comp complementary pad is associated with the negative side of the differential input buffer 2 Left and Right syle Buffer Pairs The syle buffer pairs in the left and right Banks of the device consist of two singleended output drivers and two sets of singleended input buffers supporting ratioed and absolute input levels The devices also have a differential driver per output pair The referenced input buffer can also be configured as a differential input buffer In these Banks the two pads in the pair are described as true and comp where the true pad is asso ciated with the positive side of the differential IO and the comp complementary pad is associated with the negative side of the differential IO Typical IIO Behavior During Powerup The internal poweronreset POR signal is deactivated when VCC and VCCAUX have reached satisfactory levels After the POFI signal is deactivated the FPGA core logic becomes active It is the user s responsibility to ensure that all VCCIO Banks are active with valid input logic levels to properly control the output logic states of all the IO Banks that are critical to the applicationThe default configuration of the IO pins in a blank device is tristate with a weak pullup to VCCIO The IO pins will maintain the blank configuration until VCC VCCAUX and VCCIO have reached satisfactory levels at which time the IOs will take on the userconfigured settings The VCC and VCCAUX supply the power to the FPGA core fabric whereas the VCCIO supplies power to the IO buff ers In order to simplify system design while providing consistent and predictable IO behavior the IO buffers should be powered up along with the FPGA core fabric Therefore VCCIO supplies should be powered up before or together with the V00 and VCCAUX supplies Supported Standards The MachXO syle buffer supports both singleended and differential standards Singleended standards can be further subdivided into LVCMOS and LVTTLThe buffer supports the LVTTL LVCMOS 12 15 18 25 and 33V standards In the LVCMOS and LVTTL modes the buffer has individually configurable options for drive strength bus maintenance weak pullup weak pulldown buskeeper latch or none and open drain BLVDS and LVPECL output emulation is supported on all devices The MachXOlZOO and MachX02280 support onchip LVDS output buffers on approximately 50 of the IOs on the left and right Banks Differential receivers for LVDS BLVDS and LVPECL are supported on all Banks of MachXOlZOO and MachX02280 devices PCI support is provided in the top Banks of the MachXOlZOO and MachX02280 devices Table 28 summarizes the IO characteristics of the devices in the MachXO family Tables 29 and 210 show the IO standards together with their supply and reference voltages supported by the MachXO devices For further information on utilizing the syle buffer to support a variety of standards please see the details of additional technical documentation at the end of this data sheet Lattice Semiconductor MachXO Arch itectu re Family Data Sheet Table 28 0 Support Device by Device MachX0256 MachX0640 MachXO1200 MachX02280 Number of lO Banks 2 4 8 8 Type of Input Buffers Singleended all lO Banks Singleended all lO Banks Singleended all lO Banks Differential Receivers all lO Banks Singleended all lO Banks Differential Receivers all lO Banks Types of Output Buffers Singleended buffers with complementary outputs all lO Banks Singleended buffers with complementary outputs all lO Banks Singleended buffers with complementary outputs all lO Banks Differential buffers with true LVDS outputs 50 on left and right side Singleended buffers with complementary outputs all lO Banks Differential buffers with true LVDS outputs 50 on left and right side Differential Output Emulation Capability A IO Banks A IO Banks A IO Banks A IO Banks PCI Support No No Top side only Top side only Table 29 Supported Input Standards 2 MachXO1200 and MachX02280 devices only Architecture Lattice Semiconductor MachXO Family Data Sheet Table 210 Supported Output Standards 2 These interfaces can be emulated with external resistors in all devices 3 Top Banks of MachXO1200 and MachX02280 devices only syle Buffer Banks The number of Banks vary between the devices of this family Eight Banks surround the two larger devices the MachXOlZOO and MachX02280 two Banks per side The MachX064O has four Banks one Bank per side The smallest member of this family the MachX0256 has only two Banks Each syle butter Bank is capable of supporting multiple lO standards Each Bank has its own lO supply voltage VCCIO which allows it to be completely independent from the other Banks Figure 218 Figure 218 Figure 220 and Figure 221 shows the syle Banks and their associated supplies for all devices Lattice Semiconductor Architecture MachXO Family Data Sheet Figure 218 MachX 02280 Banks unu V Luluo Figure 219 MachXO1200 Banks unu V Luluo 8lt 3 8lt 3 a D g D I I 1 1 39 I 39 I I I l I 11 BankO 35 1 Bank1 6 I I 1 l I I El IVch02 I I l I I In l I mm L 134 34LJ I1 1quot I 392 El 39 VIM 395 39 I 39m I I cum 133 Bank5 Bank433l39 quot J 1 135 I I 39 I I I 39 I l I E39 c 39 8 2 8 2 gt L gt L 8lt 3 8lt 3 a D g D I I 1 II 39 I II 39 I I I l 39 l I 11 BankO 24 1 Bank1 30 I 1 I I I El lvccloz I I l I I In l I mm 26 26J I1 1quot I I ml I wa I 395 El I m L In I I cum J28 28 Bank5 Bank4 L quot J 1 2o 1 9 I 39 I 39 I I I 39 I 39 IJ I 4 3 3 I 8 E 8 2 gt c gt L Lattice Semiconductor Arch itectu re MachXO Family Data Sheet Figure 220 MachX 0640 Banks V 0003 V ccot Figure 221 MachX 0256 Banks I Mn any V ccoo V 0001 Hot Socketing al uJ The MachXO devices have been carefully designed to ensure predictable behavior during powerup and power down Leakage into IO pins is controlled to within specified imitsThis allows for easy integration with the rest of Architecture Lattice Semiconductor MachXO Family Data Sheet the system These capabilities make the MachXO ideal for many multiple power supply and hotswap applica tions Sleep Mode The MachXO C devices VCC 182533V have a sleep mode that allows standby current to be reduced dra matically during periods of system inactivity Entry and exit to Sleep mode is controlled by the SLEEPN pin During Sleep mode the logic is nonoperational registers and EBFl contents are not maintained and lOs are tri stated Do not enter Sleep mode during device programming or configuration operation In Sleep mode power sup plies are in their normal operating range eliminating the need for external switching of power supplies Table 211 compares the characteristics of Normal Off and Sleep modes Table 21 1 Characteristics of Normal Off and Sleep Modes SLEEPN Pin Characteristics The SLEEPN pin behaves as an LVCMOS input with the voltage standard appropriate to the V00 supply for the device This pin also has a weak pullup along with a Schmidt trigger and glitch filter to prevent false triggering An external pullup to VCC is recommended when Sleep Mode is not used to ensure the device stays in normal oper ation mode Typically the device enters sleep mode several hundred nanoseconds after SLEEPN is held at a valid low and restarts normal operation as specified in the Sleep Mode Timing table The AC and DC specifications por tion of this data sheet shows a detailed timing diagram Oscillator Every MachXO device has an internal CMOS oscillator The oscillator can be routed as an input clock to the clock tree or to general routing resources The oscillator frequency can be divided by internal logic There is a dedicated programming bit to enabledisable the oscillatorThe oscillator frequency ranges from 18MHZ to 26MHZ Configuration and Testing The following section describes the configuration and testing features of the MachXO family of devices IEEE 11491Compliant Boundary Scan Testability All MachXO devices have boundary scan cells that are accessed through an IEEE 11491 compliant test access port TAPThis allows functional testing of the circuit board on which the device is mounted through a serial scan path that can access all critical logic nodes Internal registers are linked internally allowing test data to be shifted in and loaded directly onto test nodes or test data to be captured and shifted out for verification The test access port consists of dedicated lOs TDI TDO TCK and TMS The test access port shares its power supply with one of the VCCIO Banks MachX0256 VCCIO1 MachX0640 VCCIOZ MachXO1200 and MachX02280 VCCIO5 and can operate with LVCMOSS3 25 18 15 and 12 standards For more details on boundary scan test please see information regarding additional technical documentation at the end of this data sheet Architecture Lattice Semiconductor MachXO Family Data Sheet Device Configuration All MachXO devices contain a test access port that can be used for device configuration and programming The nonvolatile memory in the MachXO can be configured in two different modes In IEEE 1532 mode via the IEEE 11491 port In this mode the device is offline and IOs are controlled by BSCAN registers In background mode via the IEEE 11491 port This allows the device to remain operational in user mode while reprogramming takes place The SRAM configuration memory can be configured in three different ways At powerup via the onchip nonvolatile memory After a refresh command is issued via the IEEE 11491 port In IEEE 1532 mode via the IEEE 11491 port Figure 222 provides a pictorial representation of the different programming modes available in the MachXO devices On powerup the SRAM is ready to be configured with IEEE 11491 serial TAP port using IEEE 1532 pro tocols Leave Alone IIO When using IEEE 1532 mode for nonvolatile memory programming SRAM configuration or issuing a refresh command users may specify IOs as high low tristated or held at current value This provides excellent flexibility for implementing systems where reconfiguration or reprogramming occurs onthefly TransFR Transparent Eield Beconfiguration TransFFl TFFl is a unique Lattice technology that allows users to update their logic in the field without interrupting system operation using a single ispVM command See Lattice technical note TN1087 Minimizing System Inter ruption During Configuration Using TransFR Technology for details Security The MachXO devices contain security bits that when set prevent the readback of the SRAM configuration and nonvolatile memory spaces Once set the only way to clear the security bits is to erase the memory space For more information on device configuration please see details of additional technical documentation at the end of this data sheet Architecture Lattice Semiconductor MachXO Family Data Sheet Figure 222 MachXO Configuration and Programming ISP 11491 TAP Port Port Background 1532 Mode Program in seconds Configure in milliseconds l NonVolatile Memory Space l l l 1 Download in 1 l microseconds l l DenSIty Shifting The MachXO family has been designed to enable density migration in the same package Furthermore the archi tecture ensures a high success rate when performing design migration from lower density parts to higher density parts In many cases it is also possible to shift a lower utilization design targeted for a highdensity device to a lower density device However the exact details of the final resource utilization will impact the likely success in each case MachXO Family Data Sheet 3339ng 39 DC and Switching Characteristics November 2007 Data Sheet DS1002 Absolute Maximum Ratingsquot 239 3 LCMXO E 12V LCMXO C 18Vl25V33V Supply Voltage VCC O5 to 132V O5 to 375V Supply Voltage VCCAUX O5 to 375V O5 to 375V Output Supply Voltage VCCIO O5 to 375V O5 to 375V IO Tristate Voltage Applied 4 O5 to 375V O5 to 375V Dedicated Input Voltage Applied4 O5 to 375V O5 to 425V Storage Temperature ambient 65 to 150 C 65 to 150 C Junction Temp Tj 125 C 125 C 1 Stress above those listed underthe Absolute Maximum Ratingsquot may cause permanent damage to the device Functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Compliance with the Lattice ThermalManagement document is required All voltages referenced to GND 4 Overshoot and undershoot of 2V to VIHMAX 2 volts is permitted for a duration of lt20ns 9quotquot3 Recommended Operating Conditions power and 12V VCCIO should be tied to VCCAUX or 12V Vcc 2 See recommended voltages by HG standard in subsequent table 3 Vcc must reach minimum Vcc value before VCCAUX reaches 25V MachX0256 and MachXO640 Hot Socketing Specifications 3 Symbol Parameter Condition Min Typ Max Units lIDK Input or IO leakage Current lo 5le s le MAX l l l 1ooo l uA l 1 Insensitive to sequence of Vccv VCCAUXV and VCCIO However assumes monotonic risefall rates foercv VCCAUXV and VCCIO 2 o s Vcc 5 vcc MAX 0 s vCCIO s vCCIO MAX and o s vCCAUX s vCCAUX M 3 IDK is additive to IPUV IPD or IBH L Corp All Lattice trademarks regi rereu llduellldle patents and I 39 39m r r 39I l d All other brand or product names are trademarks or their p h 39d h r quotPquot 39to change wrthout notice wwwlatticesemicom 31 DStOOZ DC and Switching016 DC and Switching Characteristics Lattice Semiconductor MachXO Family Data Sheet MachXO1200 and MachX02280 Hot Socketing Specification3139239339 4 s 7LVDS or IO Leakage Current gt 1 lnsensitive to sequence of Vccv VCCAUXV and VCCIO However assumes monotonic risefall rates foercv VCCAUXV and VCCIO 2 o s Vcc 5 vcc MAX 0 s vCCIO s vCCIO MAX and o s vCCAUX s vCCAUX MAX 3 IDK is additive to IPUV lpw or IBH 4 LVCMOS and LVTTL only DC Electrical Characteristics Over Recommended Operating Conditions II 5 Input or IO Leakage s s s 2 IO CapaCItance Typ O to MAX 2 Dedicated Input CapaCItance Typ O to MAX as an or as an output with the output active Bus maintenance circuits are disabled TA 25 C f 10MHZ Please refer to VIL and VIH in the syle SingleEnded DC Electrical Characteristics table of this document Not applicable to SLEEPN pin When VIH is higherthan VCCIO a transient current typically of 30ns in duration or less with a peak current of 6mA can occur on the highto low transition For MachXO1200 and MachX02280 true LVDS output pins VIH must be less than or equal to VCCIO 511439quot DC and Switching Characteristics Lattice Semiconductor MachXO Family Data Sheet Supply Current Sleep Modequot2 Power Supply Power Supply are as 2 Frequency 3 TA 25 C power supplies at nominal voltage 4 Per Bank Supply Current Standby1 2 34 Over Recommended Operating Conditions Power Supply Power Supply 33V Forfurther information on supply current please see details of additional technical documentation at the end of this data sheet Assumes a outputs are tristated all inputs are configured as LVCMOS and held at VCCIO or GND Frequency OMHZ User pattern blank TJ 25 C power supplies at nominal voltage Per Bank VCCIO 25V Does not include pulluppulldown 901 97 DC and Switching Characteristics Lattice Semiconductor MachXO Family Data Sheet Initialization Supply Current 4 Over Recommended Operating Conditions Power Supply Power Supply 33V Forfurther information on supply current please see details of additional technical documentation at the end of this data sheet Assumes a O pins are held at VCCIO or Frequency OMHZ Typical user pattern TJ 25 C power supplies at nominal voltage Per Bank VCCIO 25V Does not include pulluppulldown 99 9 9 NT DC and Switching Characteristics Lattice Semiconductor MachXO Family Data Sheet Programming and Erase Flash Supply Current 4 Power Supply Power Supply 33V see current Assumes all O pins are held atVCCIO or GND Typical user pa ern JTAG programming is at 25MHZ TJ 25 C power supplies at nominal voltage Per Bank VCCIO 25V Does not include pulluppulldown wwm DC and Switching Characteristics Lattice Semiconductor MachXO Family Data Sheet syle Recommended Operating Conditions Standard on are 2 and devices have dedicated LVDS buffers 3 Input on the top bank of the MachXO1200 and MachX02280 only DC and Switching Characteristics Lattice Semiconductor MachXO Family Data Sheet syle SingleEnded DC Electrical Characteristics InputOutput l VIL VIH V0L Max VOH Min IOL IOH ndard Min V Max V Min V Max V V V mA mA 04 vCCIO 04 16 12 8 4 14 12 8 4 LVCMOS 33 03 08 20 36 02 VCCIO 02 01 01 04 24 16 16 LVTTL 03 08 20 36 04 VCCIO 04 12 8 4 12 8 4 02 VCCIO 02 01 01 04 VCCIO 04 16 12 8 4 14 12 8 4 LVCMOS 25 03 07 17 36 02 VCCIO 02 01 01 04 VCCIO 04 16 12 8 4 14 12 8 4 LVCMOS 18 03 035vCCIO 065vCCIO 36 02 vCCIO 02 01 01 04 vCCIO 04 8 4 8 4 LVCMOS 15 03 035vCCIO 065vCCIO 36 02 VCCIO 02 01 01 04 v 04 6 2 6 2 LngOS 1392 03 042 078 36 CC39O 0 VerSIon 02 VCCIOO2 01 01 LVCMOS 12 04 cho 04 6 2 6 2 03 035v 065v 36 E VerSIon CC CC 02 VCCIO 02 01 01 PCI 03 03vcCIO 05vcCIO 36 01vcCIO 09VCCIO 15 05 1 The average DC current drawn by Os between GND connections or between the last GND in an O Bank and the end of an O Bank as shown in the logic signal connections table shall not exceed n BmA Where n is the number of Os between Bank GND connections or between the last GND in a Bank and the end of a Bank DC and Switching Characteristics Lattice Semiconductor MachXO Family Data Sheet syle Differential Electrical Characteristics LVDS Over Recommended Operating Conditions Symbol Parameter Description Test Conditions Min Typ Common Mode Voltage short circuit current LVDS Emulation MachXO devices can support LVDS outputs via emulation LVDSZSE in addition to the LVDS support that is avail able onchip on certain devicesThe output is emulated using complementary LVCMOS outputs in conjunction with resistors across the driver outputs on all devices The scheme shown in Figure 31 is one possible solution for LVDS standard implementation Resistor values in Figure 31 are industry standard values for 1 resistors Figure 31 LVDS Using External Resistors LVDS25E VCCIO 25 Onchip Offchip Offchip Onchip 2 4 3 Emulated i LVDS Buffer Note All resistors are 11 The LVDS differential input buffers are available on certain devices in the MachXO family DC and Switching Characteristics Lattice Semiconductor MachXO Family Data Sheet Table 31 LVDS DC Conditions Over Recommended Operating Conditions Common BLVDS The MachXO family supports the BLVDS standard through emulation The output is emulated using complemen tary LVCMOS outputs in conjunction with a parallel external resistor across the driver outputsThe input standard is supported by the LVDS differential input buffer on certain devices BLVDS is intended for use when multidrop and bidirectional multipoint differential signaling is requiredThe scheme shown in Figure 32 is one possible solution for bidirectional multipoint differential signals Figure 32 BLVDS Multipoint Output Example Heavily loaded backplane effective Zo 45 to 90 ohms differential DC and Switching Characteristics Lattice Semiconductor MachXO Family Data Sheet Table 32 BLVDS DC Conditions Over Recommended Operating Conditions Symbol Description Common LVPECL The MachXO family supports the differential LVPECL standard through emulation This output standard is emu lated using complementary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs on all the devices The LVPECL input standard is supported by the LVDS differential input buffer on certain devices The scheme shown in Figure 33 is one possible solution for pointtopoint signals Figure 33 Differential LVPECL 100 ohms i l 150 ohms 100 ohms l l 100 ohms 1 Transmission line 20 100 ohm differential i i Offchip Offchip Onchip gt 4 i gt i Table 33 LVPE CL DC Conditions Over Recommended Operating Conditions Common DC and Switching Characteristics Lattice Semiconductor MachXO Family Data Sheet For further information on LVPECL BLVDS and other differential interfaces please see details of additional techni cal documentation at the end of the data sheet RSDS The MachXO family supports the differential RSDS standardThe output standard is emulated using complemen tary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs on all the devices The RSDS input standard is supported by the LVDS differential input buffer on certain devicesThe scheme shown in Figure 3 4 is one possible solution for RSDS standard implementation Use LVD825E mode with suggested resistors for RSDS operation Resistor values in Figure 34 are industry standard values for 1 resistors Figure 34 RSDS Reduced Swing Differential Standard VCCIO 25V 20 100 1 i VCCIO 1 121 100 1 i 1 i 1 1 Onchip 1 Offchip Offchip 1 Onchip lt gt lt gt Emulated i i RSDS Buffer Table 34 RSDS DC Conditions Common DC and Switching Characteristics Lattice Semiconductor MachXO Family Data Sheet Typical Building Block Function Performance PintoPin Performance LVCMOS25 12mA Drive RegistertoRegister Performance are tool version The uses internal parameters been characterized but are not tested on every device Rev A 019 Derating Logic Timing Logic Timing provided in the following sections of the data sheet and the ispLEVEFl design tools are worst case numbers in the operating range Actual delays may be much faster The ispLEVEFl design tool from Lattice can pro vide logic timing numbers at a particular temperature and voltage DC and Switching Characteristics Lattice Semiconductor MachXO Family Data Sheet MachXO External Switching Characteristics Over Recommended Operating Conditions Parameter Description Device Case tpD Through 1 LUT Case Clock to Output From PFU Data Setup To PFU Data Hold To PFU Frequency of IO and PFU Register Clock Skew Across Device RevA019 DC and Switching Characteristics Lattice Semiconductor MachXO Family Data Sheet MachXO Internal Timing Parameters Over Recommended Operating Conditions Parameter Description on every Rev A 019 DC and Switching Characteristics Lattice Semiconductor MachXO Family Data Sheet MachXO Family Timing Addersm3 Over Recommended Operating Conditions are 0 2 is measured with the load specified in Switching Test Conditions table 3 All other standards tested according to the appropriate specifications 4 HO standard only available in LCMXO1200 and LCMX02280 devices Rev A 019 DC and Switching Characteristics Lattice Semiconductor MachXO Family Data Sheet sysCLOCK PLL Timing Over Recommended Operating Conditions Clock Period Jitter over output a 2 Output clock is valid aftertLOCK for PLL reset and dynamic delay adjustment 3 Using LVDS output buffers 4 CLKOS as compared to CLKOP output Rev A 019 MachXO C Sleep Mode Timing High to Power Up RevA019 4 Dower Down M quot IIO 4 PWRUP 4b lPWHDN J J SLEEPN WSLEEPN 0T 1WAWAKE 316 DC and Switching Characteristics Lattice Semiconductor MachXO Family Data Sheet Flash Download Time Vcc 0 VCCAUX of the two supplies Device IO Active JTAG Port Timing Specifications RevA019 Figure 35 JTAG Port Timing Waveforms TMS BTS 47 BTH BTCPH 47 BTCPL 4p 39m r T g f IBTCOEN BTco BTCODlS TDO Valid Data Valid Data BTCRS BTCRH Data to be captured Data Captured irom O L BTUPOEN L BUTCO L BTUODiS Data to be amen 0m Valid Data Valid Data to IIO DC and Switching Characteristics Lattice Semiconductor MachXO Family Data Sheet Switching Test Conditions Figure 36 shows the output test load that is used for AC testing The specific values for resistance capacitance voltage and other test conditions are shown in Figure 35 Figure 36 Output Test Load LVTTL and LVCMOS Standards 0 Test Point CL I Table 35 Test Fixture Required Components NonTerminated Interfaces and LVCMOS settings L gt H H gt L MachXO Family Data Sheet 39 39J J3 l lf Pinout Information November 2007 Data Sheet DS1002 Signal Descriptions Signal Name lO Descriptions General Purpose Edge indicates the edge of the device on which the pad is located Valid edge designa tions are L Left B Bottom R Right T Top RowColumn Number indicates the PFU row or the column of the device on which the PIO Group exists When Edge is T Top or Bottom only need to specify Row Number When Edge is L Left or R Right only need to specify Column Number PEdge ROWColumn IO ABCDEF Indicates the PIO Within the group to which the pad Is connected Numbe iABCDEF Some of these user programmable pins are shared with special function pins When not used as special function pins these pins can be programmed as IOs for user logic During configuration of the userprogrammable IOs the user has an option to tristate the IOs and enable an internal pullup resistor This option also applies to unused pins or those not bonded to a package pin The default during configuration is for userprogram mable IOs to be tristated with an internal pullup resistor enabled When the device is erased IOs will be tristated with an internal pullup resistor enabled GSRN I Global RESET signal active low Dedicated pad when not in use it can be used as an IO TSALL I TSALL is a dedicated pad for the global output enable signal When TSALL is high all the outputs aretristated It is a dual function pin When not in use it can be used as an IO pin NC No connect GND GND Ground Dedicated pins VCC VCC The power supply pins for core logic Dedicated pins VCCAUX VCCAUX the Auxiliary power supply pin This pin powers up a variety of internal circuits including all the differential and referenced input buffers Dedicated pins VCCIOX VCCIO The power supply pins for IO Bank x Dedicated pins Sleep Mode pin Active low sleep pin When this pin is held high the device operates nor mally This pin has a weak internal pullup but when unused an external pullup to VCC is recommended When driven low the device moves into Sleep mode after a specified time PLL and Clock Functions Used as user programmable IO pins when not used for PLL or clock pins SLEEPN Reference clock PLL input Pads LOC indicates location Valid designations are ULM LOCHOLPLLU CLIN Upper PLL and LLM Lower PLL T true and C complement Optional feedback PLL input Pads LOC indicates location Valid designations are ULM LOCHOLPLLU CLFB Upper PLL and LLM Lower PLL T true and C complement PCLK n10 Primary Clock Pads n per side Test and Programming Dedicated pins TMS Test Mode Select input pin used to control the 11491 state machine TCK Test Clock input pin used to clockthe 11491 state machine TDI Test Data input pin used to load data into the device using an 11491 state machine TDO 0 Output pin Test Data output pin used to shift data out of the device using 11491 1 Applies to MachXO C devices only NC for E devices 2006 Lattice Semiconductor Corp All Lattice trademarks registered trademarks patents and disclaimers are as listed atwwwlatticesemi comlegal All other brand or product names are trademarks or their r b M T r quotPquot 39to change Without notice wwwlatticesemicom 41 D81002 Pinouts7017 Pinout Information Lattice Semiconductor MachXO Family Data Sheet Pin Information Summary Pin Pinout Information Lattice Semiconductor MachXO Family Data Sheet Power Supply and NC 17 35 66 91 B12 BS H14A14 P4 P10 G1F 1 36 9O 64 11 27 N10 40 84 81 93 62 75 N9 B9 A10 A4 B13 N3 N10 H1 N2 9415983 100 76 50 26 2 Pin orientation A1 starts from of the ascending vertically and numerical order ascending horizontally 3 All For prGA the total number of GND balls is less than the actual number of logic connections from to the common package GND plane 4 NC pins should not be connected to any active signals VCC or GND Pinout Information Lattice Semiconductor MachXO Family Data Sheet Power Supply and NC Cont F8 F7 F9F1O H11G11 K11J11 L9L1O L8L7 K6J6 H6G6 J7J8J9J10 k9L6 1J4 J9K10K1 K 16 L10L L8L9N2P14P5 G4G5H4H5K5K4M5 P2P3N5N6M7M8N1Q 1R15R16P15P16M1t 1N12N13M13M12K1z F13E12E13D13 A15C14B14E1t E7 D4D3BSBZ None None 2 All For BGA packages the balls IS less than number from the die to the common package GND plane 3 NC plns should not be connected to any active signals VCC or G Pinout Information Lattice Semiconductor MachXO Family Data Sheet LCMX0256 and LCMXO640 Logic Signal Connections 100 TQFP Pin Number Function Bank Function Differential Function Bank Function Differential Pinout Information Lattice Semiconductor MachXO Family Data Sheet LCMX0256 and LCMXO640 Logic Signal Connections 100 TQFP Cont Pin Number Function Bank Function Differential Function Bank Function Differential Pinout Information Lattice Semiconductor MachXO Family Data Sheet LCMX0256 and LCMXO640 Logic Signal Connections 100 TQFP Cont Pin Number Function Bank Function Differential Function Bank Function Differential quot Primary clock inputs are singleended Pinout Information Lattice Semiconductor MachXO Family Data Sheet LCMXO1200 and LCMX02280 Logic Signal Connections 100 TQFP Pin Number Function Bank Function Differential Function Bank Function Differential GNDIOS GNDIOS Pinout Information Lattice Semiconductor MachXO Family Data Sheet LCMXO1200 and LCMX02280 Logic Signal Connections 100 TQFP Cont Pin Number Function Bank Function Differential Function Bank Function Differential GNDO4 GNDIO4 GNDIOZ GNDIOZ Pinout Information Lattice Semiconductor MachXO Family Data Sheet LCMXO1200 and LCMX02280 Logic Signal Connections 100 TQFP Cont Pin Number Function Bank Function Differential Function Bank Function Differential 100 GNDO7 39 GNDIO7 quotDouble bonded to the pin quotNC for quotEquot devices quotquotPrimary clock inputs are singleended Pinout Information Lattice Semiconductor MachXO Family Data Sheet LCMX0256 and LCMXO640 Logic Signal Connections 100 csBGA Number Function Bank Function tial Number Function Bank Function tial Pinout Information Lattice Semiconductor MachXO Family Data Sheet LCMX0256 and LCMXO640 Logic Signal Connections 100 csBGA Cont Number Function Bank Function tial Number Function Bank Function tial Pinout Information Lattice Semiconductor MachXO Family Data Sheet LCMX0256 and LCMXO640 Logic Signal Connections 100 csBGA Cont Number Function Bank Function tial Number Function Bank Function tial quotPrimary clock inputs are singleended Pinout Information Lattice Semiconductor MachXO Family Data Sheet LCMXO640 LCMXO1200 and LCMX02280 Logic Signal Connections 132 csBGA Pinout Information Lattice Semiconductor MachXO Family Data Sheet LCMXO640 LCMXO1200 and LCMX02280 Logic Signal Connections 132 csBGA Cont Pinout Information Lattice Semiconductor MachXO Family Data Sheet LCMXO640 LCMXO1200 and LCMX02280 Logic Signal Connections 132 csBGA Cont devlces 39Prlmary clock Inputs arer slnglerended Pinout Information Lattice Semiconductor MachXO Family Data Sheet LCMXO640 LCMXO1200 and LCMX02280 Logic Signal Connections 144 TQFP Differential Pin Nu mber Pinout Information Lattice Semiconductor MachXO Family Data Sheet LCMXO640 LCMXO1200 and LCMX02280 Logic Signal Connections 144 TQFP Cont Differential Pin Nu mber Pinout Information Lattice Semiconductor MachXO Family Data Sheet LCMXO640 LCMXO1200 and LCMX02280 Logic Signal Connections 144 TQFP Cont Differential Pin Nu mber quotNC for E devices quotPrimary clock inputs arer singleended Pinout Information Lattice Semiconductor MachXO Family Data Sheet LCMXO640 LCMXO1200 and LCMX02280 Logic Signal Connections 256 ftBGA Pinout Information Lattice Semiconductor MachXO Family Data Sheet LCMXO640 LCMXO1200 and LCMX02280 Logic Signal Connections 256 ftBGA Cont Pinout Information Lattice Semiconductor MachXO Family Data Sheet LCMXO640 LCMXO1200 and LCMX02280 Logic Signal Connections 256 ftBGA Cont Pinout Information Lattice Semiconductor MachXO Family Data Sheet LCMXO640 LCMXO1200 and LCMX02280 Logic Signal Connections 256 ftBGA Cont Pinout Information Lattice Semiconductor MachXO Family Data Sheet LCMXO640 LCMXO1200 and LCMX02280 Logic Signal Connections 256 ftBGA Cont Pinout Information Lattice Semiconductor MachXO Family Data Sheet LCMXO640 LCMXO1200 and LCMX02280 Logic Signal Connections 256 ftBGA Cont Pinout Information Lattice Semiconductor MachXO Family Data Sheet LCMX02280 Logic Signal Connections 324 ftBGA Pinout Information Lattice Semiconductor MachXO Family Data Sheet LCMX02280 Logic Signal Connections 324 ftBGA Cont Pinout Information Lattice Semiconductor MachXO Family Data Sheet LCMX02280 Logic Signal Connections 324 ftBGA Cont Pinout Information Lattice Semiconductor MachXO Family Data Sheet LCMX02280 Logic Signal Connections 324 ftBGA Cont Pinout Information Lattice Semiconductor MachXO Family Data Sheet LCMX02280 Logic Signal Connections 324 ftBGA Cont Pinout Information Lattice Semiconductor MachXO Family Data Sheet LCMX02280 Logic Signal Connections 324 ftBGA Cont Pinout Information Lattice Semiconductor MachXO Family Data Sheet LCMX02280 Logic Signal Connections 324 ftBGA Cont Pinout Information Lattice Semiconductor MachXO Family Data Sheet LCMX02280 Logic Signal Connections 324 ftBGA Cont Pinout Information Lattice Semiconductor MachXO Family Data Sheet LCMX02280 Logic Signal Connections 324 ftBGA Cont Pinout Information Lattice Semiconductor MachXO Family Data Sheet LCMX02280 Logic Signal Connections 324 ftBGA Cont true outputs m Primary clock inputs are singleended Pinout Information Lattice Semiconductor MachXO Family Data Sheet Thermal Management Thermal management is recommended as part of any sound FPGA design methodology To assess the thermal characteristics of a system Lattice specifies a maximum allowable junction temperature in all device data sheets Designers must complete a thermal analysis of their specific design to ensure that the device and package do not exceed the junction temperature limits Refer to the Thermal Management document to find the devicepackage specific thermal values For Further Information For further information regarding Thermal Management refer to the following located on the Lattice website at wwwlatticesemicom Thermal Management document Technical Note TN109O Power Estimation and Management for MachXO Devices Power Calculator tool included with Lattice s ispLEVEFl design tool or as a standalone download from wwwlatticesemicomsoftware MachXO Family Data Sheet 39 p 3t f 39 Ordering Information August 2006 Data Sheet DS1002 Part Number Description LCMXO XXXX X X XXXXXX X XX Device Family J 1 E8 Engineering Sample MachXO CrOSSOVer PLD Blank Production Device Grade Logic Capacity 256 LUTs 256 I0 quotmtglrc39a39 640 LUTs 640 1200 LUTs 1200 Package 2280 LUTs 2280 T100 2 100pin TQFP T144 144pin TQFP Supp39y V quotage M100 1ooban csBGA E l39ggZ39SVs39sv M132 132ball csBGA FT256 256ball ftBGA FT324 324ball ftBGA Note Parts dual marked as described TN100 100pin LeadFree TQFP TN144 144pin LeadFree TQFP MN100 tooball LeadFree csBGA MN132 132ball LeadFree csBGA FTN256 256ball LeadFree ttBGA FTN324 324ball LeadFree ttBGA Speed 3 Slowest 4 5 Fastest Ordering Information Note MachXO devices are dual marked except the slowest commercial speed grade device For example the com mercial speed grade LCMX064OE4F2560 is also marked with industrial grade 3 grade The slowest commercial speed grade does not have industrial markings The markings appears as follows attics LCMX0640E 4F25603I Datecode Dual Mark 2006 Lattice Semiconductor Corp All Lattice trademarks registered trademarks patents and disclaimers are as listed atwwwlatticesemi comlegal All other brand or product names are trademarks or their r h M r quotPquot 39to change wrthout notice wwwlatticesemicom 51 D81 OO2 Ordering Informationiot 5 Ordering Information Lattice Semiconductor MachXO Family Data Sheet Conventional Packaging Commercial Ordering Information Lattice Semiconductor MachXO Family Data Sheet Ordering Information Lattice Semiconductor MachXO Family Data Sheet Ordering Information Lattice Semiconductor MachXO Family Data Sheet Conventional Packaging Industrial Ordering Information Lattice Semiconductor MachXO Family Data Sheet Ordering Information Lattice Semiconductor MachXO Family Data Sheet LeadFree Packaging Commercial Ordering Information Lattice Semiconductor MachXO Family Data Sheet Ordering Information Lattice Semiconductor MachXO Family Data Sheet Ordering Information Lattice Semiconductor MachXO Family Data Sheet LeadFree Packaging Industrial Ordering Information Lattice Semiconductor MachXO Family Data Sheet MachXO Family Data Sheet 39 3a39t n 39 Supplemental Information November 2007 Data Sheet DS1002 For Further Information A variety of technical notes for the MachXO family are available on the Lattice web site at wwwatticesemicom MachXO sysIO Usage Guide TN1091 MachXO sysCLOCK PLL Design and Usage Guide TN1089 MachXO Memory Usage Guide TN1092 Power Estimation and Management for MachXO Devices TN1090 MachXO JTAG Programming and Configuration User s Guide TN1086 Minimizing System Interruption During Configuration Using TransFFt Technology TN1087 MachXO Density Migration TN1097 IEEE 11491 Boundary Scan Testability in Lattice Devices For further information on interface standards refer to the following web sites JEDEC Standards LVTTL LVCMOS www39edecorg PCwwwbcisigcom 2007 Lattice Semiconductor Corp All Lattice trademarks registered trademarks patents and disclaimers are as listed atwwwlatticesemi comlegal All other brand or product names are trademarks or their r b 39d r quotPquot 39to change Without notice wwwlatticesemicom 61 D81002 Further Informationiot 2 MachXO Family Data Sheet E w l fquot Revision History November 2007 Data Sheet DS1002 Revision History packaging to the family selection Characteristics Information summary in 100 TQFP package Characteristics 2007 Lattice Semiconductor Corp All Lattice trademarks registered trademarks patents and disclaimers are as listed atwwwlatticesemi comlegal All other brand or product names are trademarks or their r k 39d r quotPquot 39to change Without notice wwwlatticesemicom 71 Revision History Lattice Semiconductor MachXO Family Data Sheet Characteristics Footnotes have been updated have been updatd Revision History Lattice Semiconductor MachXO Family Data Sheet Characteristics 400ns changed from max to min for tWAWAKE rom min to max Characteristics Characteristics Information 0 Section II MachXO Family Technical Notes MachXO syle Usage Guide 39 Semiconductor Corporation July 2007 Technical Note TN1091 Introduction The Lattice MachXO sysIOTM buffers give the designer the ability to easily interface with other devices using advanced system IO standards This technical note describes the sysIO standards available and how they can be implemented using Lattice s design software syle Buffer Overview The Lattice MachXO sysIO interface contains multiple Programmable IO Cell PIC blocks Each PIC contains two Programmable IOs PlOs Two adjacent PIOs can be joined to provide a differential IO pair labeled as T and C In the MachX0256 MachXOIZOO and MachX02280 devices the PIOs are arranged in groups of siX PIOA PIOB PIOC PIOD PIOE PIOF on the top and bottom sides of the device and in groups of four PIOA PIOB PIOC PIOD and two PIOA PIOB on the left and right sides of the device In the MachX064O device the PIOs are arranged in groups of siX PIOA PIOB PIOC PIOD PIOE PIOF on the top and bottom sides and in groups of four PIOA PIOB PIOC PIOD on the left and right sides of the device The larger two devices MachXOIZOO and MachX02280 support singleended differential receiver and differential output sysIO buffersThe two smaller devices MachX0256 and MachX0640 support singleended sysIO buffers For more information on the architecture of the sysIO buffer please refer to the device data sheets Supported syle Standards The MachXO sysIO buffer supports both singleended and differential standards Singleended standards can be further subdivided into LVCMOS LVTTL and other standards The buffers support the LVTTL LVCMOS 12 15 18 25 and 33V standards In the LVCMOS and LVTTL modes the buffer has individually configurable options for drive strength bus maintenance weak pullup weak pulldown or buskeeper latch on IO buffers MachXOIZOO and MachX02280 devices also support differential standards like LVDS FISDS BLVDS and LVPECL Table 81 lists the sysIO standards supported in the MachXO devices Table 81 sysIO Standards Supported Standard on are 2 devices have dedicated LVDS buffers 3 Input on the top bank of the MachXO1200 and MachX02280 only 2007 Lattice Semiconductor Corp All Lattice trademarks registered trademarks patents and disclaimers are as listed at wwwlatticesemi comlegal All other brand or product names are trademarks or registered trademarks of their r k 39d T r r h it Hung m on wwwlatticesemicom 81 tn10917014 Lattice Semiconductor MachXO syle Usage Guide syle Banking Scheme The MachXO family has a nonhomogeneous lO banking structure The MachX0256 has two lO banks the MachX064O has four lO banks and the two largest devices the MachXOlZOO and the MachX02280 have eight lO banks The figures below show the banking structures in each of the devices Each syle bank has a VCCIO supply voltage On the MachXOlZOO and MachX02280 devices the top and bottom banks of the syle buffer pair consist of two singleended output drivers two singleended and one differential input buffer The syle buffers on the top side bank also supports PCI buffers The left and right side syle buffer pairs along with the two singleended output and input drivers a differential input and a differential driver on half the llOs of the bank On the MachX064O and MachX0256 devices all the banks of the syle buffer pair consists of two singleended output drivers with com plementary outputs and two singleended and input buffers All the banks will also support differential output buff ers using external resistors The two pads in the pair are described as true and comp where the true pad is associated with the positive side of the differential input buffer and the comp complementary pad is associated with the negative side of the differential input buffer Figures 1 2 and 3 show the banking schemes for the MachX0640 MachX0256 and MachXOlZOOMachXOZZBO devices respectively Figure 81 MachX0256 sysIO Banking any c Mm 1 1 I Mn VCCDI Lattice Semiconductor MachXO syle Usage Guide Figure 82 MachX0640 sysIO Banking lt m z D 39 3911 BankO 1 39 I V0003 g F I vccoI s I I mu m ND M Jr Bank2 NMI J N l s 5 gt c Figure 83 MachXO 1200 and MachX 02280 sysIO Banking lt m lt m 8 Z 8 2 0 l U I 1 q l 39 I I d I 1 11 BankO N 1 Bank1 N I 1 l V I u I IVch02 I g g I mm In l I am 1M MI J 1 1quot I m I I VW I g 2 I uNu w NC in w I M Bank5 Bank4 ML quot J 1 N 1 N I 39 l 39 l I IJ 4 E I 8 E 8 2 gt L gt L Lattice Semiconductor MachXO syle Usage Guide vCCIO 12V15VI18V25V33V Each bank has a separate VCCIO supply that powers the singleended output drivers and the ratioed input buffers such as LVTTL LVCMOS and PCI LVTTL LVCMOS33 LVCM0825 and LVCMOSt2 also have fixed threshold options allowing them to be placed in any bank and is independent of bank VCCIOThe VCCIO voltage applied to the bank determines the ratioed input standards that can be supported in that bank It is also used to power the differ ential output drivers The VCCIO of one of the banks is also used to power the JTAG pins Bankl for MachX0256 Bank2 for MachX064O and Bank5 for MachXOlZOO and MachX02280 devices Therefore the threshold of the JTAG pins is determined by the VCCIO of the JTAG bank VCCAUX 33V In addition to the bank VCCIO supplies devices have a VCC core logic power supply and a VCCAUX auxiliary supply that powers the differential and referenced input buffers VCCAUX is required because VCC does not have enough headroom to satisfy the commonmode range requirements of these drivers and input buffers Mixed Voltage Support in a Bank The MachXO syle buffer is connected to three parallel ratioed input buffers These three parallel buffers are con nected to VCCIO VCCAUX and to VCC giving support for thresholds that track with VCCIO as well as fixed thresholds for 33V VCCAUX and 12V VCC inputsThis allows the input threshold for ratioed buffers to be assigned on a pin bypin basis rather than being tracked with VCCIO This option is available for all 12V 25V and 33V ratioed inputs and is independent of the bank VCCIO voltage For example if the bank VCCIO is 18V it is possible to have 12V and 33V ratioed input buffers with fixed thresholds as well as 25V ratioed inputs with tracking thresholds Prior to device configuration the ratioed input thresholds always track the bank VCCIOThis option only takes effect after configuration Output standards within a bank are always set by VCCIO Table 82 shows the syle standards that the user can mix in the same bank Table 82 Mixed Voltage Support Lattice Semiconductor MachXO syle Usage Guide syle Standards Supported in Each Bank Table 83 0 Standards Supported by Various Banks in the MachX 0640 and MachX 0256 Standards are 2 MachX0256 only has 2 banks Banks 0 and Bank 1 Table 84 0 Standards Supported by 0 Pins on Each Side of the MachXO 1200 and MachX 02280 Buffer Type Standards Inputs PLL input PLL input PLL input PLL input are 2 These are supported on half the of the bank LVCMOS Buffer Configurations All LVCMOS buffer have programmable pull programmable drive and programmable slew configurations that can be set in the software Programmable PULLUPPULLDOWNBUSKEEPER When configured as LVCMOS or LVTTL each syle buffer has a weak pullup a weak pulldown resistor and a weak buskeeper bus hold latch available Each lO can independently be configured to have one of these features or none of them Lattice Semiconductor MachXO syle Usage Guide Programmable Drive All LVCMOS and LVTTL singleended drivers have programmable drive strength This option can be set for each lO independently The table below lists the programmable drive strengths available for each lO standard The actual value will vary with the lO voltageThe user must consider the maximum allowable current per bank and the package thermal limit current when selecting the drive strength Table 85 Programmable Drive Strength Programmable Slew Rate Each LVCMOS or LVTTL output buffer pin also has a programmable output slew rate control that can be configured for either low noise or highspeed performance Each lO pin also has an individual slew rate control This allows a designer to specify slew rate control on a pinbypin basis This slew rate control affects both the rising edge and the falling edges OpenDrain Control Each LVCMOS and LVTTL output buffer can be configured to function as an opendrain output The user can implement an opendrain output by turning on the OPENDFlAlN attribute in the software Programmable PCICLAMP Each syle buffer on the top bank of the MachXOlZOO and MachX02280 devices can be configured to support PCI33 The buffers also have a PCI clamp diode that will be turned on when the syle buffer is configured as PCI33 The PCI clamp is mainly used when implementing at 33V PCI interfaceThe PCI Specification revision 22 requires the use of clamping diodes for 33V operation For more information on the PCI interface please refer to the PCI specification revision 22 The PCI clamp can also be optionally turned on for LVCMOS and LVTTL syle buffers on the top bank of the MachXOlZOO and MachX02280 devices In this case the PCI clamp is used to implement at 5V input interface 5V Input Interface Using the PCI Clamp Diode All the lOs on the top side of the MachXOlZOO and MachX02280 devices Banks 0 and 1 have a clamp diode that is used to clamp the voltage at the input to VCCIOThis clamp diode can be used along with an external resistor to make an input 5V tolerant Lattice Semiconductor MachXO syle Usage Guide Figure 84 5V Input Interface Example PCI Clamp Diode Exte mal Resistor 5V Input The value of this external resistor will depend on the PCI clamp diode characteristics The voltage vs current data across this diode can be found in the device IBIS model In order to interface to 5V input it is recommended that the VCCIO is set between 25V to 33V Below is an example of how to calculate the value of this external resistor when VCCIO is 275V Maximum voltage at input pin VINMAX 375V see device data sheet for more details Bank VCCIO 275V Maximum voltage drop across clamp diode VD VINMAX VCCIO 375 275 1V The current across the clamp diode at VD can be found in the power clamp data of the IBIS file Below is the power clamp portion of the IBIS file for a LVCMOS33 input model with PCI Clamp turned on When VD is IV the clamp diode current is ID 3918mA Table 86 Power Clamp Data from IBIS Model Assume the maximum output voltage of the driving device is VEXT 525V The value of the external resistor can then be calculated as follows REXT VEXT VINMAXVID 525V 375V3918mA 383 ohm If the VCCIO of the bank is increased it will also increase the value of the external resistor required Keep in mind that changing the BathCCIO will change the value of the input threshold voltage Lattice Semiconductor MachXO syle Usage Guide Software syle Attributes syle attributes can be specified in the HDL using the Preference Editor GUI or in the ASCII Preference file perf directly Appendices A B and C list examples of how these can be assigned using each of the methods mentioned above This section describes in detail each of these attributes 0TYPE This is used to set the syle standard for an lO The VCCIO required to set these lO standards are embedded in the attribute names itself There is no separate attribute to set the VCCIO requirements Table 6 and 7 list the avail able IO types Table 87 IO TYPE Attribute Values for MachX 0640 and MachX0256 Devices are tary LVCMOS driver with external resistor pack Table 88 IO TYPE Attribute Values for MachXO 1200 and MachX02280 Devices are mentary LVCMOS driver with external resistor pack 2 Available on 50 of the Os on the right and left side banks 3 Available on the top side bank Lattice Semiconductor MachXO syle Usage Guide OPENDRAIN LVCMOS and LVTTL lO standards can be set to opendrain configuration by using the OPENDFtAlN attribute Values ON OFF Default OFF DRIVE The Drive Strength attribute is available for LVTTL and LVCMOS output standards These can be set or each lO pin individually The programmable drive available on a pad will depend on the VCCIO Table 89 shows the drive strength available for different lO standards and the defaults for each of them Table 89 Programmable Drive Strength Values at Various VCCIO Voltages PULLMODE The PULLMODE attribute is available for all the LVTLL and LVCMOS inputs and outputs This attribute can be enabled for each lO independently Values UP DOWN NONE KEEPER Default UP Table 810 PULLMODE Values PCICLAMP PCI33 inputs and outputs are available on the top bank of the MachXOtZOO and MachX02280 devices When an lO is configured as a PC33 standard the PCICLAMP is enabled for that buffer The PCICLAMP is also available for all LVCMOSSS and LVTTL inputs This is used to implement a 5V input interface Values ON OFF Default ON for PCI33 input and output OFF for LVCMOSSS and LVTTL inputs Lattice Semiconductor MachXO syle Usage Guide SLEWRATE The SLEWFlATE attribute is available for all LVTTL and LVCMOS output drivers Each lO pin has an individual slew rate control This allows designers to specify the slew rate control on pinbypin basis Values FAST SLOW Default FAST LOC This attribute can be used to make pin assignments to the lO ports in the designThis attributes is only used when the pin assignments are made in HDL source Users can also assign pins directly using the GUI in the Preference Editor of the softwareThe appendices of this document explain this in greater detail Design Considerations and Usage This section discusses some rules and considerations for designing with the MachXO syle buffer Banking Rules If the VCCIO for any bank is set to 33V it is recommended that it be connected to the same power supply as VCCAUX thus minimizing leakage lf VCCIO for any bank is set to 12V it is recommended that it be connected to the same power supply as VCC thus minimizing leakage PCI lO standards with PCI clamps are only available on the top bank Banks 0 and 1 on the MachXOlZOO and MachX02280 devices PCI lO standards with PCI clamps are not available on the MachX064O and MachX0256 devices Only 50 of the lOs on the left and right banks of the MachXOlZOO and MachX02280 devices support aTrue LVDS driver True LVDS receivers are available on all banks for the MachXOlZOO and MachX02280 devices All banks support emulated differential outputs using an external resistor pack and complementary LVCMOS driver Zero Hold Time The user can achieve a zero hold time for his or her inputs by specifying a zero hold time preference in the soft ware The software will add additional delays to the input path in order to achieve this zero hold time Fast Output Path The MachXO devices have a dedicated fast output lO connection from the adjacent PLCs to the lO buffers within the PIO This connection provides faster output delays for faster clocktooutput propagation delays and pintopin propagation delays The software will automatically use this fast output path to achieve faster too and tPD require ments You can fulfill the too and tPD requirement by assigning these preferences in the Preference Editor in the software Dedicated Pins Global Set Rest GSR The GSR in the MachXO devices is an asynchronous Global Set ResetThis signal is can be programmed to come from either the PFU logic or from the dedicated GSR input pad When the software does not see any logic associ ated with the GSR then it will automatically use the dedicated GSR input pathThis provides faster timing When the reset used is a logic reset the polarity is programmable When the dedicated GSR input from the GSR pad is used the polarity has to be active low Lattice Semiconductor MachXO syle Usage Guide Tristate All T SALLPAD All MachXO devices have a dedicated TSALLPAD pin that is used to enable or disable the tristate control to all the output buffers By default the pin will function as an lO unless programmed to be a TSALLPAD This signal also has programmable global polarity control By default the polarity is active high This global tristate control signal can also be generated using user logic When the TSALLPAD is enabled the software will implement the tristate control using the TSALL software primi tiveThe polarity control of the TSALLPAD will control the polarity ofTSALL When TSALLPAD is not used in the design but is required for test purposes the TSALL primitive can be instanti ated in the HDL and the TSALLPAD is connected to the input of this primitive Differential IIO Implementation MachXO devices support a variety of differential standards as detailed in the following sections LVDS MachXO1200 and MachX02280 True LVDS LVDSZS drivers are available on 50 of the lOs on the left and right sides of the MachX01200 and MachX02280 devices LVDS input support is available on all sides of the MachX01200 and MachX02280 devices LVDSE The singleended syle buffer pairs in all the MachXO devices support LVDS output drivers using complementary LVCMOS drivers with external resistors LVDSZSE on all four sides of the device The MachX01200 and MachX02280 devices also support LVDSE inputs on all four sides of the device Please refer to the MachXO Family Data Sheet for a detailed explanation of these LVDS implementations BLVDS All singleended syle buffer pairs in all the MachXO devices support BusLVDS output driver using complemen tary LVCMOS drivers with external resistors on all the four sides of the device The MachX01200 and MachX02280 devices also support BLVDS inputs on all four sides of the device Please refer to the MachXO Family Data Sheet for a detailed explanation of BLVDS implementation RSDS All singleended syle buffer pairs in all the MachXO devices support FtSDS output driver using complementary LVCMOS drivers with external resistors The MachX01200 and MachX02280 devices also support FtSDS inputs on all four sides of the device Please refer to the MachXO Family Data Sheet for a detailed explanation of FtSDS implementation LVPECL All singleended syle buffers pairs in all the MachXO devices support LVPECL output driver using complementary LVCMOS drivers with external resistors The MachX01200 and MachX02280 devices also support LVPECL inputs on all four sides of the device Please refer to the MachXO Family Data Sheet for a detailed explanation of LVPECL implementation Technical Support Assistance Hotline 1800LATTICE North America 15032688001 Outside North America email techsupport latticesemi com Internet wwwlatticesemicom Lattice Semiconductor MachXO syle Usage Guide Revision History Date Version Change Summary Previous Lattice releases July 2007 014 Correction in VCCIO 12V15V18V25V33V text section VCCIO of Bank2 is used to power the JTAG pin for MachX0640 ratherthan Banks Lattice Semiconductor MachXO syle Usage Guide Appendix A HDL Attributes for Synplify and Precision RTL Synthesis Using these HDL attributes you can assign the syle attributes directly in your source You will need to use the attribute definition and syntax for the synthesis vendor you are planning to you to use Below are a list of all the syle attributes syntax and examples for Precision FtTL Synthesis and Synplify This section only lists the syle buffer attributes for these devices You can refer to the Precision FtTL Synthesis and Synplify user manuals fora complete list of synthesis attributesYou can get to these manuals through the ispLEVEFt software Help VHDL SynplifylPrecision RTL Synthesis This section lists syntax and examples for all the syle attributes in VHDL when using Precision FtTL Synthesis and Synplify synthesis tools Syntax Table 81 1 VHDL Attribute Syntax for Precision FlTL Synthesis and Synplify Attribute Syntax IO TYPE attribute IOTYPE string attribute IOTYPE of Pinname signal is IO TYPE Value attribute OPENDRAIN string OPENDRA39N attribute OPENDRAIN of Pinname signal is OpenDrain Value DRIVE attribute DRIVE string attribute DRIVE of Pinname signal is Drive Valuequot attribute PULLMODE string PULLMODE attribute PULLMODE of Pinname signal is Pumode Value attribute PCICLAMP string PC39CLAMP attribute PCICLAMP of Pinname signal is PCClamp Value attribute PULLMODE string SLEWRATE attribute PULLMODE of Pinname signal is Slewrate Value LOO attribute LOC string attribute LOC of Pinname signal is pinJocationS Examples 07TYPE Attribute Declaration ATTFtIBUTE IOTYPE string IO TYPE assignment for 0 Pin ATTFtIBUTE IOTYPE OF portA SIGNAL IS PCI33 ATTFtIBUTE IOTYPE OF porth SIGNAL IS LVCMOSSS ATTFtIBUTE IOTYPE OF portC SIGNAL IS LVDSZS OPENDRAIN Attribute Declaration ATTFtIBUTE OPENDFtAIN string OPENDFIAIN assignment for 0 Pin ATTFtIBUTE OPENDFtAIN OF porth SIGNAL IS ON Lattice Semiconductor MachXO syle Usage Guide DRIVE Attribute Declaration ATTFIIBUTE DRIVE string DRIVE assignment for IIO Pin ATTFIIBUTE DRIVE OF porth SIGNAL IS 16 PULLMODE Attribute Declaration ATTFIIBUTE PULLMODE string PULLMODE assignment for 0 Pin ATTFIIBUTE PULLMODE OF portA SIGNAL IS DOWN ATTFIIBUTE PULLMODE OF porth SIGNAL IS UP PCICLAMP Attribute Declaration ATTFIIBUTE PCICLAMP string PCICLAMP assignment for 0 Pin ATTFIIBUTE PCICLAMP OF portA SIGNAL IS ON SLEWRATE Attribute Declaration ATTFIIBUTE SLEWFIATE string SLEWFIATE assignment for 0 Pin ATTFIIBUTE SLEWFIATE OF porth SIGNAL IS FAST LOC Attribute Declaration ATTFIIBUTE LOC string LOC assignment for IIO Pin ATTFIIBUTE LOC OF inputivector SIGNAL IS E3BSCS Lattice Semiconductor MachXO syle Usage Guide Verilog Synpilfy This section lists syntax and examples for all the syle attributes in Verilog using the Syhplity synthesis tool Syntax Table 8 12 Verilog Synplify Attribute Syntax Examples IIIOTYPE PULLMODE SLEWRATE and DRIVE assignment output portB synthesis lOTYPE LVCM0833 PULLMODE quotUPquot SLEWFtATE quotFASTquot DRIVE 14 output portC syhthesis IOTYPE LVD825 IIOPENDRAIN output portA syhthesis OPENDFtAlN ON IIPCICLAMP output portA syhthesis IOTYPE PC33 PCICLAMP quotPCICLAMP IIIO pin location ihput 30 DATAO synthesis loc E3Bt F3 llRegister pin location reg dataihch1butregS synthesis loc Ft4OC47 lNectorecl internal bus reg 30 dataiihichtireg syhthesis loc quotFt4OC47R4OC46R4OC45R4OC44 Lattice Semiconductor MachXO sysIO Usage Guide Verilog Precision RTL Synthesis This section lists syntax and examples for all the syle attributes in Verilog using the Precision FtTL Synthesis syn thesis tool Syntax Table 813 Verilog Precision FITL Synthesis Attribute Syntax prag ma prag ma prag ma prag ma prag ma prag ma prag ma Example llIOTYPE pragma attribute portA IOTYPE PCI33 pragma attribute portB IOTYPE LVCMOSSS pragma attribute portC IOTYPE SSTL257 ll Openclrain pragma attribute portB OPENDFtAlN ON pragma attribute portD OPENDFtAlN OFF ll Drive pragma attribute portB DRIVE 20 pragma attribute portD DRIVE 8 ll Pullmocle pragma attribute portB PULLMODE UP ll PCICIamp pragma attribute portB PCICLAMP ON ll Slewrate pragma attribute portB SLEWFtATE FAST pragma attribute portD SLEWFtATE SLOW llLOC pragma attribute portB loc E3 Lattice Semiconductor MachXO syle Usage Guide Appendix B syle Attributes Using the Preference Editor User Interface You can also assign the syle buffer attributes using the Premap Preference Editor GUI available in the ispLEVEFi tools The Pin Attribute sheet list all the ports in your design and all the available syle attributes as preferences When you click on each of these cells you get a list of all the valid lO preferences for that port Each column takes precedence over the next Therefore when you choose a particular IOTYPE the DRIVE PULLMODE and SLE WFiATE columns will only list the valid combinations for that IOTYPE The user can lock the pin locations using the pin location column of the Pin Attribute sheet Flightclick on a cell to list all the available pin locations The Pref erence Editor will also do a DFiC check to search for any incorrect pin assignments You can enter the DIN DOUT preferences using the Cell Attributes sheet of the Preference Editor All the prefer ences assigned using the Preference Editor are written into the preference file prf h the Pin 39L l ml the Cell 39L l 39 of the Preference Editor For further infor mation on how to use the Preference Editor please refer to the ispLEVEFi Help documentationYou can get to this in the Help menu option of the software Figure 85 Pin Attributes Tab w l Lattice Semiconductor MachXO syle Usage Guide Appendix C syle Attributes Using Preference File ASCII File You can also enter the syle Attributes directly in the preference prf file as syle buffer preferencesThe PRF file is an ASCII file containing two separate sections a schematic section for those preferences created by the Mapper or Translator and a user section for preferences entered by the user You can write user preferences directly into this file The synthesis attributes appear between schematic start and schematic end of the file You can enter the syle buffer preferences after the schematic end line using the preference file syntax Below are a list of syle buffer preference syntax and examples IOBUF This preference is used to assign the attribute IOTYPE OPENDRAIN DRIVE PULLMODE PCICLAMP and SLEWRATE Syntax IOBUF ALLPORTS PORT ltport7namegt GROUP ltgroup7namegt keywordltvaluegt where ltport7namegt These are not the actual toplevel port names but should be the signal name attached to the port PlOs in the physical design ncd file are named using this convention Any multiple listings or wildcarding should be done using GROUPs Keyword IOTYPE OPENDRAIN DRIVE PULLMODE PCICLAMP SLEWRATE Example IOBUF PORT port1 IOTYPELVTTL33 OPENDRAINON DRIVE8 PULLMODEUP PCICLAMP OFF SLEWRATEFAST DEFINE GROUP bankl in outO31 IOBUF GROUP bankl OiTYPELVCM0833 LOCATE When this preference is applied to a specified component it places the component at a specified site and locks the component to the site If applied to a specified macro instance it places the macro s reference component at a specified site places all of the macro s preplaced components that is all components that were placed in the macro s library file in sites relative to the reference component and locks all of these placed components at their sitesThis can also be applied to a specified PG ROUP Syntax LOCATE COMP ltcomp7namegt MACRO ltmacronamegt SITE ltsitenamegt LOCATE PG ROUP ltpgroup7namegt SITE ltsite7namegt REGION ltregion7namegt LOCATE PGROUP ltpgroup7namegt RANGE ltsite71gt ltsite2gt ltcountgt ltdirectiongt RANGE ltchip7sidegt ltdirectiongt LOCATE BUS lt businamegt ROWCOL ltnumbergt ltbus7namegt string ltnumbergt integer Note If the compiname macroiname or siteiname begins with anything other than an alpha character for exam ple 11C7 you must enclose the name in quotes Wildcard expressions are allowed in ltcompnamegt Lattice Semiconductor MachXO syle Usage Guide Example This command places the port ClkO on the site A4 LOCATE COMP CIkO SITE A4 This command places the component PFU1 on the site named R1C7 LOCATE COMP PFU1 SITE R1C7 This command places bus1 on ROW 3 and bus2 on COL4 LOCATE BUS bus1 ROW 3 LOCATE BUS bus2 COL 4 Memory Usage Guide for 39 Semiconductor 39 u u Corporation MaChxo DeVICeS September 2007 Technical Note TN1092 Introduction This technical note discusses memory usage for the Lattice MachXO device family It is intended to be used by design engineers as a guide in integrating the EBR and PFU based memories for these device families in ispLEVER The architecture of these devices provides resources for memory intensive applications The sysMEMTM Embed ded Block RAM EBR complements its distributed PFUbased memory SinglePort RAM DualPort RAM Pseudo DualPort RAM FIFO and ROM memories can be constructed using the EBR LUTs and PFU can implement Dis tributed SinglePort RAM DualPort RAM and ROM The capabilities of the EBR Block RAM and PFU RAM are referred to as primitives and are described later in this document Designers can utilize the memory primitives in two ways Via lPexpressT39V39 The lPeXpress GUI allows users to specify the memory type and size that is required lPeX press takes this specification and constructs a netlist to implement the desired memory by using one or more of the memory primitives Via the PMI Parameterizable Module Inferencing PMl allows experienced users to skip the graphical inter face and utilize the configurable memory modules on the fly from the ispLEVER Project Navigator The parame ters and the control signals needed either in Verilog or VHDL can be set The toplevel design will have the parameters defined and signals declared so the interface can automatically generate the black box during syn thesis The remainder of this document discusses these approaches utilizing lPeXpress PMl inference memory modules and memory primitives Memories in MachXO Devices Only the MachXOiZOO and MachX02280 devices contain the sysMEM EBR blocks along with an array of logic blocks called PFUs or PFFs surrounded by Programmable lO Cells Ple This is shown in Figure 91 Figure 91 Logical View of MachXO1200 and MachX02280 Devices sysCLOCK PLL 7 PlOs Arranged Into S l5y53903m DDDDDDDDDD DDDDDDDDDD DDDDDDDDDD IIIII Programnable Function Units PFFs Without D RAM mme S Programmable Functional Unll PFUs With RAM sysMEM Embedded Block RAM EBR 2007 Lattice Semiconductor Corp All Lattice trademarks registered trademarks patents and disclaimers are as listed at wwwlatticesemi comlegal All other brand or product names are trademarks or registered trademarks of their r b 39d T r r quotIquot it Hung m on wwwlatticesemicom 91 tn1092014 Lattice Semiconductor Memory Usage Guide for MachXO Devices The PFU contains the building blocks for logic and Distributed RAM and ROM The PFF provides the logic building blocks without the distributed RAM This document describes the memory usage and implementation for both Embedded Memory Blocks EBRs and Distributed RAM of the PFU Refer to the device data sheet for details on the hardware implementation of the EBR and Distributed RAM The logic blocks are arranged in a twodimensional grid with rows and columns as shown in the figures below The physical location of the EBR and Distributed RAM follows the row and column designation Since the Distributed RAM is part of the PFU resource it follows the PFUPFF row and column designation The EBR occupies two col umns per block to account for the wider port interface Utilizing lPexpress Designers can utilize lPexpress to easily specify a variety of memories in their designs These modules will be con structed using one or more memory primitives along with general purpose routing and LUTs as required The avail able primitives are 0 Single Port RAM RAMiDQ EBRbased 0 Dual PORT RAM RAMiDPiTRUE EBRbased Pseudo Dual Port RAM RAMiDP EBRbased Read Only Memory ROM EBRBased First In First Out Memory Dual Clock FIFODC EBRbased Distributed Single Port RAM Distributed7SPRAM PFUbased Distributed Dual Port RAM DistributediDPRAM PFUbased Distributed ROM DistributediROM PFUPFFbased RAM Based Shift Register RAMiBased7Shift7Register PFUbased Distributed Shift Register RAMiBased7Shift7Register PFU based see lPexpress Help for details lPexpress Flow For generating any of these memories create or open a project for the MachXO devices From the Project Navigator select Tools gt lPexpress Alternatively users can also click on the 3 button in the toolbar when the MachXO devices are targeted in the project This opens the lPexpress window as shown in Figure 92 Lattice Semiconductor Figure 92 IPexpress Main Window Memory Usage Guide for MachXO Devices n 1 File mi HElD a a g hi i 1 Name Veisian A We Tu generate the muddle Dr H enterme infurmatiun in the Ji39jr ef milffmeg Enabled fields such as Pruieet Pain File Name etc and Blink J Dgpma acgu e 28 en the Custumize buttun A dialug Will upen tn anew J Mam M ustumizatiun er the selected muddle Dr H a A mined E Di inhaled DPRAM 2 n a named RUM 2 n Mama ripe Veixian a named 5 AM 2B R axe snnjegiser 2n Madnle Name Q n 2 n a FlFELDC 2 n E Hwy 2 n Piaiecl Palh J a RAMJPJRUE 2 n a mm 2 n 3 Rm 2 n Fie Name J w Design my Device Family Pail Name Cuxlamize ISPLEIIEI lnslalled lPsMadules i Lil H E Selling 3 Am The left pane of this window includes the Module Tree The EBRbased Memory Modules are under the EBFLComponents and the PFUbased Distributed Memon Modules are under Storage7Components as shown in Figure 92 As an example let us consider generating an EBRbased Pseudo Dual Port RAM of size 512x16 Select RAMiDP underthe EBFLComponents The right pane changes as shown in Figure 93 Lattice Semiconductor Memory Usage Guide for MachXO Devices Figure 93 Example Generating Pseudo Dual Port RAM RAMiDP Using IPexpress D 5 File mi Help a e 9 E j 1 Name Veisian 2 Tu generate the muddle ur lP enterme lnfurmatlun in the lf ef li 2 f e Enabled fields such as Pruject Path File Name etc and click quot quotE De 28 en the Custumize buttun A dialug Will upen tn anew DsP Maddie W M custumizatiun er the selected muddle Dr H a A Distributed Di immemwn 2 n Disliinuemun 2n Maciaiwe Maddie Veisian 2U 13 named RAM 2 mmaaseesiil egiser 2 n a A EBFLCampanenls MaduleName RAMP 9E FlFEI 2n FlFELDC 2n Piajecl Palh a isplaals jexampleszgamachxavhdlcnlhui J RAMJURUE 2 n a mm 2 n a W 2 n me Name Melanie J w Design my SchematicNHDL v DeviceFamily MachXEl Paii Name LCMXmZnnE aiinncEs Cuslamize lspggver lnslalled lPsMadules l g y y RAMP RAMP In this right pane options like the Device Family Macro Type Category and ModuleiName are device and selected module dependentThese cannot be changed in IPexpress Users can change the directory where the generated module files will be placed by clicking the Browse button in the Project Path The Module Name text box allows users to specify an entity name for the module they are about to generate Users must provide this entity name Design entry Verilog or VHDL by default is the same as the project type If the project is a VHDL project the selected design entiy option will be Schematic VHDL and Schematic VerilogHDL if the project type is Verilog HDL The Device pulldown menu allows users to select different devices within the same family MachXO in this exam ple Then clickthe Customize button This opens anotherwindow where users can customize the RAM Figure 94 Lattice Semiconductor Memory Usage Guide for MachXO Devices Figure 94 Example Generating Pseudo Dual Port RAM RAMiDP Module Customization A lzl Eanilguialiah EeneialeLDg l RAMiDP Eanilguialian WW 5 ans I Addiess Depth 5i2 Data Width i5 Addiess De Ih 5i2 Data idlh i RdElackEn UIiSUI V D W a I7 Enable Dulpul REEISIEI iElack 17 Enable ESR iiiiiiiii WiElackEn WE ReseIMade r Asym r Sync Mammy rig Memainilemeal r Binaiy r Hex r AddiessedHex a Uideii lg Style Big Man IMSB LSBI 1 r impart LPC In lspLeyei pyuieci Geneiaie Cluse Help The left side of this window shows the block diagram of the module The right side includes the Configuration tab where users can choose options to customize the RAMiDP such as eg specify the address port sizes and data widths Users can specify the address depth and data width for the Read Port and the Write Port in the text boxes pro vided In this example we are generating a Pseudo Dual Port RAM of size 512 x 16 Users can also create the RAMs of different portwidths in case of Pseudo Dual Port and True Dual Port RAMs The Input Data and the Address Control is always registered as the hardware only supports the clocked write operation for the EBR based RAMs The check box Enable Output Registers inserts the output registers in the Read Data Port as the output registers are optional forthe EBRbased RAMs Users have the option to setthe Reset Mode as Asynchronous Reset or Synchronous Reset Enable GSR can be checked to be enable the Global Set Reset Users can also preinitialize their memory with the contents specified in the Memory File It is optional to provide this file in the RAM howeverfor ROM the Memon File is requiredThese files can be of Binaiy Hex orAddresses Hex format The details of these formats are discussed in the Initialization File section of this document At this point users can click the Generate button to generate the module they have customized AVHDL orVerilog netlist is then generated and placed in the specified location Users can incorporate this netlist in their designs Another important button is the Load Parameters button IPexpress stores the parameters the user has specified in an ltmodule7namegtlpc fileThis file is generated along with the module Users can click on the Load Parameter button to load the parameters of a previously generated module to revisit or make changes to them Once the module is generated user can either instantiate the pc orthe VerilogHDL VHDL file in toplevel mod ule of their design The various memory modules both EBR and Distributed are discussed in detail in this document Lattice Semiconductor Memory Usage Guide for MachXO Devices Memory Modules Single Port RAM RAMiDQ EBR BasedThe EBFl blocks in the MachXO devices can be configured as Single Port RAM or RAMiDQ lPeXpress allows users to generate the VerilogHDL or VHDL along EDIF netlist for the memory size as per design requirements lPeXpress generates the memory module as shown in Figure 95 Figure 95 Single Port Memory Module Generated by IPexpress Clock 4 ClockEn 4 Reset 4 RANLDQ 4gtQ EBRbased Single Port WE Memory Address 4 Data 4 Since the device has a number of EBFl blocks the generated module makes use of these EBFl blocks or primi tives and cascades them to create the memory sizes specified by the user in the lPeXpress GUI For memory sizes smaller than an EBFl block the module will be created in one EBFl block For memory sizes larger than one EBFl block multiple EBFl blocks can be cascaded in depth or width as required to create these sizes In Single Port RAM mode the input data and address for the ports are registered at the input of the memory array The output data of the memory is optionally registered at the output The various ports and their definitions for the Single Port Memory are listed in Table 91 The table lists the corre sponding ports for the module generated by lPeXpress and for the EBFl RAMiDQ primitive Table 91 EBBbased Single Port Memory Port Definitions Generated Module EBR Block Primitive Description Active State Reset or RST resets only the input and output registers of the RAM It does not reset the contents of the memory Chip Select CS is a useful port in the EBFl primitive when multiple cascaded EBFl blocks are required by the memory The CS signal forms the M88 for the address when multiple EBFl blocks are cascaded CS is a 3bit bus so it can cascade eight memories easily If the memory size specified by the user requires more than eight EBFl Lattice Semiconductor Memory Usage Guide for MachXO Devices blocks the ispLEVEFl software automatically generates the additional address decoding logic which is imple mented in the PFU external to the EBFl blocks Each EBFl block consists of 9216 bits of RAM The values for X address and y data for each EBFl block for the devices are listed in Table 92 Table 92 Single Port Memory Sizes for 9K Memories in MachXO Memory Size Input Data Output Data MSBLSB Table 93 shows the various attributes available for the Single Port Memory RAMiDQ Some of these attributes are user selectable through the lPeXpress GUI For detailed attribute definitions refer to Appendix A Table 93 Single Port RAM Attributes for MachXO Default through Attribute Description Values Value lPeXpress 100b111 or Set Reset hex string The Single Port RAM RAMiDQ can be configured as NORMAL READ BEFORE WRITE or WRITE THROUGH modes Each of these modes affects what data comes out of the port Q of the memory during the write operation followed by the read operation at the same memory location Additionally users can select to enable the output registers for RAMiDQ Figures 611 show the internal timing waveforms for the Single Port RAM RAMiDQ with these options Lattice Semiconductor Memory Usage Guide for MachXO Devices Figure 96 Single Port RAM Timing Waveform NORMAL Mode without Output Registers L swazak H CIockEn SUWREVILEBR kazmiak WE J 7 suAuuRjaR WHERE Address 7 Data 7 Q Invalld Dala X Dala0 X Dala1 i i i i i Figure 97 Single Port RAM Timing Waveform NORMAL Mode with Output Registers Reset Clock CIockEn WE Address Dala Q Invalld Dala Lattice Semiconductor Memory Usage Guide for MachXO Devices Figure 98 Single Port RAM Timing Waveform READ BEFORE WHITE Mode without Output Registers 0quot sucwRi I i mm CIockEn 39 swamzaa HWRENJBR WE i i Address Dala Q Invalld Dala OldiDaIaio K NewiDaIaio X OldiDaIaJ X NewiDaIaJ X i i OOjBR i Figure 99 Single Port RAM Timing Waveform READ BEFORE WHITE Mode with Output Registers 1 mwki i I i mazak CIockEn t isuwRErAjak iwmm WE i i Address 7 Data 7 Q Invalld Dala OldiDaIaio NewiDaIaio OldiDaIaJ New Dala1 i i i i i W i i Lattice Semiconductor Memory Usage Guide for MachXO Devices Figure 910 Single Port RAM Timing Waveform WHITE THROUGH Mode without Output Registers Clock ClockEn WE Address Data Q Invalid Data Data Figure 91 1 Single Port RAM Timing Waveform WHITE THROUGH Mode with Output Registers PM U U I i Hcazak ClockEn Add0 4 Address 7 Q Invalid Data lt Dala0 K Dalaj X Data l l l l l True Dual Port RAM RAMDPTRUE EBR Based The EBFt blocks in MachXO devices can be configured as TrueDual Port RAM or RAMiDPiTFtUE IPeXpress allows users to generate the VerilogHDL VHDL or EDIF netlists for various memory sizes depending on design requirements IPeXpress generates the memory module as shown in Figure 912 Lattice Semiconductor Memory Usage Guide for MachXO Devices Figure 9 12 True Dual Port Memory Module generated by lPeXpress ClockA 4 lt7 ClockB CIockEnA 4 lt7 ClockEnB ResetA 4 lt7 ResetB RAMiDPiTRUE WrA EBRbased True Dual WrB Port Memory AddressA 4 lt7 AddressB DatalnA 4 lt7 DatalnB QA lt7 4 QB The generated module makes use of these EBFl blocks or primitives For memory sizes smaller than an EBFl block the module will be created in one EBFl block When the specified memory is larger than one EBFl block multiple EBFl blocks can be cascaded in depth or width as required to create these sizes In True Dual Port RAM mode the input data and address for the ports are registered at the input of the memory array The output data of the memory is optionally registered at the output The various ports and their definitions for Single Port Memory are in Table 94 The table lists the corresponding ports for the module generated by lPeXpress and for the EBFl RAMiDPiTFlUE primitive Table 94 EBFI based True Dual Port Memory Port Definitions Generated Module EBR Block Primitive Description Active State Active High Reset or RST resets only the input and output registers of the RAM It does not reset the contents of the memory Chip Select CS is a useful port in the EBFl primitive when multiple cascaded EBFl blocks are required by the memory The CS signal forms the M88 for the address when multiple EBFl blocks are cascaded Since CS is a 3 bit bus it can cascade eight memories easily However if the memory size specified by the user requires more than eight EBFl blocks the ispLEVEFl software automatically generates the additional address decoding logic which is implemented in the PFU external to the EBFl blocks Each EBFl block consists of 9216 bits of RAM The values for X s for address and y s data for each EBFl block for the devices are listed in Table 95 Lattice Semiconductor Memory Usage Guide for MachXO Devices Table 95 MachXO Dual Port Memory Sizes for 9K Memory Memory Size A A MSBLSB MSBLSB X Table 96 shows the various attributes available for the True Dual Port Memory RAMiDPiTRUE Some of these attributes are userselectable through the lPeXpress GUI For detailed attribute definitions refer to the Appendix A Table 96 MachXO Dual Port RAM Attributes Attribute Description Values lPeXpress OUTREG OUTREG Ob101 Ob110 Ob111 000 000 100101110111 NORMAL NORMAL The True Dual Port RAM RAMiDPiTRUE can be configured as NORMAL READ BEFORE WRITE or WRITE THROUGH modes Each of these modes affects what data comes out of port Q of the memory during the write operation followed by the read operation at the same memory location Detailed discussions of the WRITE modes and the constraints of the True Dual Port can be found in Appendix A Additionally users can select to enable the output registers for RAMiDPiTRUE Figures 1318 show the internal timing waveforms for the True Dual Port RAM RAMiDPiTRUE with these options Lattice Semiconductor Memory Usage Guide for MachXO Devices Figure 913 True Dual Port RAM Timing Waveform NORMAL Mode without Output Registers CIockA ClockEnA AddressA DaIaA QA invahd Data DaiaAo DaiaJM DaiaA2 CIockB ClockEnB AddressB DaIaB QB invahd Data Daiajo Daiaji DaiajiZ Lattice Semiconductor Memory Usage Guide for MachXO Devices Figure 914 True Dual Port RAM Timing Waveform NORMAL Mode with Output Register Reset CIockA CIockEnA swam AddressA DalaA DaiaAo Dai aw QA invahd Data DaiaAo DaiaJM CIockB CIockEnB swam AddressB DalaB Daiajo Daiaji QB invahd Data Datajo Dataji Lattice Semiconductor Memory Usage Guide for MachXO Devices Figure 915 True Dual Port RAM Timing Waveform READ BEFORE WHITE Mode without Output Registers ClockA ClockEnA AddressA DaIaA ClockB ClockEnB AddressB DaIaB New Data7Ao invahd Data New Datajo invahd Data suwmuex New Data7A1 o d7Data7Ao N ewDataAo Oi d7Data7A1 New7Data7A1 isuWRErAjak New Dataji oidjatajo NewDataBo oidjatajt NewDataBi Lattice Semiconductor Memory Usage Guide for MachXO Devices Figure 916 True Dual Port RAM Timing Waveform READ BEFORE WRITE Mode with Output Registers Reset CIockA CIockEnA AddressA New New Da aA DaiaiAO DaiaiAi QA invahd Data OidiDataiAO NewiDaiaiAO OidiDaiaiAi New DaiaJM CIockB CIockEnB AddressB DalaB New New Datajo Daiaji QB invahd Data oidjaiajo NewDa aBo oidjaiaji Lattice Semiconductor Memory Usage Guide for MachXO Devices Figure 917 True Dual Port RAM Timing Waveform WRITE THROUGH Mode without Output Registers ClockA ClockEnA AddressA DataA ClockB ClockEnB AddressB DataB suwmu moon Datajo DataJM Data7A2 Data DamM Invalid Data DamA0 DamM DamA2 Data DamA4 suwmu moon Data o Data i Data z Data s Data A Invalid Data Daia o Dwain Daia z Daia s Daia A Lattice Semiconductor Memory Usage Guide for MachXO Devices Figure 918 True Dual Port RAM Timing Waveform WRITE THROUGH Mode with Output Registers Reset CIockA ClockEnA AddressA Dal 3A DaiaiAO DaiaiAi DaiaiAZ DaiaiAS DaiaiAA QA Invalld Data DataiAO DaiaiAi DataiAZ DataiAs CIockB ClockEnB AddressB DaIaB DaiaiBO DaiaiBi DaiaiBZ DaiaiBS DaiaiBA QB Invalld Data DataiBO DaiaiBi DataiBZ DataiBs Lattice Semiconductor Memory Usage Guide for MachXO Devices Pseudo Dual Port RAM RAMDP EBR Based The EBFl blocks in the MachXO devices can be configured as PseudoDual Port RAM or RAMiDP lPeXpress allows users to generate the VerilogHDL or VHDL along EDIF netlist for the memory size as per design require ments lPeXpress generates the memory module as shown in Figure 919 Figure 919 Pseudo Dual Port Memory Module Generated by lPeXpress WrClock 4 lt7 RdClock WrClockEn 4 lt7 RdClockEn Reset 4 RAMeDP EBRbased WE 39 Pseudo Dual Port Memory WrAddress 4 lt7 RdAddress Data 4 4 Q The generated module makes use of these EBFl blocks or primitives For the memory sizes smaller than an EBFl block the module will be created in one EBFl block If the specified memory is larger than one EBFl block multiple EBFl blocks can be cascaded in depth or width as required to create these sizes In Pseudo Dual Port RAM mode the input data and address for the ports are registered at the input of the memory array The output data of the memory is optionally registered at the output The various ports and their definitions for the Single Port Memory are listed in Table 97 The table lists the corre sponding ports for the module generated by lPeXpress and for the EBFl RAMiDP primitive Table 97 EBFlBased PseudoDual Port Memory Port Definitions Generated Module Block Primitive Description Active State Reset HST resets only the input and output registers of the RAM It does not reset the contents of the memory Chip Select CS is a useful port when multiple cascaded EBFl blocks are required by the memory The CS signal forms the M88 for the address when multiple EBFl blocks are cascaded Since CS is a 3bit bus it can cascade eight memories easily However if the memory size specified by the user requires more than eight EBFl blocks the Lattice Semiconductor Memory Usage Guide for MachXO Devices ispLEVEFt software automatically generates the additional address decoding logic which is implemented in the PFU external to the EBFt blocks Each EBFt block consists of 9216 bits of RAM The values for X s for address and y s data for each EBFt block for the devices are as per Table 98 Table 98 MachXO PseudoDual Port Memory Sizes for 9K Memory PortMemory lnputDataPort lnputDataPort OutputData OutputData PortA PortB Size A B Port B MSBLSB MSBLSB Table 99 shows the various attributes available for the PseudoDual Port Memory RAMiDP Some of these attributes are userselectable through the lPeXpress GUI For detailed attribute definitions refer to Appendix A Table 99 MachXO PseudoDual Port RAM Attributes Attribute Description Values lPeXpress Select Decode forWrite Ob10110b11010b111 Select Decode for Read Ob101 Ob1100b111 Users have the option of enabling the output registers for PseudoDual Port RAM RAMiDP Figures 20 and 21 show the internal timing waveforms for PseudoDual Port RAM RAMiDP with these options Lattice Semiconductor Memory Usage Guide for MachXO Devices Figure 920 PSEUDO DUAL PORT RAM Timing Diagram without Output Registers WrClock WrClockEn RdClock RdClockEn WrAddress RdAddress Data Q invalid Data Figure 921 PSEUDO DUAL PORT RAM Timing Diagram with Output Registers WrCloCk WrCloCkEn RdCloCk RdCloCkEn WrAddress RdAddress Data Q invalid Data Read Only Memory ROM EBR Based The EBFt blocks in the MachXO devices can be configured as Read Only Memory or ROM IPeXpress allows users to generate the VerilogHDL or VHDL along EDIF netlist tor the memory size as per design requirement Users are required to provide the ROM memory content in the form of an initialization file IPeXpress generates the memory module as shown in Figure 922 Lattice Semiconductor Memory Usage Guide for MachXO Devices Figure 922 ROM Read Only Memory Module Generated by lPeXpress OutClock 4 OutClockEn 4 ROM EBRbased Read Only Q Reset 4 Address 4 The generated module makes use of these EBR blocks or primitives For the memory sizes smaller than an EBR block the module will be created in one EBR block If the specified memory is larger than one EBR block multiple EBR blocks can be cascaded in depth or width as required to create these sizes In ROM mode the address for the port is registered at the input of the memory array The output data of the mem ory is optionally registered at the output The various ports and their definitions for the ROM are listed in Table 910 The table lists the corresponding ports for the module generated by lPeXpress and for the ROM primitive Table 910 EBRbased ROM Port Definitions Generated Module EBR Block Primitive Description Active State Reset RST resets only the input and output registers of the RAM It does not reset the contents of the memory Chip Select CS is a useful port when multiple cascaded EBR blocks are required by the memory The CS signal forms the M88 for the address when multiple EBR blocks are cascaded Since CS is a 3bit bus it can cascade eight memories easily However if the memory size specified by the user requires more than eight EBR blocks the ispLEVER software automatically generates the additional address decoding logic which is implemented in the PFU external to the EBR blocks While generating the ROM using lPeXpress the user must provide the initialization file to preihitialize the contents of the ROM These files are the mem files and they can be of Binary Hex or the Addressed Hex formatsThe ihi tialization files are discussed in detail in the Initializing Memory section of this document Users have the option of enabling the output registers for Read 0th Memory ROM Figures 23 and 24 show the internal timing waveforms for the Read 0th Memory ROM with these options Lattice Semiconductor Memory Usage Guide for MachXO Devices Figure 923 ROM Timing Waveform without Output Registers OutClock stoma H incsz OutClockEn Address 0 Wede X new X 3334 X Data x Data l l l l l l Figure 924 ROM Timing Waveform with Output Registers Rest iswLmRH i l imam OuiClockEn Address AchO Addj AchZ AdCLS Ach4 ismuuma imuukjak Q Invalid Data X Dala0 X Daiaj X Data l l l l l First In First Out FIFO FFODC EBR Based The EBFi blocks in MachXO devices can be configured as Dual Clock First In First Out Memories FlFoiDC lPeX press allows users to generate the VerilogHDL or VHDL along EDIF netlist tor the memory size according to design requirements lPeXpress generates the FlFoiDC memory module as shown in Figure 925 Figure 925 FIFO Module Generated by lPeXpress CLK 4b 4b DO WE 4 4 FF FIFO RE EBRbased FirstIn FirstOut AF Memory RST 4b 4b EF DI 4b 4gtAE The generated module makes use of these EBFi blocks or primitives For the memory sizes smaller than an EBFi block the module will be created in one EBFi block It the specified memory is larger than one EBFi block multiple EBFi blocks can be cascaded in depth or width as required to create these sizes Lattice Semiconductor Memory Usage Guide for MachXO Devices A clock is always required as only synchronous write is supported The various ports and their definitions for the FlFoiDC are listed in Table 911 Table 91 1 EBBbased FIFoiDC Memory Port Definitions Generated Module Port Name in Primitive Description Active State Reset HST resets only the input and output registers of the RAM It does not reset the contents of the memory The various supported sizes for the FlFoiDC tor MachXO are listed in Table 912 Table 9 12 MachXO FIFoiDC Data Widths Sizes Table 913 shows the various attributes available for the FlFoiDC Some of these attributes are userselectable through the lPeXpress GUI For detailed attribute definitions refer to Appendix A Lattice Semiconductor Memory Usage Guide for MachXO Devices Table 913 FIFO and FIFoiDC Attributes for MachXO Attribute Description EmptyPOime 1111111111111 F P me 1111111111111 Power 1111111111111 POime 1111111111111 F P me 1111111111111 EmptyPO me 1111111111111 FlFoiDC Flags The FlFoiDC have four flags available Empty Almost Empty Almost Full and Full Almost Empty and Almost Full flags have a programmable range The program ranges for the four FlFoiDC flags are specified in Table 914 Table 914 FIFoiDC Flag Settings The only restriction on the flag setting is that the values must be in a specific order EmptyO Almost Empty next followed by Almost Full and Full respectivelyThe value of Empty is not equal to the value of Almost Empty or Full is equal to Almost Full In this case a warning is generated and the value of Empty or Full is used in place of Almost Empty or Almost Full When coming out of reset the active high flags Empty and Almost Empty are set to high since they are true The user should specify the absolute value of the address at which the Almost Empty and Almost Full flags will go true For example if the Almost Full flag is required to go true at the address location 500 for a FIFO of depth 512 the user should specify a value of 500 in lPeXpress The Empty and Almost Empty flags are always registered to the read clock and the Full and Almost Full flags are always registered to the write clock At reset both the write and read counters are pointing to address zero After reset is deasserted data can be writ ten into the FlFoiDC to the address pointed to by the write counter at the positive edge of the write clock when the write enable is asserted Lattice Semiconductor Memory Usage Guide for MachXO Devices Similarly data can be read from the FlFoiDC from the address pointed to by the read counter at the positive edge of the read clock when read enable is asserted Read Pointer Reset RPReset is used to indicate a retransmit and is more commonly used in packetized com munications In this application the user must keep careful track of when a packet is written into or read from the FlFoiDC The data output of the FlFoiDC can be registered or honregistered through a selection in lPeXpress The output registers are enabled by read enable A reset will clear the contents of the FlFoiDC by resetting the read and write pointers and will put the flags in the initial reset state FlFoiDC Operation If the output registers are not enabled it will take two clock cycles to read the first word outThe register for the flag logic causes this extra clock latency In the architecture of the emulated FlFoiDC the internal read enables for reading the data out is controlled not only by the read enable provided by the user but also the empty flag When the data is written into the FIFO an internal empty flag is registered using write clock that is enabled by write enable WrEh Another clock latency is added due to the clock domain transfer from write clock to read clock using another register which is clocked by read clock that is enabled by read enable Internally the output of this register is inverted and then ANDed with the userprovided read enable that becomes the internal read enable to the RAMiDP which is at the core of the FlFoiDC Thus the first read data takes two clock cycles to propagate through During the first data out read enable goes high for one clock cycle empty flag is deasserted and is hot propagated through the second register enabled by the read enable The first clock cycle brings the Empty Low and the second clock cycle brings the internal read enable high FtdEh and EF and then the data is read out by the second clock cycle Similarly the first write data after the full flag has a similar latency If the user has enabled the output registers the output registers will cause an extra clock delay during the first data out as they are clocked by the read clock and enabled by the read enable 1 First FtdEh and Clock Cycle to propagate the EF internally 2 Second FtdEh and Clock Cycle to generate internal Read Enable into the DPRAM 3 Third FtdEh and Clock Cycle to get the data out of the output registers Lattice Semiconductor Memory Usage Guide for MachXO Devices Figure 926 FIFoiDC without Output Registers NonPipelined Reset RPReset WvCiock WvEn RdCiock RdEn Data Data72 G invahd Data FuH AtmostFuH E mpty AimostEmpty Figure 927 FIFoiDC with Output Regis ters Pipelined Reset RPR eset WvCiock WvE n R dCiock Rd En Data 0 invahd D ata FuH AtmostFuH E mpty AimostEmpty Lattice Semiconductor Memory Usage Guide for MachXO Devices Distributed Single Port RAM DistributedSPRAM PFU Based PFU based Distributed Single Port RAM is created using the 4ihput LUT LookUp Table available in the PFU These LUTs can be cascaded to create larger distributed memory sizes Figure 928 shows the Distributed Single Port RAM module as generated by lPeXpress Figure 928 Distributed Single Port FlAM Module Generated by lPeXpress Clock 4 ClockEn 4 Reset 4 PFU based Distributed Single Port 4 Q WE 4 Memory Address 4 Data 4 The generated module makes use of the 4ihput LUT available in the PFU Additional logic such as clock and reset is generated by utilizing the resources available in the PFU Ports such as Read Clock FldClock and Read Clock Enable FldClockEh are not available in the hardware primi tiveThese are generated by the lPeXpress when the user wants the to enable the output registers in the lPeXpress configuration The various ports and their definitions are listed in Table 915 The table lists the corresponding ports for the mod ule generated by lPeXpress and for the primitive Table 915 PFUbased Distributed Single Port FlAM Port Definitions Generated Module PFU Primitive Description Active State Ports such as Clock Enable ClockEh are not available in the hardware primitive These are generated by lPeX press when the user wishes the to enable the output registers in the lPeXpress configuration Users have the option of enabling the output registers for Distributed Single Port RAM Distributed78PFlAM Fig ures 27 and 28 show the internal timing waveforms for the Distributed Single Port RAM Distributed78PFlAM with these options Lattice Semiconductor Memory Usage Guide for MachXO Devices Figure 929 PFUBased Distributed Single Port RAM Timing Waveform Without Output Registers Clock CIockEn WE Address m suwwww t Invalid Data Figure 930 PFUBased Distributed Single Port RAM Timing Waveform With Output Registers Reset Clock CIockEn WE Address mmmmmi 39suwm H i suAnanFu i NAnanFu Invalid Data Lattice Semiconductor Memory Usage Guide for MachXO Devices Distributed Dual Port RAM DistributedDPRAM PFU Based PFUbased Distributed Dual Port RAM is also created using the 4ihput LUT LookUp Table available in the PFU These LUTs can be cascaded to create larger distributed memory sizes Figure 931 Distributed Dual Port FlAM Module Generated by lPeXpress WrAddress 4 RdAddress 4 RdClock 4 RdClockEn 4 Reset 4 Distributed Dual Port a0 WrClock 4 WrClockEn 4 WE 4 Data 4 The generated module makes use of the 4ihput LUT available in the PFU Additional such as Clock and Reset is generated by utilizing the resources available in the PFU Ports such as Read Clock FldClock and Read Clock Enable FldClockEh are not available in the hardware primi tive These are generated by lPeXpress when the user wants the to enable the output registers in the lPeXpress configuration The various ports and their definitions are listed in Table 916 The table lists the corresponding ports for the mod ule generated by lPeXpress and for the primitive Table 916 PFU based Distributed DualPort FlAM Port Definitions Generated Module EBR Block Primitive Description Active State Ports such as Read Clock FldClock and Read Clock Enable FldClockEh are not available in the hardware primi tive These are generated by lPeXpress when the user wants the to enable the output registers in the lPeXpress configuration Lattice Semiconductor Memory Usage Guide for MachXO Devices Users have the option of enabling the output registers for Distributed Dual Port RAM DistributecLDPFiAM Fig ures 30 and 31 show the internal timing waveforms for the Distributed Dual Port RAM DistributecLDPFiAM with these options Figure 932 PFUBased Distributed Dual Port RAM Timing Waveform without Output Registers Non Pipelined WrCIockEn 74 WE WrAddress 7 Addio Ade Addiz FtdAddress 7 Data 7 Q Invalid Data Lattice Semiconductor Memory Usage Guide for MachXO Devices Figure 933 PFUBased Distributed Dual Port RAM Timing Waveform with Output Registers Pipelined Reset WrCIock 7 7 WrCIockEn X FidCIock 7 J RdClockEn f J i WE WrAddress 7 RdAddress 7 Q Invalid Data i i gtK 39 39 39 39 i 39 932 Lattice Semiconductor Memory Usage Guide for MachXO Devices Distributed ROM DistributedROM PFU Based PFUbased Distributed ROM is also created using the 4ihput LUT LookUp Table available in the PFU These LUTs can be cascaded to create larger distributed memory sizes Figure 934 shows the Distributed ROM module as generated by lPeXpress Figure 934 Distributed ROM Generated by lPeXpress Address 4b OutClock 4b PFUbased Distributed ROM Q OutClockEn 4 Reset 4b The generated module makes use of the 4ihput LUT available in the PFU Additional logic like clock and reset is generated by utilizing the resources available in the PFU Ports such as Out Clock OutClock and Out Clock Enable OutClockEh are not available in the hardware primi tive These are generated by lPeXpress when the user wants the to enable the output registers in the lPeXpress configuration The various ports and their definitions are listed in Table 917 The table lists the corresponding ports for the mod ule generated by lPeXpress and for the primitive Table 917 PFUbased Distributed ROM Port Definitions Generated Module PFU Block Primitive Description Active State Users have the option of enabling the output registers for Distributed ROM DistributediROM Figures 33 and 34 show the internal timing waveforms for the Distributed ROM with these options Figure 935 PFUBased ROM Timing Waveform Without Output Registers Lattice Semiconductor Memory Usage Guide for MachXO Devices Figure 936 PFUBased ROM Timing Waveform with Output Registers Reset OutClockEn suAnanFu mnm Address Q Invalid Data Dataio Initializing Memory In the EBFI based FIOM or RAM memory modes and the PFU based FIOM memory mode it is possible to specify the poweron state of each bit in the memory array Each bit in the memory array can have one of two values 0 or 1 Initialization File Formats The initialization file is an ASCII file which can be created or edited using any ASCII editor lPeXpress supports three types of memory file formats 1 Binary file 2 Hex file 3 Addressed Hex The file name for the initialization file is mem ltfile7namegtmem Each row depicts the value to be stored in a particular memory location and the number of characters or the number of columns represents the number of bits for each address or the width of the memory module The initialization file is primarily used for configuring the FIOMs The EBFI in RAM mode can also use the initializa tion file to preload the memory contents Binary File The binary file is a text file of 0 s and 1 sThe rows indicate the number of words and the columns indicate the width of the memory Memory Size 20X32 00100000010000000010000001000000 00000001000000010000000100000001 00000010000000100000001000000010 00000011000000110000001100000011 00000100000001000000010000000100 00000101000001010000010100000101 Lattice Semiconductor Memory Usage Guide for MachXO Devices 00000110000001100000011000000110 00000111000001110000011100000111 0000100001001000OOOOlOOOOlOOlOOO 00001001010010010000100101001001 00001010010010100000101001001010 00001011010010110000101101001011 00001100000011000000110000001100 00001101001011010000110100101101 00001110001111100000111000111110 00001111001111110000111100111111 0001000OOOOlOOOOOOOlOOOOOOOlOOOO OOOlOOOlOOOlOOOlOOOl000100010001 000100100001001000OlOOlOOOOlOOlO 00010011000100110001001100010011 Hex File The hex file is essentially a text file of hex characters arranged in a similar rowcolumn arrangementThe number of rows in the file is same as the number of address locations with each row indicating the content of the memory location Memory Size 8X16 A001 0803 1004 CE06 0007 040A 0017 02A4 Addressed Hex Addressed heX consists of lines of address and data Each line starts with an address followed by a colon and any number of data The format of the memfile is address data data data data where address and data are hexadec imal numbers A0 03 F3 3E 4F 82 SB 9F The first line puts 03 at address A0 F3 at address A1 SE at address A2and 4F at address A3 The second line puts SB at address 82 and 9F at address BS There is no limitation on the values of address and data The value range is automatically checked based on the values of addriwidth and dataiwidth If there is an error in an address or data value an error message is printed Users need not specify data at all address locations If data is not specified at a certain address the data at that location is initialized to 0 lPeXpress makes memory initialization possible through both the synthesis and simula tion flows Technical Support Assistance Hotline 1800LATTICE North America 15032688001 Outside North America email techsupportatticesemicom Internet wwwlatticesemicom Lattice Semiconductor Memory Usage Guide for MachXO Devices Revision History memory access DC withioutput Registers waveforms 936 Lattice Semiconductor Memory Usage Guide for MachXO Devices Appendix A Attribute Definitions DATA7WDTH Data width is associated with the RAM and FIFO elements The DATA7WDTH attribute defines the number of bits in each word It takes the values defined in the RAM size tables in each memory module REGMODE REGMODE or the Register mode attribute is used to enable pipelihihg in the memoryThis attribute is associated with the RAM and FIFO elementsThe REGMODE attribute takes the NOFtEG or OUTREG mode parameter that disables and enables the output pipeline registers RESETMODE The RESETMODE attribute allows users to select the mode of reset in the memory This attribute is associated with the block RAM elements RESETMODE takes two parameters SYNC and ASYNC SYNC means that the memory reset is synchronized with the clock ASYNC means that the memory reset is asynchronous to clock CSDECODE CSDECODE or the Chip Select Decode attributes are associated to block RAM elements Chip Select CS is a useful port when multiple cascaded EBFt blocks are required by the memory The CS signal forms the M88 for the address when multiple EBFt blocks are cascaded CS is a 3bit bus so it can cascade eight memories easily CSDECODE takes the following parameters 000 001 010 O1 1 100 101 1 10 and 1 1 1 CSDECODE values determine the decoding value of CS2O CSDECODE7W is chip select decode for write and CSDECODEiFt is chip select decode for read for Pseudo Dual Port RAM CSDECODE7A and CSDECODEB are used for true dual port RAM elements and refer to the A and B ports WRITEMODE The WFtlTEMODE attribute is associated with the block RAM elements It takes the NORMAL WFtlTETHFtOUGH and FtEADBEFOFtEWFtlTE mode parameters In NORMAL mode the output data does not change or get updated during the write operation This mode is sup ported for all data widths lh WFtlTETHFtOUGH mode the output data is updated with the input data during the write cycleThis mode is sup ported for all data widths lh FtEADBEFOFtEWFtlTE mode the output data port is updated with the existing data stored in the write address during a write cycle This mode is supported for X9 X18 and X36 data widths WFtlTEMODEiA and WRITEMODEB are used for dual port RAM elements and refer to the A and B ports in case of aTrue Dual Port RAM For all modes of the True Dual Port module simultaneous read access from one port and write access from the other port to the same memory address is not recommended The read data may be unknown in this situation Also simultaneous write access to the same address from both ports is not recommended When this occurs the data stored in the address becomes undetermined when one port tries to write a 39H39 and the other tries to write a 39L39 It is recommended that users implement control logic to identify this situation if it occurs and then either 1 Implement status signals to flag the read data as possibly invalid or 2 Implement control logic to prevent the simultaneous access from both ports GSR GSFt the Global Set Reset attribute is used to enable or disable the global setreset for the RAM element ice MachXO sysCLOCK ggrpgg3 ggtor Desrgn and Usage Gurde September 2006 Technical Note TN1089 Introduction As clock distribution and clock skew management become critical factors in overall system performance the Phase Locked Loop PLL is increasing in importance for digital designers Lattice incorporates its sysCLOCKT39V39 PLL tech nology in the MachXOT39V39 device family to help designers manage clocks within their designsThe PLL components in the MachXO device family use the same PLL as the LatticeECPT39V39 LatticeECT39VI and LatticeXPTM families The number of PLLs for each device are listed in Table 101 Table 10 1 MachXO Family and PLLs l MachX0256 l MachX0640 l MachXO1200 l MachX02280 l Number of PLLs l o l o l 1 l 2 l MachXO Top Level View Figure 101 shows a chiplevel view of the MachXOlZOO and MachX02280 Figure 10 1 Top Level View of MachXO1200 and MachX02280 l We Baum l l svsmanm U N N x x C C 3963 3963 Q Q m m i i E E E E g g E E L L 5 g m 2 F mquot m to Q c 0 U t L U syleBa nkS syleBa nk 4 sysio Banks MachXO1200 MachX02280 sys C L O C K P L L This technical note describes the features and functions of the PLLs and their configuration in the ispLEVEFt design tool Figure 102 shows the block diagram of the PLL 2006 Lattice Semiconductor Corp All Lattice trademarks registered trademarks patents and disclaimers are as listed at wwwlatticesemi comlegal All other brand or product names are trademarks or registered trademarks of their r b M T r r quotIquot 39t Hung m uu wwwlatticesemicom 101 tn1089012 MachXO sysCLOCK PLL Lattice Semiconductor Design and Usage Guide Figure 102 PLL Block Diagram RST D CLKI D CLKOK CLKOK Phase amp Loop VCO CLKOP PhaseDuly Frequency Filler DlVlder Select Detector CLKFB 3 CLKlNTFB DDAMODE DDAIZR Lock LOCK DDAILAG 4 DDAIDEL2 0 lnlemal Feedback Clocklree Feedback Features Clock synthesis Phase shiftduty cycle selection Internal clock tree and external feedback Dynamic delay adjustment No external components required Lock detect output Func onalDesc p on PLL Divider and Delay Blocks Input Clock CLKI Divider The CLKI divider is used to control the input clock frequency into the PLL block The divider setting directly corre sponds to the divisor of the output clock The input and output of the input divider must be within the input and out put frequency ranges specified in the device data sheet Feedback Loop CLKFB Divider The CLKFB divider is used to divide the feedback signal Effectively this multiplies the output clock because the divided feedback must speed up to match the input frequency into the PLL blockThe PLL block increases the out put frequency until the divided feedback frequency equals the input frequencyThe input and output of the feedback divider must be within the input and output frequency ranges specified in the device data sheet Delay Adjustment The delay adjust circuit provides programmable clock delay The programmable clock delay allows for step delays in increments of 250ps nominal for a total of 200ns lagging or leading The time delay setting has a tolerance See the device data sheet for details Under this mode CLKOP CLKOS and CLKOK are identically affectedThe delay adjustment has two modes of operation Static Delay Adjustment In this mode the userselected delay is configured at powerup Dynamic Delay Adjustment DDA In this mode a simple bus is used to configure the delayThe bus signals are available to the general purpose FPGA Output Clock CLKOP Divider The CLKOP divider serves the dual purposes of squaring the duty cycle of the VCO output and scaling up the VCO frequency into the 420MHz to 840MHz range to minimize jitter Refer to Table for CLKOP Divider values MachXO sysCLOCK PLL Lattice Semiconductor Design and Usage Guide CLKOK Divider The CLKOK divider feeds the global clock net It divides the CLKOP signal of the PLL by the value of the divider It can be set to values of 2 4 6126128 PLL Inputs and Outputs CLKI Input The CLKI signal is the reference clock for the PLL It must conform to the specifications in the data sheet in order for the PLL to operate correctly The CLKI can be derived from a dedicated dualpurpose pin or from routing RST Input The PLL reset occurs under two conditions At powerup an internal powerup reset signal from the configuration block resets the PLLThe user controlled PLL reset signal RST is provided as part of the PLL module that can be driven by an internally generated reset function or a pin This RST signal resets all internal PLL counters When RST goes inactive the PLL will start the lockin process and will take the tLOCK time to complete the PLL lock Note The use of RST is mandatory RST must be asserted to start the PLL locking process or to restart the locking process after losing lock Figure 103 shows the timing diagram of the HST input Figure 103 FIST Input Timing Diagram quot tRST PLLiRST H tLOCK 4gtr LOOK CLKFB Input The feedback signal to the PLL which is fed through the feedback divider can be derived from the Primary Clock net CLKOP a dedicated dualpurpose pin directly from the CLKOP divider CLKINTFB or from general routing External feedback allows the designer to compensate for boardlevel clock alignment CLKOP Output The sysCLOCK PLL main clock output CLKOP is a signal available for selection as a primary clock CLKOS Output with Phase and Duty Cycle Select The sysCLOCK PLL auxiliary clock output CLKOS is a signal available for selection as a primary clock The CLKOS is used when phase shift andor duty cycle adjustment is desiredThe programmable phase shift allows for different phase in increments of 45 to 315 The duty select feature provides duty select in 18th of the clock period CLKOK Output with Lower Frequency The CLKOK is used when a lower frequency is desired It is a signal available for selection as a primary clock Dynamic Delay Control IIO Ports Refer to Table 104 for detailed information LOCK Output The LOCK output provides information about the status of the PLL After the device is powered up and the input clock is valid the PLL will achieve lock within the specified lock time Once lock is achieved the PLL lock signal will be asserted If during operation the input clock or feedback signals to the PLL become invalid the PLL will lose lock PLL RST must be applied to resynchronize the PLL to the reference clock The LOCK signal is available to the FPGA routing to implement generation of RST MachXO sysCLOCK PLL Lattice Semiconductor Design and Usage Guide ModelSim simulation models take two to four reference clock cycles from RST release to LOCK high PLL Attributes The PLL utilizes several attributes that allow the configuration of the PLL through source constraints This section details these attributes and their usage FIN The input frequency can be any value within the specified frequency range based on the divider settings CLKLDIV CLKFBiDIV CLKOPiDIV CLKOKiDIV These dividers determine the output frequencies of each output clock The user is not allowed to input an invalid combination determined by the input frequency the dividers and the PLL specifications FREQUENCYPNCLKOP FREQUENCYPNCLKOK These output clock frequencies determine the divider values DEL The FDEL attribute is used to pass the Delay Adjustment step associated with the Output Clock of the PLL This allows the user to advance or retard the Output Clock by the step value passed multiplied by 250ps hominalThe step ranges from 8 to 8 resulting the total delay range to 2hs PHASEADJ The PHASEADJ attribute is used to select Coarse Phase Shift for CLKOS output The phase adjustment is pro grammable in 45 increments DUTY The DUTY attribute is used to select the Duty Cycle for CLKOS output The Duty Cycle is programmable at 18 of the period increment FB MODE There are three sources of feedback signals that can drive the CLKFB Divider Internal CLKOP Clock Tree and User Clock CLKOP Clock Tree feedback is used by default Internal feedback takes the CLKOP output at CLKOP Divider output before the Clock Tree to minimize the feedback path delay The User Clock feedback is driven from the dedicated pin clock pin or user specified internal logic DELAYCNTL This attribute is designed to select the Delay Adjustment mode If the attribute is set to DYNAMIC the delay con trol switches between Dynamic and Static depending upon the input logic of DDAMODE pih If the attribute is set to STATIC Dynamic Delay inputs are ignored in this mode CLKOK Output with Lower Frequency The CLKOK is used when a lower frequency is desired It is a signal available for selection as a primary clock MachXO PLL Primitive Definitions A PLL primitive is used for MachXO PLL implementation The definitions of the PLL lO ports are shown in Table 102 Figure 104 shows the MachXO PLL primitive library symbolThe EHXPLLC includes all features avail able ih the PLL including Dynamic Delay Adjustment MachXO sysCLOCK PLL Lattice Semiconductor Design and Usage Guide Figure 104 MACHXO PLL Primitive Symbols Table 102 MachXO PLL 0 Definitions source PLL Attributes Definitions The MachXO PLL utilizes several attributes that allow the configuration of the PLL through source constraintsThis section details these attributes and their usage Table 103 MachXO PLL UserAttributes MM GUI Editor Default Attributes Access Attribute Name Support Value 00010205102050100 00 O 45 90315 Lattice Semiconductor MachXO sysCLOCK PLL Design and Usage Guide Table 103 MachXO PLL UserAttributes Continued N 01M N MM GUI Access Editor Support Default Attributes Attribute Name Value Y DUTY N 4 Increment upon STATIC This mode sets the delay control to Static Control CLKOPiDIV value is calculated to maximize the fvco within the specified range based on FIN CLKOPiFREQ in conjunction with CLKLDIV and CLKFBiDIV values The CLKOP Dividervalues are 2 4 6 830 32 if CLKOS is unused and 2 4 8 16 32 if CLKOS is used All divider settings are user transparent in Frequency Mode These are user attributes in Divider Mode CLKFB source INTERNAL CLKINTFB internal feedback path is used CLKOP Primary Clock net feedback node of CLKOP User Clock General routing includes FPGA logic or general lO Primary Clock net includes user connecting CLKOP to CLKFB internally to the chip orthe use of a device clock pin Dedicated PLL feedback pin Refer to data sheet for current specifications This attribute is not available in the lPexpress GUI After reviewing the trace report file users can determine the amount of delay that will best fit the clocking in their design Further information on FDEL settings is described in the following section FDEL Settings There are four ways the user can enter the desired FDEL value Although the FDEL entry is not available in the lPexpress GUI the module generated by lPexpress includes the attribute with default value Users can replace it with a desired value Example of source code with default FDEL value attribute FDEL of ehxpllmod00 generic map FDELgtquot 0quot label is quot0quot quot 2 Preference File User may specify the preference in the Preference file Example ASIC quotFDELCODEOOquot TYPE quotEHXPLLBquot FDELquot 2quot 3 PreMap Preference Editor Users can enter the FDEL value in the PreMap Preference Editor as shown in Figure 105 1 06 MachXO sysCLOCK PLL Lattice Semiconductor Design and Usage Guide Figure 105 PreMap Preference Editor meal senmlv ln amp l 4 9 Maine evI1oo H Nets Cells Black iCyclsMsXDzluy Mas 4 EPIC Device Editor Users can edit their preferences in the EPIC Device Editor as shown in Figure 106 Figure 106 EPIC Preferences Edit Window zvallJLD PLL3RZDC1 29 gmqu v gvound v gmund v DETEETDH DtlLEIIK canoe Dynamic Delay Adjustment The Dynamic Delay Adjustment is controlled by the DDAMODE input When the DDAMODE input is set to 1 the delay control is done through the inputs DDAIZFl DDAILAG and DDAIDEL2O For this mode the attribute DELAYCNTLquot must be set to DYNAMIC Table 104 shows the delay adjustment values based on the attribute nput settings MachXO sysCLOCK PLL Lattice Semiconductor Design and Usage Guide In this mode the PLL may come out of lock due to the abrupt change of phase RST must be asserted to relock the PLL Upon deassertion of RST the PLL will start the lockin process and will take the tLOCK time to complete the PLL lock Table 104 Delay Adjustment 1 ley ps DDAIZR DDAILAG DDAIDEL20 Nominal MachXO PLL Usage in lPexpress The MachXO PLL is fully supported by lPeXpress in ispLEVEFt Figure 107 shows the main window when PLL is selected The only entry required in this window is the module name Other entries are set to the project settings The user may change these entries as desired After entering a module name click on Customize to open the Configuration Tab window as shown in Figure 108 MachXO sysCLOCK PLL Lattice Semiconductor Design and Usage Guide Figure 107 lPexpress Main Window leala 7 Nm 3 4 MW Tu generate the module Dr IP enlertne informatan m the L JAIW WEJ W enabled fields such as PmJeLt Pam File Name etc and click E J 39 on the Custnmtze button A uiarug will upen to allow 2 usmmrzanun or me seietled muuuiz or P Maun39yp Mndule Veum 2n 2 n svtlmvB x i JAVMeuwamieg l Jnswmie maan m tr ALMencvyJAadues 3 w is JCumumalm Pmlwhm JCnmetimty JDSP w JPvmssmslemley Flam W DewEnvy Dam Fmrly Macm Pail Nam mymanmcss ispLever39 lPxMmelex 1 l Wm ram l l li Configuration Tab The Configuration Tab lists all user accessible attributes with default values set Upon completion of entries click on Generate to generate source and constraint files The user may choose to use the lpc file to load parameters Mode There are two modes for configuring the PLL in the Configuration Tab Frequency Mode and Divider Mode MachXO sysCLOCK PLL Lattice Semiconductor Design and Usage Guide Frequency Mode n this mode the user enters input and output clock frequencies and the software calculates the divider settings for user If the output frequency the user entered is not achievable the nearest frequency will be displayed in the Actual text box After input and output frequencies are entered clicking the Calculate button will display the divider values Figure 108 shows the Frequency Mode configuration tab Figure 108 MachXO PLL Configuration Tab Frequency Mode Screen Capture 1 5 Earlmsivn Gmaucwgl Cm guatian r PutnamMade r om Mud cm c p mm was nw Emmy mm Mm Ian l l v F jF W Fr cums 34 r EmhkCLKDS rm M F aluminang v 39 g W J W 1 max wwi r EMNaELKGK IT Dynum Dlvcmm A wl mm 944an A Ma r Impun LPCmIspLevevpmJect aammyn Clnse Help 1010 MachXO sysCLOCK PLL Lattice Semiconductor Design and Usage Guide Divider Mode In this mode the user sets the divider settings with input frequency The user must choose the CLKOP Divider value to maximize the fVOO to achieve 0 nmum PLL performance After input frequency and divider settings are complete clicking the Calculate button will display the frequencies Figure 109 shows the Divider Mode Configura tion tab Figure 109 MachXO PLL Configuration Tab Divider Mode n 5 Carlinum mummy l as l Emu cums mama Mud 1mg rrtuu m 1 i ll Wu W11 mt 7nmw i l Emmux l Dwmmcm 33 m r mumMme r was Made on cums I r Adual rimno hm Divide 39 mummy mu r l F m H v in l l r lmpun LPC in ume mum arm l Class Help Frequency Programming in Divider Mode for Advanced Users Table 105 Frequency Limits 1011 MachXO sysCLOCK PLL Lattice Semiconductor Design and Usage Guide Equations for generating Divider Settings and Output Frequency Ranges for Divider Mode Users The divider names are abbreviated with legacy names as follows CLKI DIVIDEFt M CLKFB DIVIDEFt N CLKOP DIVIDEFt V CLKOK DIVIDEFt K fvco Constraint From the loop fOUTfNNM 1 From the loop fVCO tom v 2 Substitute 1 in 2 yields tVCO 1m NM V 3 Arrange 3 1m fvco VNM 4 From equation 4 fINMIN fVCOMIN VNM 5 fINMAX fVCOMAXVNM 6 prD Constraint From the loop fPFD fiNM 7 fIN fPFD M fINMIN fPFDMIN M 25 My assume fPFDMIN 25 8 So equation 5 becomes leMIN tVCOMIN VNM it below 25 M round up to 25 M 9 From the loop tINMAX 1PFDMAX M 420 M 10 Assume fINMAX 420 So equation 6 becomes thMAX tVCOMAXVNM it above 420 round down to 420 11 From equation 1 tOUTMIN tINMNNM it below 25 N round up to 25 N 12 tOUTMAX tINMAXNM it above 420 round down to 420 13 fOUTKMlN fOUTMINK fOUTKMAX fOUTMAXK Example When CLKOS is Not Used Assume tIN 40 MHZ M 2 N 3 V 4 Then tOUT 40 32 60 within range tVCO 60 4 240 out of range 1012 MachXO sysCLOCK PLL Lattice Semiconductor Design and Usage Guide prD4O220 or60320 outofrange Assume M 1 Then fOUT 4031 120 within range fVCO 120 4 480 within range but not an optimum value fPFD 401 or 1203 40 within range In this case V 6 will satisfy all conditions fVCO 1206 720 lt 840 Oscillator OSCC There is a dedicated oscillator in the MachXO device whose output is made available for user The oscillator frequency range is 18 to 26 MHZ The output of the oscillator can also be routed as an input clock to the clock treeThe oscillator frequency output can be further divided by internal logic user logic for lower frequen cies if desiredThe oscillator is powered down when not in use Primitive Name OSCC Table 106 OSCC Port Definition l lO l Name l Description 1 Output l 080 l OscillatorClockOutput l Figure 10 10 Oscillator Primitive Symbol OSCC OSCC Oscillator Usage with VHDL Example COMPONENT oscc PORT OSCOUT stdlogic END COMPONENT begin OSCInstO OSCC PORT MAP OSC gt oscint ClockControl Distribution Network The MachXO family provides global clocks four primary clocks and four secondary clocks These global signals are generated from four 161 muxes as shown in Figure 1011 and Figure 1012 The available clock sources for the MachX0256 and MachX064O devices are four dual function clock pins and 12 internal routing signals The available clock sources for the MachX02280 devices are four dual function clock pins siX internal routing signals and siX PLL outputs Dual function lOs are provided for clocking usage These lOs are used as user programmable lO pins when not in use as PLL or clock pins 1013 MachXO sysCLOCK PLL Lattice Semiconductor Design and Usage Guide PCLK PIO Primary Clock Pads There are two PCLK PlOs on top and two PlOs on bottom for a total of four pins for each MachXO device These pads connect directly to the global clock network PLL PIO There are two pad pairs one pad pair on the upper side and one pair on the lower side for the MachX02280 and one pad pair for the MachXOlZOO PLLFB PIO Two pad pairs one pad pair on the upper side and one pair on the lower side for the MachX02280 and one pad pair for the MachXOlZOO Primary Clock Mux Connectivity The Primary Clock MuX input sources include Primary clock input pins PLL outputs From routing The Primary Clock MuX outputs feed four clock input switch boxes in a PFU Figure 10 1 1 Primary Clock Net Global Clocks 4 Global Clocks 4 From Routing From Routing PLL Outputs MachX0256 and MachXOlZOO MachX064O Global Clocks From Routing PLL Outputs PCLKB MachXOZZBO 1014 MachXO sysCLOCK PLL Lattice Semiconductor Design and Usage Guide Secondary ClockCEILSR Mux Connectivity The Secondary ClockCELSR Mux input sources include Primary Clock input pins From routing The Secondary ClockCELSR Mux outputs teed tour clock input switch boxes and eight control input switch boxes in each PFU Each slice includes one clock input switch box and two control input switch boxes one for CE Clock Enable and the other for LSR Local SetReset Figure 10 12 Secondary ClockControl Net All MachXO SCLKOCELSR From Routing SCLKl CELSR Global Clocks SCLK2CELSR SCLKBCELSR Primary Clock and Secondary ClockCEILSR Distribution Network The Clock Input Switch Box and Control Input Switch Box are described in Figure 1013 and Figure 1014 Figure 1015 shows the entire connectivity of the MachXO clock distribution network for each PFU Figure 10 13 Clock Switch Mux to Each PFU Slice Primaiy Clock Secondary Clock Routing GND Secondary Clock CELSR To PFU SLICE Routing CELSR VCCGND 1015 MachXO sysCLOCK PLL Lattice Semiconductor Design and Usage Guide Figure 10 15 Primary Clock and Secondary CIockCELSFI Distribution Primary Clock Net Global Clocks 9119 1 PCLKO 1 Primary Clock 4 From Routing 6 PFU CLK03 OLKOP l l l l l l l l l l CLKOS l PLL CLKOK I f PCLK2 Secondainlock 6 9 l CELSR l Outputs l 7 7 7 7 77 l l l l l l OLKOP OLKOS OLKOK l Secondaiy Clock 1 l FU CELSR l l l CE03 3 l 3939 Secondary ClockCEILSR Net l 8 l r r r r 7 r 7 r 7 r a gl l F R 12 l l SCLKOCELSR L005quot l 1 rom outing 7vi 7 7 7 7 J Global Clocks l l l l l l l l 7 l l l SCLKzCELSR Secondaiy Clock l l to l CELSR l PFU c r l l LSR03 l 3 l l l l l l l Maximum Number of Secondary Clocks Available As illustrated in Figure Figure 1015 there are four secondary clock nets in the clock distribution network but only three of them are reaching the clock input mux at PFUThis limits the number of total secondary clocks available to three Post Map Preference Editor Usage Fine delay adjustment can be entered in the PostMap Preference Editor after Place and Run to determine the required timing for the system design The Clock Preference assignments are also entered in the PostMap Preference Editor Figure 1016 shows an example screen shot 1016 MachXO sysCLOCK PLL Lattice Semiconductor Design and Usage Guide Figure 1016 PostMap Preference Editor Example File 511 Vim Preferean Tani Help JUQB JSHaEOOJQ EQI39gPiIa oa r J Maltade ath PCB Layout Recommendations for VCCPLL and GNDPLL if Separate Pins are Available It is best to connect VCCPLL to V00 at a single point using a filter and to create a separate GNDpLL plane directly under it tied via a single point to GND Separate islands for both VCCPLL and GNDPLL are recommended if applicable Technical Support Assistance Hotline 1BOOLA39I39I39ICE North America 15032688001 Outside North America email techsupportatticesemicom Internet wwwatticesemicom Revision History 1017 Power Estimation and Management ggrgg3 ggtor for MachXO DeVIces September 2007 Technical Note TN1090 Introduction One requirement for design engineers using programmable devices is to be able to calculate the power dissipation for a particular device used on a board Lattice s ispLEVEFl design tools include the Power Calculator tool which allows designers to calculate the power dissipation for a given device This technical note provides users with details for using the Power Calculator to calculate the power consumption of the Lattice MachXOT39V39 family of devices General guidelines for reducing power consumption are also included Power Supply Sequencing and Hot Socketing The MachXO devices have been designed to ensure predictable behavior during powerup and powerdown Power supplies can be sequenced in any order During powerup and powerdown sequences the lOs remain in tristate until the power supply voltage is high enough to ensure reliable operation In addition leakage into lO pins is controlled to within specified limits listed in the device data sheetThis allows for easy integration with the rest of the system These capabilities make the MachXO ideal for many multiple power supply and hotswap applications Recommended Powerup Sequence As described in the previous paragraph the supplies can be sequenced in any order However once internal power is achieved determined by VCC VCCAUX the device releases lOs from tristate and the management of lOs becomes the designer s responsibility Therefore to simplify a system design it is recommended that supplies be sequenced VCCIO VCC VCCAUX If VCCIO is tied to VCC or VCCAUX it is recommended that VCCIO and the associated power supply are powered up before the remaining supply Please refer to the Hot Socketing section of the device data sheet for more information Power Calculator Hardware Assumptions Power consumption of the device can be broken down coarsely into the DC portion and the AC portion The Power Calculator reports the power dissipation in terms of 1 DC portion of the power consumption 2 AC portion of the power consumption The DC power or the static power consumption is the total power consumption of the used and the unused resources These power components are fixed for each resource and depend upon the number of resource units utilizedThe DC component also includes the static power dissipation for the unused resources of the device The AC portion of the power consumption is associated with the used resources and is the dynamic part of the power consumption lts power dissipation is directly proportional to the frequency at which the resource is running and the number of resource units used Power Calculator Power Calculator Equations The power equations used in the Power Calculator are shown below 2007 Lattice Semiconductor Corp All Lattice trademarks registered trademarks patents and disclaimers are as listed at wwwlatticesemi comlegal All other brand or product names are trademarks or registered trademarks of their r h M T r r quotIquot l Hang m uu wwwlatticesemicom 1 11 tn10907011 Power Estimation and Management Lattice Semiconductor for MachXO Devices Total DC Power Resource Total DC Power of Used Portion Total DC Power of Unused Portion DC Leakage per Resource when Used NRESOU CE DC Leakage per Resource when Unused NTOTAL RESOURCE NRESOURCEH Where NTOTAL RESOURCE is the total number of resources in a device NRESOURCE is the number of resources used in the design The total DC power consumption for all the resources as per the design data is the Quiescent Power in the Power Calculator The AC Power on the other hand is governed by the following equation Total AC Power Resource KRESOURCE fMAX AFRESOURCE NRESOURCE Where NTOTAL RESOURCE is the total number of resources in a device NRESOURCE is the number of resources used in the design KRESOURCE is the power constant for the resourceThe units of this factor are mWMHz is the max frequency at which the resource is running Frequency is measured in MHz AFRESOURCE is the activity factor for the resource group Activity factor is in terms of the percentage of switching frequency Based on the above equations if we wish to calculate the power consumption of the slice portion it will be as shown below Total DC Power Slice Total DC Power of Used Portion Total DC Power of Unused Portion DC Leakage per Slice when Used NSLICE DC Leakage per Slice when Unused NTOTAL SLICE NSLICE Total AC Power Slice KSLICE fMAX AFSLICE NSLICE Power Calculations The Power Calculator is a powerful tool which allows users to estimate power consumption at three different levels 1 Estimate of the utilized resources before completing place and route 2 Post place and route design 3 Post place and route post trace and post simulation For first level estimation the user provides estimates of device usage in the Power Calculator Wizard and the tool provides a rough estimate of the power consumption In the second level a more accurate approach the user imports the actual device utilization by importing the post place and route netlist NCD file The third and final stage brings even more accuracy to the calculation by importing the Trace TWR file to popu late the maximum frequencies fMAX into the tool Users also have the option of importing the information from the post simulation VCD file and calculating the activity factor and toggle rates of various components These power calculations are discussed in detail in the following sections of this document Power Estimation and Management Lattice Semiconductor for MachXO Devices Starting the Power Calculator The user may launch the Power Calculator using one of two methods The first method is by clicking the Power Calculator button in the toolbar as shown in Figure 1 Figure 111 Starting Power Calculator From the Toolbar Alternatively users can launch the Power Calculator by going to the Tools menu and selecting Power Calculator as shown in Figure Power Estimation and Management Lattice Semiconductor for MachXO Devices Figure 1 12 Starting Power Calculator from Tools Menu mug Main T0015 Menu and Mugs Simulator m Render 7 Camels The Power Calculator does not support some of Lattice s older devices The toolbar button and menu item is only present when supported devices are selected Creating a Power Calculator Project After starting the Power Calculator the user will see the Power Calculator window Click on File gt Menu and select New to get to the Start Project window as shown in Figure 113 Power Estimation and Management Lattice Semiconductor f r MachXO Devices Figure 1 13 Power Calculator Start Project Window Create New Project V II Flla Edll Hall Dlwllll all Pl Power calculator New Prniect 5 Power Calculalor 50 CnpyrigM C 2mm Power Vie it WW Project Name vrllogmerarhlcaldeslgnl ijecl Dira DWE luguerllugJIierzrthichdeSign l3 NCD File vl39llugJIerarthltaL axlgn nm 5 Finish Canch Hzlu The Start Project window is used to create a new Power Calculator project pep project Three pieces of data must be input into the Start Project window 1 The Power Calculator project name by default is the same as the Project Navigator project nameThis can be changed if desired The Project directory is where the Power Calculator project pep file will be stored By default it is stored in the Main Project folder The MOD file is automatically selected if available or users can browse to the NOD file in a different loca N 9quot tion Power Calculator Main Window The main Power Calculator window is shown in Figure 114 Power Estimation and Management f r Lattice Semiconductor MachXO Devices Figure 1 14 Power Calculator Main Window Type We w The top pane of the window shows information about the device family device and the part number as it appears in the Project Navigator The V00 used for the power calculation is also listed Users have a choice of selecting the core voltage V00 with 5 o of the nominal value or values The option of selecting VOOJ is also available Users provide the ambient temperature and thejunction temperature is calculated based on that Users can also entervalues for airflow in Linear Feet per Minute LFM along with heat sink to get thejunction tem perature A table in the top part of the Power Calculator summarizes the currents and power consumption associated with each type of power supply for the device This also takes into consideration the lO power supplies In the middle pane of the window there are three tabs 1 Power View The first tab is the PowerView Under this tab the Power Calculator tool has an interactive spreadsheet type interface with all values in terms of power consumption The first column breaks down the design in terms of clock domains The second and third columns which are shaded blue in the tool provide the DC or static and AC or dynamic power consumption respec 39vely In case of the lOs there are four columns that are shaded blueThese provide the DC and AC power for lOs for the core voltage V00 and the lO voltage supply VOO O The first three rows show the Quiescent Power forvcc VOOAUX and VOOJ These are DC power numbers for a blank device or a device with no resource utilization Power Estimation and Management Lattice Semiconductor for MachXO Devices Some of the cells are shaded yellow in the toolThese cells are editable cells and users can type in values such as frequency activity factors and resource utilizationThe second tab the Report tab is the summaly of the PowerView This report is in text format and provides the details of the power consumption ICC ViewThe second tab is the ICC view This tab is exactly same as the PowerView tab except that all values are in terms of current or mA Report The third and final tab is the Report View This is an HTML type of Power Calculator report It sum marizes the contents of the Power and ICC views N no The final pane or the lower pane of the window is the log pane where users can see the log of the various opera tions in the Power Calculator Figure 1 15 Power Calculator Main Window Po wer Report View Dwtu m m ispLever 50 Power Calculator 50 cwyrtumc mm Latdle Summudunar Can Anmgim Rexewed Power CalculatorWizard The Power Calculator Wizard estimates the power consumption of a given designThis estimation is done before a design is created The user must understand the logic requirements of the design The wizard allows the user to provide these parameters and then estimates the power consumption of the device To start the Power Calculator in theWizard mode go to the File menu and selectWizard Alternatively click on the Wizard button to get the Power Calculator Wizard window as shown in Figure 116 Select the option Create a New Proiect and check the Wizard check box in the Power Calculator Start Proiect window Users are required to provide the project name and the project folder Click Continue Since this is power estimation before the actual design no NCD file is required Lattice Semiconductor Power Estimation and Management r MachXO Devices Figure 1 16 Power Calculator Start Project Window Using the New Project Window Wizard Wane m lElll Pm mumquot s n mam 2am LmizzszmtmnauuartalvAllmamx ukrved a run umpme r am In x a 7 mm mm mm mm mm mum m m mm 1 i mummy mummy j as The next screen allows users to select the device family device and appropriate part number for which users plan to estimate power After making the proper selections click Continue see Figu 1 7 Figure 117 Power Calculator Wizard Mode Window Device Selection 3 ram lly w H Device LCMXOS IDE v Fan Nam LcmxomuEmuuczs v Cammue Back Cancll Hth Lattice Semiconductor Power Estimation and Management f r MachXO Devices In the following screens as shown in Figures 812 users can select further resources like lO types clock name frequency at which the clock is running and other parameters by selecting the appropriate resource using the pull 1 Routing Resources 2 Logic 3 EBFl 4 5 PLL 6 Clock Tree The numbers in these windows refer to the number of clocks and the index corresponds to each clock By default the clock names are clk71 clk72 and so on Users can change the Name text box For each clock domain and resource users can name of each clock by typing in the Clock specify parameters such as frequency activity fac tor etc In the final window users must click the Create button for each clockdriven resource to include the param eters they have specified for it Figure 118 Power Calculator Wizard Mode Window Resource Specification 19 FlnlSh Back Cancel Help These parameters are then used in the Power Type View window which can be seen upon clicking on F Figure 1 iner almlatnr 7 Wizard 5 TYPE urResuurce LBS C Number mam Domains n Lug lo Cluck Tm Clock Dam am ClotKName Frequmcy MHz Activity Fatlnr m Number afSlices in Logic Made Numbnrufsliczs in Dist RAM Mndnt Number atsnus m Ripple Mode Power Estimation and Management Lattice Semiconductor for MachXO Devices Figure 1 19 Power Calculator Wizard Mode Main Window um Hut 5m Power Calculator Creating a New ProjectWithout the NOD File When starting a new project without the NOD file begin either by using the Wizard as discussed above or by selecting the Create a New Project option in the Power Calculator gt Start Project Users are required to provide a project name and project directory After clicking Continue the Power Calculator main window will be displayed However in this case there are no resources addedThe power estimation row for the routing resources is always available in the Power Calculator Users are required to add more information like the slice EBFl lO PLL and clock tree utilization to calculate the power consumption For example if the user wants to add the logic resources as shown in Figure 1110 rightclick on Logic and select Add Row in the popup menu 1110 Power Estimation and Management Lattice Semiconductor for MachXO Devices Figure 1 110 Power Calculator Main Window Adding Resources Dwm m Strut This adds a new row for the logic resource utilization with clock domain as clkil Similarly users can add other resources like EBFi lOs PLLs routing etc Each of these resources is for the AC power estimation and categorized by clock domains Power Calculator Creating a New Project with the NOD File If the post place and routed NCD file is available the Power Calculator can use this file to import accurate informa tion about the design data and resource utilization and calculate the power When the Power Calculator is started the NOD file is automatically placed in the NOD File option if it is available in the project directow Otherwise browse to the NOD file in the Power Calculator 1111 Power Estimation and Management f r Lattice Semiconductor MachXO Devices Figure 1 11 1 Power Calculator Start Project Window with Post PAR NCD File 491 51 Luau mmuuuorcmpAummnmm szu mm m PIok Dlem film Lhwmm Mwn 9 mm m 2 W cum w Viuig Muir iui l39lLt The information from the NOD file is automatically inserted into the correct rows Power Calculator uses the clock names from the design as shown in Figure 1 12 1112 Power Estimation and Management Lattice Semiconductor for MachXO Devices Figure 1112 Power Calculator Main Window Resource Utilization Picked up from the NOD File Drum mu Smk Power Calculator Open Existing Project The Power Calculator Start Project window also allows users to open an existing project Select the option Open Existing Project browse to the pep project file and click ContinueThis opens the existing project in similar win dows as discussed above This is shown in Figure 1113 1113 Power Estimation and Management Lattice Semiconductor f r MachXO Devices Figure 1113 Opening an Existing Project in the Power Calculator 32 m m win quot39 w 4 l man a mum g wwwmmum uquot E wwwcm m m amp 9quot am ww Power Calculator Importing Simulation File VCD to the Project Us rs can import the post simulation VCD file into the power calculator project to estimate their designs activity factors Select Open Simulation File option under the File menu browse to theVCD file location and s t Open All AF and toggle rate fields are populated with the information from this file This is shown in Figure 11 1114 Power Estimation and Management Lattice Semiconductor for MachXO Devices Figure 1114 Importing Simulation File in the Existing Project in the Power Calculator ll u 1 as Edt Nola NW ompvmtm PM W Drum mmmz Pun amz MX054nEv3nnJ5 Ll mm w v Ammammptmumzsn c commcumin ng JuhnlonTempuamrezszQQ m Emumm mlmued tsunami mmm mmm mmm rammed Mu my mm Dtslun I r g m Vtwbdil v 25v vmsv 2 m an an n 39u a V yummy umquot Rem Ll smlmp CI verihgrhievavchczdruasmn m r AF m manna ma acme mm mumI21 mm H u M it mm mum new my nacmient MM Dzqu mum mama ly gm ma W m mama VEMWWWMM v gm nalnFlamz r Se vpePanel 7 END 4 sum 1va Power Calculator Importing Trace Report File TWR to the Project Users can import the post Trace TWFl file into the Power Calculator project to estimate their designs activity fac tors Select Open Trace Report File option under the File menu browse to the TWFl file location and select Open All Freq MHZ fields are populated with the information from this file This is shown in Figure 1115 1115 Power Estimation and Management f r Lattice Semiconductor MachXO Devices Figure 1 115 Importing Trace Report File in the Existing Project in the Power Calculator a 5 lac w Help NW opawm ztm campusmm Dull mmxosdni mum ltMxomzmmm Ll OMSlMtWiem mm m mbknt39l cmpxmurern c mm m inunan mlmued Emma Save my mm Dtslyn r Vm Vt wxiw mm m In mm 5 3 if Q VullnaneiarchlcaLdzsrgw d mm mm a Mawmem H u n in Beam MyDammen mm 9quot may l nmmm mcuwv 9m mainframer bellypeuan itulatemmtieaun nalnFlamz r Se vpei anel 7 END El was was Activity Factor and Toggle Rate Activity Factor o or AF o is defined as the percentage of frequency or time that a signal is active or toggling of the output Most of the resources associated with a clock domain are running or toggling at some percentage of the frequency at which the clock is running Users are required to provide this value as a percentage under the AF o column in the Power Calculator tool Another term used for lOs is the lO Toggle Rate or the lO Toggle Frequency The AF o is applicable to the PFU routing and memory read write ports etcThe activity of lOs is determined by the signals provided by the user in the case of inputs or as an output of the design in the case of outputs So the rates at which lOs toggle defines their activity TheToggle Flate orTFl in MHZ of the output is defined as Toggle Flate MHz 12 fMAX AF o Users are required to provide theTFl MHZ value for the lO instead of providing the frequency and AF o in case of other resources The AF can be calculated for each routing resource output or PFU however it involves long calcu lations The general recommendation of a design occupying roughly 30 to 70 of the device is that the AF o used can be between 15 to 25 This is an average value that can be seen most of the design The accurate value of an AF depends upon clock frequency stimulus to the design and the final output Ambient and Junction Temperature and Airflow A common method of characterizing a packaged device s thermal performance is with Thermal Resistance 8 For a semiconductor device thermal resistance indicates the steady state temperature rise of the diejunction above a given reference for each watt of power heat dissipated at the die surface lts units are CW 1116 Power Estimation and Management Lattice Semiconductor for MachXO Devices The most common examples are GJA Thermal Resistance JunctiontoAmbient in oCW and 6J0 Thermal Resis tance JunctiontoCase also in oCW Another factor is 6J3 Thermal Resistance JunctiontoBoard in oCW Knowing the reference ie ambient case or board temperature the power and the relevant 6 value the junction temp can be calculated as per the following equations TJTA6JAP 1 TJTC6JCP 2 TJTB6JBP Where TJ TA TC and TB are the junction ambient case or package and board temperatures in 0C respectively P is the total power dissipation of the device GJA is commonly used with natural and forced convection aircooled systems 6J0 is useful when the package has a high conductivity case mounted directly to a PCB or heatsink And 6J3 applies when the board temp adjacent to the package is known Power Calculator utilizes the ambient temperature C to calculate the junction temperature C based on the GJA for the targeted device per equation 1 above Users can also provide the airflow values in LFM to get a more accurate value of the junction temperature Managing Power Consumption One of the most critical design factors today is reducing system power consumption especially for modern hand held devices and electronics There are several design techniques that designers can use to significantly reduce overall system power consumption Some of these include 1 Reducing operating voltage 2 Operating within the specified package temperature limitations 3 Using optimum clock frequency reduces power consumption as the dynamic power is directly proportional to the frequency of operation Designers must determine if a portion of their design can be clocked at a lower rate which will reduce power 4 Reducing the span of the design across the device A more closely placed design utilizes fewer routing resources for less power consumption 5 Reducing the voltage swing of the lOs where possible 6 Using optimum encoding where possible For example a 16bit binary counter has on average only 12 Activity Factor and a 7bit binary counter has an average of 28 Activity Factor On the other hand a 7bit Linear Feedback Shift Register could toggle as much as 50 Activity Factor which causes higher power consumption A gray code counter where only one bit changes at each clock edge will use the least amount of power as the Activity Factor would be less than 10 7 Minimize the operating temperature by the following methods a Use packages that can better dissipate heat For example packages with lower thermal impedance b Place heat sinks and thermal planes around the device on the PCB c Better airflow techniques using mechanical airflow guides and fans both system fans and device mounted fans Power Calculator Assumptions The following are the assumptions made in the Power Calculator 1 The Power Calculator tool is based on equations with constants based on room temperature of 25 C 2 The user can define the AmbientTemperature TA for device Junction Temperature TJ calculation based on the power estimation TJ is calculated from userentered TA and power calculation of typical room tem perature 1117 Power Estimation and Management Lattice Semiconductor for MachXO Devices 3 The lO power consumption is based on output loading of 5pF Users have ability to change this capacitive loading The current version of the Power Calculator allows users to get an estimate of the power dissipation and the current for each type of power supplies that are VCC VCCIO VCCJ and VCCAUX 5 The nominal VCC is used by default to calculate power consumption Users can choose a lower or higher VCC from a list of available values The current versions also allow users to enter an airflow in Linear Feet per Minute LFM along with the heat sink option to calculate the junction temperature The default value of the lO types for the devices is LVCM08126mA The Activity Factor is defined as the toggle rate of the registered output For example assuming that the input of a flipflop is changing at every clock cycle 100 AF of a flipflop running at 100MHz is SOMHZ 4s 5 0 Technical Support Assistance Hotline 1800LATTICE North America 15032688001 Outside North America email techsupportlatticesemicom Internet wwwlatticesemicom Revision History Date Version Change Summary July 2005 010 Initial release September 2007 011 Document title changed to Power Estimation and Management for MachXO Devices 1118 MachXO JTAG Programming and nugg39pggggfggbr Configuration User s Guide February 2007 Technical Note TN1086 Introduction The Lattice MachXOT39V39 is a reconfigurable programmable logic deviceThe MachXO uses SRAM memory cells to allow configuring the device to any required functionality The MachXO also provides nonvolatile Flash memory cells to store the configuration data The data retrieved from the Flash memory rapidly loads the SRAM memory at powerup or at the request of the user This combination of memory types provides several unique programming and operational capabilities not found in antifuse or SRAMonly based FPGA devices Some of the capabilities pro vided by the MachXO Instanton SRAM loading at powerup Bitstream security Since there is no external PROM there is no access to the bitstream used to program the MachXO device Instant reconfiguration to a known good state from the Flash memory ie recovery from soft upset events Reprogramming of the Flash while in normal SRAM operation This technical note describes how to take advantage of these unique capabilities Programming Overview The Lattice MachXO contains two types of memory SRAM and Flash refer to Figure 121 SRAM contains the active configuration essentially the fuses that define the circuit connections Flash provides an internal storage space for the configuration data The SRAM can be configured in two ways by using IEEE 1532 mode via the IEEE 11491 compliant ispJTAGT39V39 port or from data stored in the onchip Flash memory While writing SRAM via the ispJTAG port the state of the FPGA s lOs is determined by the BSCAN registers The state of each BSCAN boundary scan register can be determined by the user available options are high low tristate default or current value also called leave alone The SRAM may be read without disturbing the operation of the device This is called transparent or background readback Care must be exercised when reading EBFl or distributed RAM as it is possible to cause conflicts with accesses from the user design causing possible data corruption It is recommended that readwrite enables to the EBFl or distributed RAM be turned off any time these resources are being read via the JTAG port The onchip Flash can also be programmed using IEEE 1532 mode via the IEEE 11491 compliant ispJTAG port If the SRAM portion of the device is blank then the Flash will be programmed using direct mode In direct mode the state of the device s lOs is determined by the BSCAN registers The state of each BSCAN register can be deter mined by the user available options are high low tristate default or current value If the SRAM portion of the device is not blank then the Flash will be r g 39 in 39 39g 39 r mode Both SRAM and Flash memory in the Lattice MachXO have multiple security fuses to prevent unauthorized read back of the configuration data Once set the only way to clear these security bits is to erase the memory space A secured device will read out all zeros Note that very early production releases of the MachXO1200 and MachX02280 marked with a 4W in the part number field did not support writes to or reads from the SRAM fabric using JTAG These parts do however sup port all other programming modes 2007 Lattice Semiconductor Corp All Lattice trademarks registered trademarks patents and disclaimers are as listed at wwwlatticesemi comlegal All other brand or product names are trademarks or registered trademarks of their p b 39d T r r quotIquot 391 Hang m uu wwwlatticesemicom 121 tn1086013 MachXO JTAG Programming and Lattice Semiconductor Configuration User s Guide Figure 12 1 Programming Block Diagram JTAG 1532 Mode Coniigure in milliseconds Program in seconds Flash Memory Space Memory Space Coniigure in microseconds Memory Space ispJTAG The ispJTAG pins are standard IEEE 11491 TAP Test Access Port pinsThe ispJTAG pins are dedicated pins and are always accessible when the Lattice MachXO device is powered up Table 12 1 ispJTAG Pins Definition a TDI and the associated VCCIO A pulldown of47K is recommended on TCK TDO The Test Data Output pin is used to shift serial test instructions and data out of the MachXOTDO is clocked out on the falling edge otTCK When TDO is not being driven by the internal circuitry the pin will be in a high impedance state tristate An internal pullup resistor on the TDO pin is providedThe internal resistor is pulled up to the asso ciated VCCIQ TDI The Test Data Input pin is used to shift serial test instructions and data into the MachXO TDI is clocked into the device on the rising edge of TCK An internal pullup resistor on the TDI pin is provided The internal resistor is pulled up to the associated VCCIQ TMS The Test Mode Select pin controls test operations on the TAP controller Oh the rising edge of TCK depending on the state otTMS a transition will be made in the TAP controller state machine An internal pullup resistor on the TMS pin is providedThe internal resistor is pulled up to the associated VCCIQ MachXO JTAG Programming and Lattice Semiconductor Configuration User s Guide TCK The test clock pin provides the clock to run the TAP controller which loads and unloads the data and instruction registersTCK can be stopped in either the high or low state and can be clocked at speeds up to the frequency indi cated in the device data sheet The TCK pin does not have a pullup A pulldown on the PCB of 47 K is recom mended to avoid inadvertent clocking of the TAP controller as VCC ramps up Vcc Supply for JTAG VCC for the internal JTAG logic is supplied by the associated bank s VCCIQ To determine which bank contains the JTAG pins please refer to the Lattice MachXO Family Data Sheet Valid voltage levels are 33V 25V 18V 15V and 12V but check that the desired voltage is compatible with the ispDOWNLOAD Cable connected to the down load header Figure 122 Download Header to MachXO Wiring X 0 MachXO TDI TDI 7V0 VCCIO OOmemwa A l E 1 47K lt7 Note Place a decoupling capacitor close to the connectors VCCIO pin Any standard ceramic capacitor value may be used for example 01 pF 001 pF etc Download Cable Pinout Standard pinouts for the 1X10 1X8 and 2X5 download headers are shown in the ispDOWNLOAD Cable Data Sheet All new ispDOWNLOAD Cables have uncommitted flywire connections so they can be attached to any of the header styles Refer to the ispDOWNLOAD Cable data sheet for additional details BSDL Files BSDL files for this device can be found on the Lattice Semiconductor web siteThe boundary scan ring covers all of the lO pins Device Wake Up When configuration is complete the SRAM has been loaded the device will wake up in a predictable fashionThe wake up sequence is driven by and is synchronous to an internal clock Software Options Preference Options Preference options are set by opening the Preference Editor within the ispLEVEFl design software and selecting the global options tab MachXO JTAG Programming and Lattice Semiconductor Configuration User s Guide Table 122 Preference Options for the MachXO Security When CONFIGSECUFIE is set to ON the onchip security fuses will be set and no readback of the general con tents SFIAM or Flash will be supported through the ispJTAG portThe ispJTAG DevicelD area including the User code and the device Status Register are readable and not considered securable Default is OFF Usercode Usercode is a user defined 32bit register sometimes called the UES User Electronic Signature The Usercode can be thought of as a user notepad The Usercode is supported as part of the IEEE 11491 definition Lattice incorporated the Usercode to store such design and manufacturing data as the manufacturer39s ID program ming date programmer make pattern code checksum PCB location revision number and product flow The intent is to assist users with the complex chore of record maintenance and product flow control In practice the Usercode can be used for any of a number of ID functions The Usercode can be easily edited using the User codeUES Editor in ispVM by clicking on ispTools gt ispVM Editors Note that the Usercode is included in the file transmission checksum but not the fuse checksum Configuring SRAM or Programming Flash The final step in the design process is to load the JEDEC file created by ispLEVEFt into the Lattice MachXO The JEDEC file can be used to configure the SFIAM or program the Flash Simply connect a Lattice download cable to the ispJTAG connector that is wired to your Lattice MachXO and apply power to the FPGA Then start ispVM and follow these steps 1 Click on File gt New 3 Click on Edit gt Add New Device JD Select the MachXO device Browse to the JEDEC file created in ispLEVEFl and then select either SFIAM or Flash via the Device Access Options drop down box b Click OKYou are now ready to program the MachXO by clicking on the green GO button on the toolbar U39I For other options such as Read and Save Verify ID etc return to Device Information by double clicking on the MachXO in Device List and use the Operation dropdown box If you need to create an SVF Serial Vector File a file to allow programming from yourATE Automated Test Equip ment or a file to support VME ispVM Embedded simply perform steps 1 2 and 3 above but click on SVF ATE or VME instead of GO More information on ispVM and ispVM Embedded can be found by starting ispVM and clicking on Help Here you will find several tutorials as well as the help facility Technical Support Assistance Hotline 1800LATTICE North America 15032688001 Outside North America email techsupportIatticesemicom Internet wwwlatticesemicom MachXO JTAG Programming and Lattice Semiconductor Configuration User s Guide Revision History Date Version Change Summary Previous releases February 2007 013 Updated Download Cable Pinout section HDL Synthesis Coding Guidelines for quotnuggrpgggggggtor Lattice Semiconductor FPGAs October 2005 Technical Note TN1008 Introduction Coding style plays an important role in utilizing FPGA resources Although many popular synthesis tools have sig nificantly improved optimization algorithms for FPGAs it still is the responsibility of the user to generate meaningful and efficient HDL code to guide their synthesis tools to achieve the best result for a specific architecture This appli cation note is intended to help designers establish useful HDL coding styles for Lattice Semiconductor FPGA devices It includes VHDL and Verilog design guidelines for both novice and experienced users The application note is divided into two sections The general coding styles for FPGAs section provides an over view for effective FPGA designs The following topics are discussed in detail Hierarchical Coding Design Partitioning Encoding Methodologies for State Machines Coding Styles for Finite State Machines FSM Using Pipelines Comparing IF Statements and CASE Statements Avoiding Nonintentional Latches The HDL Design with Lattice Semiconductor FPGA Devices section covers specific coding techniques and exam ples Using the Lattice Semiconductor FPGA Synthesis Library Implementation of Multiplexers Creating Clock Dividers Register Control Signals CE LSR GSR Using PIC Features Implementation of Memories Preventing Logic Replication and Fanout Comparing Synthesis Results and Place and Route Results General Coding Styles for FPGA The following recommendations for common HDL coding styles will help users generate robust and reliable FPGA designs Hierarchical Coding HDL designs can either be synthesized as a flat module or as many small hierarchical modules Each methodology has its advantages and disadvantages Since designs in smaller blocks are easier to keep track of it is preferred to apply hierarchical structure to large and complex FPGA designs Hierarchical coding methodology allows a group of engineers to work on one design at the same time It speeds up design compilation makes changing the imple mentation of key blocks easier and reduces the design period by allowing the reuse of design modules for current and future designs In addition it produces designs that are easier to understand However if the design mapping into the FPGA is not optimal across hierarchical boundaries it will lead to lower device utilization and design perfor mance This disadvantage can be overcome with careful design considerations when choosing the design hierar chy Here are some tips for building hierarchical structures The top level should only contain instantiation statements to call all major blocks Any IO instantiations should be at the top level Any signals going into or out of the devices should be declared as input output or bidirectional pins at the top level wwwlatticesemicom 131 tn1008021 HDL Synthesis Coding Guidelines Lattice Semiconductor for Lattice Semiconductor FPGAs Memory blocks should be kept separate from other code Design Partitioning By effectively partitioning the design a designer can reduce overall run time and improve synthesis results Here are some recommendations for design partitioning Maintain Synchronous Subblocks by Registering All Outputs It is suggested to arrange the design boundary such that the outputs in each block are registered Registering out puts helps the synthesis tool to consider the implementation of the combinatorial logic and registers into the same logic block Registering outputs also makes the application of timing constraints easier since it eliminates possible problems with logic optimization across design boundaries Single clock is recommended for each synchronous block because it significantly reduces the timing consideration in the block It leaves the adjustment of the clock relationships of the whole design at the top level of the hierarchy Figure 131 shows an example of synchronous blocks with registered outputs Figure 13 1 Synchronous Blocks with Registered Outputs B C as 9 Keep Related LogicTogether in the Same Block Keeping related logic and sharable resources in the same block allows the sharing of common combinatorial terms and arithmetic functions within the block It also allows the synthesis tools to optimize the entire critical path in a single operation Since synthesis tools can only effectively handle optimization of certain amounts of logic optimi zation of critical paths pending across the boundaries may not be optimal Figure 132 shows an example of merg ing sharable resource in the same block Figure 132 Merge Sharable Resource in the Same Block B C 93 Separate Logic with Different Optimization Goals Separating critical paths from noncritical paths may achieve efficient synthesis results At the beginning of the project one should consider the design in terms of performance requirements and resource requirements If there 1 32 HDL Synthesis Coding Guidelines Lattice Semiconductor for Lattice Semiconductor FPGAs are two portions of a block one that needs to be optimized for area and a second that needs to be optimized for speed they should be separated into two blocks By doing this different optimization strategies for each module can be applied without being limited by one another Keep Logic with the Same Relaxation Constraints in the Same Block When a portion of the design does not require high performance this portion can be applied with relaxed timing constraints such as multicycle to achieve high utilization of device area Relaxation constraints help to reduce overall run time They can also help to efficiently save resources which can be used on critical paths Figure 133 shows an example of grouping logic with the same relaxation constraint in one block Figure 133 Logic with the Same Relaxation Constraint A B A FF1 FF2 FF1 FF2 F b F Keep Instantiated Code in Separate Blocks It is recommended that the RAM block in the hierarchy be left in a separate block Figure 134This allows for easy swapping between the RAM behavioral code for simulation and the code for technology instantiation In addition this coding style facilitates the integration of the ispLEVEFl lPexpressT39V39 tool into the synthesis process Figure 134 Separate RAM Black Top RAM Controller RegisterFile State Machine Counter Keep the Number FPGA Gates at 30 to 80 PFU Per Block This range varies based on the computer configuration time required to complete each optimization run and the targeted FPGA routing resources Although a smaller block methodology allows more control it may not produce the most efficient design since it does not provide the synthesis tool enough logic to apply Resource Sharing algorithms On the other hand having a large number of gates per block gives the synthesis tool too much to work on and causes changes that affect more logic than necessary in an incremental or multiblock design flow State Encoding Methodologies for State Machines There are several ways to encode a state machine including binary encoding graycode encoding and onehot encoding State machines with binary or graycode encoded states have minimal numbers of flipflops and wide combinatorial functions which are typically favored for CPLD architectures However most FPGAs have many flip flops and relatively narrow combinatorial function generators Binary or graycode encoding schemes can result in inefficient implementation in terms of speed and density for FPGAs On the other hand onehot encoded state machine represents each state with one flipflop As a result it decreases the width of combinatorial logic which matches well with FPGA architectures For large and complex state machines onehot encoding usually is the preferable method for FPGA architectures For small state machines binary encoding or graycode encoding may be more efficient There are many ways to ensure the state machine encoding scheme fora design One can hard code the states in the source code by specifying a numerical value for each state This approach ensures the correct encoding of the state machine but is more restrictive in the coding style The enumerated coding style leaves the flexibility of state machine encoding to the synthesis tools Most synthesis tools allow users to define encoding styles either through 1 33 HDL Synthesis Coding Guidelines Lattice Semiconductor for Lattice Semiconductor FPGAs attributes in the source code or through the tools Graphical User Interface GUI Each synthesis tool has its own synthesis attributes and syntax for choosing the encoding styles Refer to the synthesis tools documentation for details about attributes syntax and values The following syntax defines an enumeration type in VHDL type typename is statelnamestate2name stateNname Here is aVHDL example of enumeration states type STATETYPE is SOSlSZ s3s4 signal CURRENTSTATE NEXTSTATE STATETYPE The following are examples of Synplify and LeonardoSpectrum VHDL synthesis attributes Synpli attribute synencoding string attribute synencoding of ltsignalnamegt type is quotvalue quot The synencoding attribute has 4 values sequential onehot gray and safe LeonardoSpectrum Declare TYPEENCODINGSTYLE attribute Not needed if the exemplar1164 package is used type encodingstyle is BINARY ONEHOT GRAY RANDOM AUTO attribute TYPEENCODINGSTYLE encodingstyle attribute TYPEENCODINGSTYLE of lttypenamegt type is ONEHOT In Verilog one must provide explicit state values for statesThis can be done by using the bit pattern eg 339b001 or by defining a parameter and using it as the case item The latter method is preferable The following is an exam ple using parameter for state values Parameter statel 239hl state2 239h2 currentstate state2 setting current state to 239h2 The attributes in the source code override the default encoding style assigned during synthesis Since Verilog does not have predefined attributes for synthesis attributes are usually attached to the appropriate objects in the source code as commentsThe attributes and theirvalues are case sensitive and usually appear in lower caseThe follow ing examples use attributes in Verilog source code to specify state machine encoding style Synpli Reg20 state synthesis synencoding quotvaluequot The synencoding attribute has 4 values sequential onehot gray and safe In LeonardoSpectrum it is recommended to set the state machine variable to an enumeration type with enum pragma Once this is set in the source code encoding schemes can be selected in the LeonardoSpectrum GUI LeonardoSpectrum Parameter exemplar enum lttypenamegt s0 0 s1 1 s2 2 s3 3 S4 4 Reg 20 exemplar enum lttypenamegt presentstate neXtstate In general synthesis tools will select the optimal encoding style that takes into account the target device architec ture and size of the decode logic One can always apply synthesis attributes to override the default encoding style if necessary HDL Synthesis Coding Guidelines Lattice Semiconductor for Lattice Semiconductor FPGAs Coding Styles for FSM A finite state machine FSM is a hardware component that advances from the current state to the next state at the clock edge As mentioned in the Encoding Methodologies for State Machines section the preferable scheme for FPGA architectures is onehot encoding This section discusses some common issues encountered when con structing state machines such as initialization and state coverage and special case statements in Verilog General State Machine Description Generally there are two approaches to describe a state machine One is to use one processblock to handle both state transitions and state outputsThe other is to separate the state transition and the state outputs into two differ ent processblocks The latter approach is more straightforward because it separates the synchronous state regis ters from the decoding logic used in the computation of the next state and the outputs This will make the code easier to read and modify and makes the documentation more efficient It the outputs of the state machine are combinatorial signals the second approach is almost always necessary because it will prevent the accidental reg istering of the state machine outputs The following examples describe a simple state machine in VHDL and Verilog In the VHDL example a sequential process is separated from the combinatorial process In Verilog code two always blocks are used to describe the state machine in a similar way VHDL Example for State Machine Verilog Example for State Machine archltecture lattlceifpga of dramirefresh ls parameter so 0 s1 1 s2 2 s3 3 s4 4 type stateityp ls so s1 s2 s3 s4 slgnal presentistate nextistate stateityp reg 20 presentistate nextistate begln reg ras cas ready process to update the present state reglsters process clk reset always block to update the present state begln always posedge clk or posedge reset lf reset39139 then egln presentistate lt so lf reset presentistate so elslf clk39event and clkl then else presentistate nextistate presentistate lt nextistate end end lf end process registers always block to calculate the next state amp outputs always presentistate or refresh or cs process to calculate the next state a output begin transltlons process presentistate refresh cs nextistate so begln ras lbx cas lbx ready l39bX r cas lt 39039 ready lt 39039 case presentistate tate ls so lf refresh begln as lt 39 039 7 case present when 50 s37 b cas lbo ready lbo ras lt7 cas lt 1 ready lt l lf refresh 39139 then n xtistate lt s3 end elslf cs then nextistate lt sl else lf cs begl else nextistate lt so nextistate sl ras lbo cas lbl ready lbo end l end when s1 gt else begln ras lt 39039 cas 1 ready lt 39o39 nextistate so ras lb1cas lbl ready lbl nextistate lt s2 end when s2 gt s1 begln ras 39 cas lt o39 rea lt 39039 nextistate s2 ras lbo cas lbo ready lbo lf cs 039 then nextistate lt so end else nextistate lt s2 s2 lf cs begln end lf nextistate so ras lbl cas lbl ready lbl when s3 gt end ras lt 1 cas lt 39039 ready lt 39039 else begin nextistate lt s4 nextistate s2 ras lbo cas 139bEI ready l39bEI when s4 gt end ras lt 39039 cas lt 39039 ready lt o s3 begln n xtistate lt sEI nextistate s4 ras lbl cas lbo ready lbo when others gt end ras lt 39u39 cas lt 39u39 ready lt 39u39 s4 begln nextistate lt sEI nextistate so ras lbo cas lbo ready lbo d case en end process transltlons endcase end HDL Synthesis Coding Guidelines Lattice Semiconductor for Lattice Semiconductor FPGAs Initialization and Default State A state machine must be initialized to a valid state after powerup This can be done at the device level during power up or by including a reset operation to bring it to a known state For all Lattice Semiconductor FPGA devices the Global SetReset GSFl is pulsed at powerup regardless of the function defined in the design source code In the above example an asynchronous reset can be used to bring the state machine to a valid initialization state In the same manner a state machine should have a default state to ensure the state machine will not go into an invalid state if not all the possible combinations are clearly defined in the design source code VHDL and Verilog have different syntax for default state declaration In VHDL if a CASE statement is used to construct a state machine When Others should be used as the last statement before the end of the statement If an lFTHEN ELSE statement is used Else should be the last assignment for the state machine In Verilog use default as the last assignment fora CASE statement and use Else for the lFTHENELSE statement When Others in VHDL Default Clause in Verilog archltecture lattlceitpga of FSMl ls Deflne state labels expllcltly type s ateityp ls deflt ldle read write parameter deflt239bxx slgnal nextistate stateityp parameter ldle 239b00 begln parameter read 239b01 processclk rst parameter wrlte239b10 begln 1f rst39139 then reg 10 nextistate nextistate lt ldle doul lt 39039 reg dout elslf elkevent and clk39139 then case nextistate ls always posedge clk or posedge rst dle gt if rst begln nextistate lt read dout lt d1n07 n state lt ldle when read gt dout lt 139b0 nextistate lt wrlte dout lt d1n17 en when wrlte gt else begln nextistate lt ldle dout lt d1n27 casenextistate 1d when others gt 1e begln nextistate lt deflt dout lt 39039 dout lt d1n07 nextistate lt read end case end end 1 read begln end process dout lt d1n17 nextistate lt wrlte end wrlte begln dout lt d1n27 nextistate lt ldle end default begln dout lt 139b0 nextistate lt deflt end Fu Case and Parallel Case Specification in Verilo Verilog has additional attributes to define the default states without writing it specifically in the code One can use fullcase to achieve the same performance as default The following examples show the equivalent representa tions of the same code in Synplify LeonardoSpectrum allows users to apply Verilogspecific options in the GUI set tings case currentistate synthesis fullicase case currentistate 2 b00 nextistate lt 2 b01 2 b00 nextistate lt 2 b01 2 b01 next state lt 2 b11 2 b01 next state lt 2 b11 2 b11 nextstate lt 2 b00 2 b11 nextistate lt 2 b00 default nextistate lt 213x Parallelicase makes sure that all the statements in a case statement are mutually exclusive It is used to inform the synthesis tools that only one case can be true at a timeThe syntax for this attribute in Synplify is as follows synthesis parallelcase Using Pipelines in the Designs Pipelining can improve design performance by restructuring along data path with several levels of logic and break ing it up over multiple clock cycles This method allows a faster clock cycle by relaxing the clocktooutput and setup time requirements between the registers It is usually an advantageous structure for creating faster data paths in registerrich FPGA devices Knowledge of each FPGA architecture helps in planning pipelines at the 1 36 HDL Synthesis Coding Guidelines Lattice Semiconductor for Lattice Semiconductor FPGAs beginning of the design cycle When the pipelining technique is applied special care must be taken for the rest of the design to account for the additional data path latency The following illustrates the same data path before Figure 135 and after pipelining Figure 136 Figure 135 Before Pipelining 4r FF1 Comb Comb Comb FF1 Function Function Function b b Slow Clock Figure 136 After Pipelining FF1 V Before pipelining the clock speed is determined by the clocktoout time of the source register the logic delay through four levels of combinatorial logic the associated routing delays and the setup time of the destination regis ter After pipelining is applied the clock speed is significantly improved by reducing the delay of four logic levels to one logic level and the associated routing delays even though the rest of the timing requirements remain the same It is recommended to check the Place and Route timing report to ensure that the pipelined design gives the desired performance Fast C lock Comparing lF statement and CASE statement CASE and lFTHENELSE statements are common for sequential logic in HDL designsThe lFTHENELSE state ment generally generates priorityencoded logic whereas the CASE statement implements balanced logic An lF THENELSE statement can contain a set of different expressions while a Case statement is evaluated against a common controlling expression Both statements will give the same functional implementation if the decode condi tions are mutually exclusive as shown in the following VHDL codes Case Statement 7 mutually exclusive conditions IfThenElse i mutually exclusive conditions process s x y 2 process x y z begln begin 01 lt 39039 01 lt 39039 02 lt 39039 02 lt 39039 03 lt 39039 03 lt 39039 case s is if s quot00 then 01 lt x when quot00quot gt 01 lt x elsif s quot01 then 02 lt y when quot01quot gt 02 lt y elsif s quot10 then 03 lt 2 when quot10quot gt 03 lt 2 end if end case end process end process 1 37 HDL Synthesis Coding Guidelines Lattice Semiconductor for Lattice Semiconductor FPGAs However the use of lfThenElse construct could be a key pitfall to make the design more complex than necessary because extra logic are needed to build a priority tree Consider the following examples A IfThenElese Statement Complex 03 Equations B IfThenElse Statement Simpli ed 03 Equation processs1 s s3 x y 2 process s1 s2 begin begin 01 lt 1039 01 lt 39039 02 lt 1039 02 lt 39039 03 lt 39039 03 lt 39039 if s1 1 then if s1 1 then 01 x 01 lt elsif s2 1 then end if 02 y if s2 1 then elsif s3 1 then 02 lt y 03 lt 2 end if end if if s3 lt 391 then end process 03 lt 2 end if end process If the decode conditions are not mutually exclusive lFTHENELSE construct will cause the last output to be dependent on all the control signalsThe equation for 03 output in example A is 03 lt 2 and s3 and not 51 and 52 If the same code can be written as in example B most of the synthesis tools will remove the priority tree and decode the output as 03 lt 2 and 3 This reduces the logic requirement for the state machine decoder If each output is indeed dependent of all of the inputs it is better to use a CASE statement since CASE statements provide equal branches for each output Avoiding Nonintentional Latches Synthesis tools infer latches from incomplete conditional expressions such as an lFTHENELSE statements with out an Else clause To avoid nonintentional latches one should specify all conditions explicitly or specify a default assignment Otherwise latches will be inserted into the resulting RTL code requiring additional resources in the device or introducing combinatorial feedback loops that create asynchronous timing problems Nonintentional latches can be avoided by using clocked registers or by employing any of the following coding techniques Assigning a default value at the beginning of a process Assigning outputs for all input conditions Using else when others as the final clause Another way to avoid nonintentional latches is to check the synthesis tool outputs Most of the synthesis tools give warnings whenever there are latches in the design Checking the warning list after synthesis will save a tremen dous amount of effort in trying to determine why a design is so large later in the Place and Route stage HDL Design with Lattice Semiconductor FPGA Devices The following section discusses the HDL coding techniques utilizing specific Lattice Semiconductor FPGA system features This kind of architecturespecific coding style will further improve resource utilization and enhance the performance of designs Lattice Semiconductor FPGA Synthesis Library The Lattice Semiconductor FPGA Synthesis Library includes a number of library elements to perform specific logic functionsThese library elements are optimized for Lattice Semiconductor FPGAs and have high performance and utilization The following are the classifications of the library elements in the Lattice Semiconductor FPGA Synthe 1 38 HDL Synthesis Coding Guidelines Lattice Semiconductor for Lattice Semiconductor FPGAs sis Library The definitions of these library elements can be found in the Reference Manuals section of the ispLEVEFt online help system Logic gates and LUTs Comparators adders subtractors Counters Flipflops and latches Memory 4Especific memory block FlAM function Multiplexors Multipliers All lO cells including lO flipflops PIC cells Special cells including PLL GSFl boundary scan etc FPSC elements lPepxress a parameterized module complier optimized for Lattice FPGA devices is available for more complex logic functions lPeXpress supports generation of library elements with a number of different options such as PLLs and creates parameterized logic functions such as PFU and EBFl memory multipliers adders subtractors and counters lPeXpress accepts options that specify parameters for parameterized modules such as data path mod ules and memory modules and produces a circuit description with Lattice Semiconductor FPGA library elements Output from lPeXpress can be written in EDIF VHDL or Verilog In order to use synthesis tools to utilize the Lattice FPGA architectural features it is strongly recommended to use lPeXpress to generate modules for source code instantiation The following are examples of Lattice Semiconductor FPGA modules supported by lPeXpress PLL Memory implemented in PFU Synchronous singleport FlAM synchronous dualport FlAM synchronous FlOM synchronous FIFO Memory implemented with EBFl Quadport Block FlAM DualPort Block FlAM SinglePort Block FlAM FlOM FIFO Other EBFl based Functions Multiplier CAM PFU based functions Multiplier adder subtractor addersubtractor linear feedback shifter counter MPlSystem Bus lPeXpress is especially efficient when generating high pin count modules as it saves time in manually cascading small library elements from the synthesis library Detailed information about lPeXpress and its user guide can be found in the ispLEVEFt help system HDL Synthesis Coding Guidelines Lattice Semiconductor for Lattice Semiconductor FPGAs Implementing Multiplexers The flexible configurations of LUTs can realize any 4 5 or 6input logic function like 2to1 3to1 or 4to1 multi plexers Larger multiplexers can be efficiently created by programming multiple 4input LUTs Synthesis tools camn automatically infer Lattice FPGA optimized multiplexer library elements based on the behavioral description in the HDL source code This provides the flexibility to the Mapper and Place and Route tools to configure the LUT mode and connections in the most optimum fashion 161 MUX process se1 din begin 1 selquot quot then muxout elslf Se then ut elslf sel then muxout elslf sel then muxout lslf Se the muxout elslf sel then muxout elslf sel then muxout lslf self the muxout elslf sel then muxout elslf sel then muxout lslf Se the muxout elslf sel then muxout elslf self then muxout lslf sel the muxout elslf sel hen muxou elslf Se then muxout else end 1 end process Clock Dividers There are two ways to implement clock dividers in Lattice Semiconductor FPGA devicesThe first is to cascade the registers with asynchronous clocks The register output feeds the clock pin of the next register Figure 137 Since the clock number in each PFU is limited to two any clock divider with more than two bits will require multiple PFU implementations As a result the asynchronous daisy chaining implementation of clock divider will be slower due to the interPLO routing delays This kind of delays is usually ambiguous and inconsistent because of the nature of FPGA routing structures Figure 137 Daisy Chaining of Flipflops 1310 HDL Synthesis Coding Guidelines Lattice Semiconductor for Lattice Semiconductor FPGAs The following are the HDL representations of the design in Figure 137 VHDL Example of Daisy Chaining FF Verilog Example of Daisy Chaining FF 1st FF to dlvlde Clock 1n half always posedge CLK or posedge RST CLKiDIVI processCLK RST begln begln f RS 1 RST39139 then clkl 139b0 clkl 39039 else elslf CLK39evenl and CLK39139 then clkl lclkl clkl lt cl 1 end end 1 end process CLKiDIVI always posedge clkl or posedge RST be 1n 2nd FF to de clock 1n half 1f RST CLKiDIVZ processclk1 RST clk2 139b0 begln else 1 RST39139 then clk2 lclk2 clk2 397 end elslf clkl39evenl and clk11 then clk2 lt not clk27 end 1f end process CLKiDIVZ The preferable way is to fully employ the PLC39s natural Ripplemode A single PFU can support up to 8bit ripple functions with fast carry logic Figure 138 is an example of 4bit counter in PLC Ripple Mode In Lattice Semicon ductor FPGA architectures an internal generated clock can get on the clock spine for small skew clock distribution further enhancing the performance of the clock divider Figure 138 Use PLC Ripple Mode 4TB gt DIVBY2 LUT in gt DIVBY4 Ripple Mode 4Bit Counter 4D gt DIVBYB TD L mm Here are the HDL representations of the design in Figure 138 VHDL quotRippleModequot Clock Divider Verilog quotRippleModequot Clock Divider posedge CLK or posedge RST CouNTA processCLK RST begln be 1n 1f RST 1f RST39139 then cnt 439b0 cnt lt othersgt39039 else elslf CLK39eVenl and CLK39139 then cnt cnt 139b1 c l l 17 end end 1f end process CouNTA asslgn DIVBY4 cnt1 asslgn DIVBY16 cnt3 DIVBY4 lt cnl1 DIVBY16 lt cnt3 1311 HDL Synthesis Coding Guidelines Lattice Semiconductor for Lattice Semiconductor FPGAs Register Control Signals The generalpurpose latchesFFs in the PFU are used in a variety of configurations depending on device family For example the Lattice EC ECP SC and XP family of devices clock clock enable and LSFl control can be applied to the registers on a slice basis Each slice contains two LUT4 lookup tables feeding two registers programmed asto be in FF or Latch mode and some associated logic that allows the LUTs to be combined to perform functions such as LUT5 LUT6 LUT7 and LUT8 There is control logic to perform setreset functions prgorammable as syn chronousasynchronous clock select chipselect and wider RAMROM functions The ORCA Series 4 family of devices clock clock enable and LSFl control can be applied to the registers on a nibblewide basis When writing design codes in HDL keep the architecture in mind to avoid wasting resources in the device Here are several points for consideration If the register number is not a multiple of 2 or 4 dependent on device family try to code the registers in a way that all registers share the same clock and in a way that all registers share the same control signals Lattice Semiconductor FPGA devices have multiple dedicated Clock Enable signals per PFUTry to code the asynchronous clocks as clock enables so that PFU clock signals can be released to use global low skew clocks Try to code the registers with Local synchronous SetReset and Global asynchronous SetReset For more detailed architecture information refer to the Lattice Semiconductor FPGA data sheets Clock Enable Figure 139 shows an example of gated clocking Gating clock is not encouraged in digital designs because it may cause timing issues such as unexpected clock skewsThe structure of the PFU makes the gating clock even more undesirable since it will use up all the clock resources in one PFU and sometimes waste the FF Latches resources in the PFU By using the clock enable in the PFU the same functionality can be achieved without worrying about timing issues as only one signal is controlling the clock Since only one clock is used in the PFU all related logic can be implemented in one block to achieve better performance Figure 1310 shows the design with clock enable signal being used Figure 139 Asynchronous Gated Clocking din qout clk gate Figure 13 10 Synchronous Clock Enabling din E W gt clken S clk The VHDL and Verilog coding for Clock Enable are as shown in Figure 1310 VHDL example for Clock Enable Verilog example for Clock Enable i ckinname processc1k posedge clk begin qout lt clken dln qout 1 clk39event or cl k39139 then 1 clken39139 then 7 1n end 1f end 1 end process ClockiEnable 1312 Lattice Semiconductor HDL Synthesis Coding Guidelines for Lattice Semiconductor FPGAs The following are guidelines for coding the Clock Enable in Lattice Semiconductor FPGAs Clock Enable is only supported by FFs not latches Nibble wide FFs and slices inside a PLC share the same Clock Enable All flipflops in the Lattice Semiconductor FPGA library have a positive clock enable signal In the ORCA Series 4 architecture the Clock Enable signal has the higher priority over synchronous setreset by default However it can be programmed to have the priority of synchronous LSFl over the prior ity of Clock Enable This can be achieved by instantiating the library element in the source code For exam ple the library element FD1P3X is a flipflop that allows synchronous Clear to override Clock Enable Users can also specify the priority of generic coding by setting the priority of the control signals differently The following examples demonstrate coding methodologies to help the synthesis tools to set the higher pri ority of Clock Enable or synchronous LSFl VHDL Example of CE over Sync LSR COUNTS processCLK GRST beg1n 1 GRST 39139 th cnt lt others gt o els1 CLK39event and CE Over LSR Clock 1 CKEN 39139 th cnt lt cnt 1 els1 LRST 39139 then cnt lt others gt39o39 CLK 39 1 39 then Enable has hlgher prlorlty en end 1f end 1f end process COUNTS Verilog Example of CE over Sync always posedge CLK or posedge GRST eg1n 1 LSR VHDL Example of Sync LSR Over CE COUNTS processCLK GRST vent and CLK39139 then LSR over CE Sync setReset has hlgher pr1or1ty 1 LRST 39139 then Verilog Example of Sync LSR Over CE be 1 1 GRST cnt s 439b0 else 1 LRST c 39bm else 1 CKEN always posedge CLK or posedge GRST n cnt 139b1 SET I Reset There are two types of setreset functions in Lattice Semiconductor FPGAs Global GSFl and Local LSFl The GSFl signal is asynchronous and is used to initialize all registers during configuration It can be activated either by an external dedicated pin or from internal logic after configurationThe local SETFleset signal may be synchronous or asynchronous GSFl is pulsed at power up to either set or reset the registers depending on the configuration of the device Since the GSFl signal has dedicated routing resources that connect to the set and reset pin of the flip flops it saves generalpurpose routing and buffering resources and improves overall performance If asynchronous reset is used in the design it is recommended to use the GSFl for this function if possibleThe reset signal can be forced to be GSFl by the instantiation library element Synthesis tools will automatically infer GSFl if all registers in 1313 HDL Synthesis Coding Guidelines Lattice Semiconductor for Lattice Semiconductor FPGAs the design are asynchronously set or reset by the same wire The following examples show the correct syntax for instantiating GSFI in the VHDL and Verilog codes VHDL Example of GSR Instantiation Verilog Example of GSR Instantiation llbrary 1eee tdilog1c71164 use leeestdilog1c7unslgnedall 15 Hith clkI rstI rst clk 1n std g c output1o cntout cntout out stdilogicivectoru downto 0 end gsritest module gsritesuclk rst cntout entlty gsritest port 39 reg10 cnt archltecture behave of gsri est 1s GSR ul GSRrstI slgnal cnt stdiloglcivectoru downto 0 begln always posedge clk or negedge rst begln u1 GSR port map gsrgtrst 1f Irst CHI 239b0 processclk rst else begin cnt cnt 1 1 rsf 1 then end cnt lt o elslf rlslngiedge clk then 3551ng cutout cnt cnt lt cnt 1 endmodule d 1f en end process cntout lt cut end behave Use PIC Features Using IIO RegistersLatches in PIC Moving registers or latches into InputOutput cells PIC may reduce the number of PLCs used and decrease rout ing congestion In addition it reduces setup time requirements for incoming data and clocktooutput delay for out put data as shown in Figure 1311 Most synthesis tools will infer input registers or output registers in PIC if possible Users can set synthesis attributes in the specific tools to turn off the autoinfer capability Users can also instantiate library elements to control the implementation of PIC resource usage Figure 1311 Moving FF into PIC Input Register PIC PLC PIC I I W I I I I IINSIG 4D D Q IINSIG I I gt I I I I I I I I Before Using Input Register After Using Input Register Figure 13 12 Moving FF into PIC Output Register PLC PIC PIC I I quot I I I I I D Q OUTSIG I ouLSIG I I gt I I I I I I I I Before Using Output Register After Using Output Register 1314 HDL Synthesis Coding Guidelines Lattice Semiconductor for Lattice Semiconductor FPGAs Inferring Bidirectional IIO Users can either structurally instantiate the bidirectional lO library elements or behaviorally describe the lO paths to infer bidirectional buffers The following VHDL and Verilog examples show how to infer bidirectional lO buffers Inferring Bidirecti nal 10 in VHDL Inferring Iii directional 10 in Verilog llbrary lees module bldlrilnfer A B DIR s eeestd logic 1164311 lnoui A B T T lnput DIR entity bldlrilnfer 1s I portA B lnoul stdiloglc assmn B DIR A 1 b2 m stdiloglc asslgn A DIR B 139bz dlr end bldlr lnfer endmodule archltecture lattlce fpga of bldlrilnfer 1s begin B lt A when d 1 else 39239 A lt B when d1r39039 else 39239 end lattlce fpga Specifying IIO Types and Locations Users can either assign lO types and unique lO locations in the Preference Editor or specify them as attributes in the VHDL or Verilog source code The following examples show how to add attributes in the Synplify and Leonar doSpectrum synthesis tool sets For a complete list of supported attributes refer to the HDL Attributes section of the ispLEVEFl online help system VHDL example of specifying lO type and location attributes for Synplify amp Leonardo entity cnt is portclk in stdilogic res out stdilogic attribute LEVELMODE string attribute LEVELMODE of clk signal is SSTLZ attribute LOC of clk signal is V2 attribute LEVELMODE of res signal is SSTLZ attribute LOC of res signal is V3 end entity cnt Verilog example of specifying lO type and location attributes for Synplify amp Leonardo module cntclkres input clk synthesis LEVELMODE SSTLZ LOC V2 output res synthesis LEVELMODE SSTLZ LOC V3 exemplar begin exemplar attribute clk LEVELMODE SSTL2 exemplar attribute clk LOC V2 exemplar attribute res LEVELMODE SSTL2 exemplar attribute res LOC V3 exemplar end endmodule 1315 HDL Synthesis Coding Guidelines Lattice Semiconductor for Lattice Semiconductor FPGAs Implementation of Memories Although an FlTL description of RAM is portable and the coding is straightforward it is not recommended because the structureofFlAM blocksin every quot 39 I S nthesist 39 r39 39 4 h quot im le mentation and thus generate inefficient netlists for device fitting For Lattice Semiconductor FPGA devices RAM blocks should be generated through lPexpress as shown in the following screen 5 0t v39aisum a 3 Mudnis Tu generate the module or lP mm the Inlurmatlnn In the a ummwmemduies enabled ms such as Project Pam File Name etc i m cm 1 J quot39 3MC E an the Custumlze human A warm mu alien in allmv Etymbs customrbatiun orthe selzmea module or lF u MamType Mnduln Velsmn39 2n 2n Module Name RAMDPTRUE 0 AM Mm R carL flyaw 7quot PvnieuPam cvmcumeru Endscmnqsvwducumtnmtdi J a JEavampmms FlF 2n 3 n le Name Zn in RA DestgnEnlry SchematicVetting HDL v a n r J P Atwmunmm umcemmliy mulceaoecsp 1i Jinnnc mly l msp 7 5 4p 5 Muncmmpmplmais WNWquot MW 25 m1DP1UE l 5e DASHNZ FLK Inmalla lPsMnnulas 3 n PM P mua RAMJPJNJE When implementing large memories in the design it is recommended to construct the memory from the Enhanced Block RAM EBFl components found in every Lattice Semiconductor FPGA device When implementing small memories in the design it is recommended to construct the memory from the resources in the PFU The memoly utilizing resources in the PFU can also be generated by lPexpress Lattice Semiconductor FPGAs support many different memory types including synchronous dualport RAM syn chronous singleport RAM synchronous FIFO and synchronous ROM For more information on supported mem ory types per FPGA architecture please consult the Lattice Semiconductor FPGA data sheets Preventing Logic Replication and Limited Fanout Lattice Semiconductor FPGA device architectures are designed to handle high signal fanouts When users make use of clock resources there will be no hindrance on fanout problems However synthesis tools tend to replicate logic to reduce fanout during logic synthesis For example if the code implies Clock Enable and is synthesized with speed constraints the synthesis tool may replicate the Clock Enable logic This kind of logic replication occupies e resources in the devices and makes performance checking more difficult It is recommended to control the logic replication in synthesis process by using attributes for high fanout limit 1316 HDL Synthesis Coding Guidelines Lattice Semiconductor for Lattice Semiconductor FPGAs In the Synplicity project GUI under the Implementation Options gt Devices tab users can set the Fanout Guide value to 1000 instead of using the default value of 100 This will guide the tool to allow high fanout signals without replicating the logic In the LeonardoSpectrum tool project GUI under Technology gt Advanced Settings users can set the Max Fanout to be any number instead of the default value 0 j mumcmquotng mammalquot awful Tm Regan Venlagl VHDLI Taming a speed Package lmvlemenlallans LucenlDRmSeiles v oEnz v 2 v BA352 v way Fanam em Far2 35 Usage Dvllan Descilvllan mi 2 Synplicily Eancel Apply Help Use ispLEVER Project Navigator Results for Device Utilization and Performance Many synthesis tools give usage reports at the end of a successful synthesis These reports show the name and the number of library elements used in the designThe data in these reports do not represent the actual implemen tation of the design in the final Place and Route tool because the EDIF netlist will be further optimized during Map ping and Place and Route to achieve the best results It is strongly recommended to use the MAP report and the PAR report in the ispLEVER Project Navigator tool to understand the actual resource utilization in the device Although the synthesis report also provides a performance summary the timing information is based on estimated logic delays only The Place amp Route TRACE Report in the ispLEVER Project Navigator gives accurate perfor mance analysis of the design by including actual logic and routing delays in the paths Technical Support Assistance Hotline 1800LA39I39I39ICE North America 15032688001 Outside North America email techsupportlatticesemicom Internet wwwatticesemicom 1317 PCB Layout Recommendations 39 39 Semiconductor Corporation for PaCkageS September 2006 Technical Note TN1074 Introduction As Ball Grid Array BGA packages become increasingly popular it is important to understand how they are affected by various board layout techniquesThis document provides a brief overview of PCB layout considerations when working with BGA packages It outlines some of the most common problems and provides tips for avoiding them at the design stage Advantages and Disadvantages of BGA Packaging One of the greatest advantages of BGA packaging over other new technologies is that it can be supported with existing placement and assembly equipment BGAs also offer significantly more misalignment tolerance less sus ceptibility to coplanarity issues and easier PCB signal routing under a BGA package see Figure 141 The primary drawback of BGA packaging is the inability to access the solder joints for testing and inspection a later section in this document provides layout recommendations for testing At best only the outermost row of balls can be seen and board size and other components often restrict even that view The best option available for a complete inspection of the device is Xray imaging By this means the user can visually assess shorted connec tions missing balls filled vias and in some cases opens see Figure 142 Opens and partial opens where the solder did not wet the entire pad are more difficult to see and may require higher resolution equipment Figure 14 1 Misalignment of BGA Balls vs QFP Leads BGA Ball QFP Leads SolderablePad I r r l l l l l l 4 47012 4 47012 BGA Ball QFP Leads Solderable Pad I r r l l l l l 4 lt7 024 A 47 024 2006 Lattice Semiconductor Corp All Lattice trademarks registered trademarks patents and disclaimers are as listed at wwwlatticesemi comlegal All other brand or product names are trademarks or registered trademarks of their r b M W F r quotIquot it Hang m uu wwwlatticesemicom 141 tn1074013 PCB Layout Recommendations Lattice Semiconductor for BGA Packages Figure 142 Example of How Defects May Appear in an XFiay Image Via Normal solderjoint Soldershort 0 coo o o O o o o coo o o coo o o o 0 Missing solder ball 00 00 JAOOO 2000 Solderfilled via PCB Layout All Lattice BGA packages utilize Solder Mask Defined SMD pads For optimized solder joint formation the PCB pads should match the BGA solder pads see Figure 143 For example it the BGA has solder pads with 060 mm openings so should the corresponding site on the PCB Figure 143 SMD Pad with Example Dimensions I I I l l Via I Land I Opemng m Solder Mask over Solder Land 89 MaSk Land 9 H I Cross Section Plated Through Hole Via Placement Probably the most critical aspect of BGA PCB layout is the consideration for Plated Through Hole PTH place ment It the pad is too close or on top of the hole or it there is no solder mask covering the via then it is possible for the ball solder and paste to melt and be wicked into the hole If enough solder is lost into the hole the result could be an open for that lead While this type of defect can usually be detected in an Xray image it is best avoided at layout see Figure 142 PCB Layout Recommendations Lattice Semiconductor for BGA Packages BGA Board Layout Recommendations Pitch 100mm prGA ftBGA fpSBGA chGA All Other Pitch Pitch Pitch prGA 127mm 05mm 08mm ftBGA 100 prGA Organic Ceramic PBGA csBGA caBGA fpSBGA 256 ftBGA chGA chGA SBGA Solder Land Diameter L 043 053 066 053 080 070 080 Opening in Solder Mask M 030 040 045 040 060 050 063 Solder Ball Land Pitch e 050 080 100 100 100 100 127 Note The numbers in this table are intended to be used as an example only The actual numbers are dependent on the PCB manufacturing tol erance BGA Package Types mm or an mm and die down configuration SBGA packages offer enhanced thermal dissipation capability mm Further Information For additional information please visit the web sites listed below wwwamkorcomProductsall products Mww39 quot 39 39 39 bqa annnntn nrlf Technical Support Assistance Hotline 1800LATTICE North America 15032688001 Outside North America email techsupportlatticesemicom Internet wwwlatticesemicom Revision History 1 43 0 Section III MachXO Family Handbook Revision History
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