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Why an led display is more suitable for low-light conditions?

Why an led display is more suitable for low-light conditions?

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Online Instructor’s Manual  


Why an led display is more suitable for low-light conditions?



to accompany  

Digital Fundamentals  Tenth Edition  

Thomas L. Floyd  

Upper Saddle River, New Jersey  

Columbus, Ohio

 


What is the standard sop expression for segment d is?



__________________________________________________________________________________  

Copyright © 2009 by Pearson Education, Inc., Upper Saddle River, New Jersey 07458.  

Pearson Prentice Hall. All rights reserved. Printed in the United States of America. This publication is protected by  Copyright and permission should be obtained from the publisher prior to any prohibited reproduction, storage in a  retrieval system, or transmission in any form or by any means, electronic, mechanical, photocopying, recording, or  likewise. For information regarding permission(s), write to: Rights and Permissions Department.  We also discuss several other topics like What is the study of energy and its transformations?

Pearson Prentice Hall™ is a trademark of Pearson Education, Inc.  

Pearson® is a registered trademark of Pearson plc  


What is magneto-optic disk?



Prentice Hall® is a registered trademark of Pearson Education, Inc.

Instructors of classes using Floyd, Digital Fundamentals, Tenth Edition , may reproduce material from the  instructor’s manual for classroom use.  

10 9 8 7 6 5 4 3 2 1  

 ISBN-13: 978-0-13-712960-7   ISBN-10: 0-13-712960-2

CONTENTS  

PART 1: PROBLEM SOLUTIONS ............................................................................................1  CHAPTER 1 Introductory Concepts ............................................................................................2  CHAPTER 2 Number Systems, Operations, and Codes ..............................................................7  CHAPTER 3 Logic Gates ..........................................................................................................23  CHAPTER 4 Boolean Algebra and Logic Simplification..........................................................35  CHAPTER 5 Combinational Logic Analysis.............................................................................60  CHAPTER 6 Functions of Combinational Logic.......................................................................95  CHAPTER 7 Latches, Flip-Flops, and Timers.........................................................................115  CHAPTER 8 Counters .............................................................................................................130  CHAPTER 9 Shift Registers ...................................................................................................159  CHAPTER 10 Memory and Storage ..........................................................................................175  CHAPTER 11 Programmable Logic and Software....................................................................185  CHAPTER 12 Signal Interfacing and Processing ......................................................................195  CHAPTER 13 Computer Concepts ............................................................................................204  CHAPTER 14 Integrated Circuit Technologies .........................................................................210  If you want to learn more check out Who is maximilien françois marie isidore de robespierre?

PART 2: SYSTEM APPLICATION ACTIVITY SOLUTIONS ..........................................217  CHAPTER 4 ............................................................................................................................218  CHAPTER 5 ............................................................................................................................221  CHAPTER 6 ............................................................................................................................223  CHAPTER 7 ............................................................................................................................228  CHAPTER 8 ............................................................................................................................230  CHAPTER 9 ............................................................................................................................233  CHAPTER 10 ............................................................................................................................234  CHAPTER 11 ............................................................................................................................235  If you want to learn more check out The raf kinase activates what cascade?

PART 3: OVERVIEW OF IEEE STD. 91-1984 .....................................................................239  

PART 4: LABORATORY SOLUTIONS FOR EXPERIMENTS IN DIGITAL   FUNDAMENTALS by David Buchla......................................................................265  

iii

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NOTE: For access to hidden faults in Multisim circuits, the password is book.  iv

PART 1  

Problem Solutions

Chapter 1  

CHAPTER 1  

INTRODUCTORY CONCEPTS

Section 1-1 Digital and Analog Quantities  

1. Digital data can be transmitted and stored more efficiently and reliably than analog data. Also,  digital circuits are simpler to implement and there is a greater immunity to noisy environments.  We also discuss several other topics like Who are avery mccarty and macleod?
We also discuss several other topics like What types of tasks do people with broca’s aphasia & wernicke’s aphasia struggle with?

2. Pressure is an analog quantity.  

3. A clock, a thermometer, and a speedometer can have either an analog or a digital output.  

Section 1-2 Binary Digits, Logic Levels, and Digital Waveforms

4. In positive logic, a 1 is represented by a HIGH level and a 0 by a LOW level. In negative logic,  a 1 is represented by a LOW level, and a 0 by a HIGH level.  

5. HIGH = 1; LOW = 0. See Figure 1-1.  

If you want to learn more check out Who is lysistrata's next­-door neighbor that is older than her?

6. A 1 is a HIGH and a 0 is a LOW:  

 (a) HIGH, LOW, HIGH, HIGH, HIGH, LOW, HIGH  

 (b) HIGH, HIGH, HIGH, LOW, HIGH, LOW, LOW, HIGH

2  

Chapter 1  

7. See Figure 1-2.  

8. T = 4 ms. See Figure 1-3.  

11 = T = 0.25 kHz = 250 Hz  

9. f = ms 4 

10. The waveform in Figure 1-61 is periodic because it repeats at a fixed interval.  

11. tW = 2 ms; T = 4 ms  

t 100 = 50%  

ms 2 100 W 

 % duty cycle = ⎟⎠⎞ ⎜⎝⎛ ⎟ = ⎠⎞ ⎜⎝⎛ms 4

T

12. See Figure 1-4.

3

Chapter 1  

13. Each bit time = 1 μs  

 Serial transfer time = (8 bits)(1 μs/bit) = 8 μs  

 Parallel transfer time = 1 bit time = 1 μs  

14. T = 1 1

f 3.5 GHz = = 0.286 ns  

Section 1-3 Basic Logic Operations  

15. LON = SW1 + SW2 + SW1 ⋅ SW2  

16. An AND gate produces a HIGH output only when all of its inputs are HIGH.  17. AND gate. See Figure 1-5.  

18. An OR gate produces a HIGH output when either or both inputs are HIGH. An exclusive-OR  gate produces a HIGH if one input is HIGH and the other LOW.  

Section 1-4 Introduction to the System Concept

19. See Figure 1-6.

4  

Chapter 1  

1 = 100 μs  

20. T = kHz 10 

 Pulses counted = s 100ms 100μ = 1000  

21. See Figure 1-7.  

Section 1-5 Fixed-Function Integrated Circuits  

22. Circuits with complexities of from 100 to 10,000 equivalent gates are classified as large scale  integration (LSI).  

23. The pins of an SMT are soldered to the pads on the surface of a pc board, whereas the pins of a  DIP feed through and are soldered to the opposite side. Pin spacing on SMTs is less than on DIPs  and therefore SMT packages are physically smaller and require less surface area on a pc board.  

24. See Figure 1-8.

5

Chapter 1  

Section 1-6 Test and Measurement Instruments  

25. Amplitude = top of pulse minus base line  

V = 8 V − 1 V = 7 V  

26. A flashing probe lamp indicates a continuous sequence of pulses (pulse train).  Section 1-7 Introduction to Programmable Logic  

27. The following do not describe PLDs: VHDL, AHDL  

28. SPLD: Simple Programmable Logic Device  

 CPLD: Complex Programmable Logic Device  

 HDL: Hardware Description Language  

 FPGA: Field-Programmable Gate Array  

 GAL: Generic Array Logic  

29. (a) Design entry: The step in a programmable logic design flow where a description of the  circuit is entered in either schematic (graphic) form or in text form using an HDL.  

 (b) Simulation: The step in a design flow where the entered design is simulated based on  defined input waveforms.  

 (c) Compilation: A program process that controls the design flow process and translates a  design source code to object code for testing and downloading.  

 (d) Download: The process in which the design is transferred from software to hardware.  

30. Place and route or fitting is the process where the logic structures described by the netlist are  mapped into the actual structure of the specific target device. This results in an output called a  bitstream.

6  

CHAPTER 2  

NUMBER SYSTEMS, OPERATIONS, AND CODES Section 2-1 Decimal Numbers  

1. (a) 1386 = 1 ⋅ 103 + 3 ⋅ 102 + 8 ⋅ 101 + 6 ⋅ 100 

 = 1 ⋅ 1000 + 3 ⋅ 100 + 8 ⋅ 10 + 6 ⋅ 1  

 The digit 6 has a weight of 100 = 1  

 (b) 54,692 = 5 ⋅ 104 + 4 ⋅ 103 + 6 ⋅ 102 + 9 ⋅ 101 + 2 ⋅ 100  = 5 ⋅ 10,000 + 4 ⋅ 1000 + 6 ⋅ 100 + 9 ⋅ 10 + 2 ⋅ 1  

 The digit 6 has a weight of 102 = 100  

 (c) 671,920 = 6 ⋅ 105 + 7 ⋅ 104 + 1 ⋅ 103 + 9 ⋅ 102 + 2 ⋅ 101 + 0 ⋅ 100  = 6 ⋅ 100,000 + 7 ⋅ 10,000 + 1 ⋅ 1000 + 9 ⋅ 100 + 2 ⋅ 10 + 0 ⋅ 1   The digit 6 has a weight of 105 = 100,000  

2. (a) 10 = 101 (b) 100 = 102 

 (c) 10,000 = 104 (d) 1,000,000 = 106 

3. (a) 471 = 4 ⋅ 102 + 7 ⋅ 101 + 1 ⋅ 100 

 = 4 ⋅ 100 + 7 ⋅ 10 + 1 ⋅ 1  

 = 400 + 70 + 1  

 (b) 9,356 = 9 ⋅ 103 + 3 ⋅ 102 + 5 ⋅ 101 + 6 ⋅ 100 

 = 9 ⋅ 1000 + 3 ⋅ 100 + 5 ⋅ 10 + 6 ⋅ 1  

 = 9,000 + 300 + 50 + 6  

 (c) 125,000 = 1 ⋅ 105 + 2 ⋅ 104 + 5 ⋅ 103 

 = 1 ⋅ 100,000 + 2 ⋅ 10,000 + 5 ⋅ 1000  

 = 100,000 + 20,000 + 5,000  

4. The highest four-digit decimal number is 9999.  

Section 2-2 Binary Numbers  

5. (a) 11 = 1 ⋅ 21 + 1 ⋅ 20 = 2 + 1 = 3  

 (b) 100 = 1 ⋅ 22 + 0 ⋅ 21 + 0 ⋅ 20 = 4  

 (c) 111 = 1 ⋅ 22 + 1 ⋅ 21 + 1 ⋅ 20 = 4 + 2 + 1 = 7  

 (d) 1000 = 1 ⋅ 23 + 0 ⋅ 22 + 0 ⋅ 21 + 0 ⋅ 20 = 8  

 (e) 1001 = 1 ⋅ 23 + 0 ⋅ 22 + 0 ⋅ 21 + 1 ⋅ 20 = 8 + 1 = 9  

 (f) 1100 = 1 ⋅ 23 + 1 ⋅ 22 + 0 ⋅ 21 + 0 ⋅ 20 = 8 + 4 = 12  

 (g) 1011 = 1 ⋅ 23 + 0 ⋅ 22 + 1 ⋅ 21 + 1 ⋅ 20 = 8 + 2 + 1 = 11   (h) 1111 = 1 ⋅ 23 + 1 ⋅ 22 + 1 ⋅ 21 + 1 ⋅ 20 = 8 + 4 + 2 + 1 = 15

7  

Chapter 2  

6. (a) 1110 = 1 ⋅ 23 + 1 ⋅ 22 + 1 ⋅ 21 = 8 + 4 + 2 = 14

(b) 1010 = 1 ⋅ 23 + 1 ⋅ 21 = 8 + 2 = 10  

 (c) 11100 = 1 ⋅ 24 + 1 ⋅ 23 + 1 ⋅ 22 = 16 + 8 + 4 = 28  

 (d) 10000 = 1 ⋅ 24 = 16  

(e) 10101 = 1 ⋅ 24 + 1 ⋅ 22 + 1 ⋅ 20 = 16 + 4 + 1 = 21  

(f) 11101 = 1 ⋅ 24 + 1 ⋅ 23 + 1 ⋅ 22 + 1 ⋅ 20 = 16 + 8 + 4 + 1 = 29  

(g) 10111 = 1 ⋅ 24 + 1 ⋅ 22 + 1 ⋅ 21 + 1 ⋅ 20 = 16 + 4 + 2 + 1 = 23  

(h) 11111 = 1 ⋅ 24 + 1 ⋅ 23 + 1 ⋅ 22 + 1 ⋅ 21 + 1 ⋅ 20 = 16 + 8 + 4 + 2 + 1 = 31  

7. (a) 110011.11 = 1 ⋅ 25 + 1 ⋅ 24 + 1 ⋅ 21 + 1 ⋅ 20 + 1 ⋅ 2−1 + 1 ⋅ 2−2  = 32 + 16 + 2 + 1 + 0.5 + 0.25 = 51.75  

 (b) 101010.01 = 1 ⋅ 25 + 1 ⋅ 23 + 1 ⋅ 21 + 1 ⋅ 2−2 = 32 + 8 + 2 + 0.25   = 42.25  

 (c) 1000001.111 = 1 ⋅ 26 + 1 ⋅ 20 + 1 ⋅ 2−1 + 1 ⋅ 2−2 + 1 ⋅ 2−3 

 = 64 + 1 + 0.5 + 0.25 + 0.125 = 65.875  

 (d) 1111000.101 = 1 ⋅ 26 + 1 ⋅ 25 + 1 ⋅ 24 + 1 ⋅ 23 + 1 ⋅ 2−1 + 1 ⋅ 2−3  = 64 + 32 + 16 + 8 + 0.5 + 0.125 = 120.625  

 (e) 1011100.10101 = 1 ⋅ 26 + 1 ⋅ 24 + 1 ⋅ 23 + 1 ⋅ 22 + 1 ⋅ 2−1 + 1 ⋅ 2−3 + 1 ⋅ 2−5  = 64 + 16 + 8 + 4 + 0.5 + 0.125 + 0.03125  

 = 92.65625  

 (f) 1110001.0001 = 1 ⋅ 26 + 1 ⋅ 25 + 1 ⋅ 24 + 1 ⋅ 20 + 1 ⋅ 2−4 

 = 64 + 32 + 16 + 1 + 0.0625 = 113.0625  

 (g) 1011010.1010 = 1 ⋅ 26 + 1 ⋅ 24 + 1 ⋅ 23 + 1 ⋅ 21 + 1 ⋅ 2−1 + 1 ⋅ 2−3  = 64 + 16 + 8 + 2 + 0.5 + 0.125 = 90.625  

(h) 1111111.11111 = 1 ⋅ 26 + 1 ⋅ 25 + 1 ⋅ 24 + 1 ⋅ 23 + 1 ⋅ 22 + 1 ⋅ 21 

+ 1 ⋅ 20 + 1 ⋅ 2−1 + 1 ⋅ 2−2 + 1 ⋅ 2−3 + 1 ⋅ 2−4 + 1 ⋅ 2−5 

 = 64 + 32 + 16 + 8 + 4 + 2 + 1 + 0.5 + 0.25 + 0.125 + 0.0625 + 0.03125  

 = 127.96875  

8. (a) 22 − 1 = 3 (b) 23 − 1 = 7  

 (c) 24 − 1 = 15 (d) 25 − 1 = 31  

 (e) 26 − 1 = 63 (f) 27 − 1 = 127  

 (g) 28 − 1 = 255 (h) 29 − 1 = 511  

 (i) 210 − 1 = 1023 (j) 211 − 1 = 2047  

9. (a) (24 − 1) < 17 < (25 − 1); 5 bits  

 (b) (25 − 1) < 35 < (26 − 1); 6 bits  

 (c) (25 − 1) < 49 < (26 − 1); 6 bits  

 (d) (26 − 1) < 68 < (27 − 1); 7 bits  

 (e) (26 − 1) < 81 < (27 − 1); 7 bits  

 (f) (26 − 1) < 114 < (27 − 1); 7 bits  

 (g) (27 − 1) < 132 < (28 − 1); 8 bits  

 (h) (27 − 1) < 205 < (28 − 1); 8 bits

8  

Chapter 2  

10. (a) 0 through 7:  

 000, 001, 010, 011, 100, 101, 110, 111  

 (b) 8 through 15:  

 1000, 1001, 1010, 1011, 1100, 1101, 1110, 1111  

 (c) 16 through 31:  

 10000, 10001, 10010, 10011, 10100, 10101, 10110, 10111, 11000, 11001, 11010,  11011, 11100, 11101, 11110, 11111  

(d) 32 through 63:  

100000, 100001, 100010, 100011, 100100, 100101, 100110, 100111, 10100, 101001,   101010, 101011, 101100, 101101, 101110, 101111, 110000, 110001, 110010, 110011,  110100, 110101, 110110, 110111, 111000, 111001, 111010, 111011, 111100, 111101,  111110, 111111  

(e) 64 through 75:  

 1000000, 1000001, 1000010, 1000011, 1000100, 1000101, 1000110, 1000111,   1001000, 1001001, 1001010, 1001011  

Section 2-3 Decimal-to-Binary Conversion  

11. (a) 10 = 8 + 2 = 23 + 21 = 1010  

 (b) 17 = 16 + 1 = 24 + 20 = 10001  

 (c) 24 = 16 + 8 = 24 + 23 = 11000  

 (d) 48 = 32 + 16 = 25 + 24 = 110000  

 (e) 61 = 32 + 16 + 8 + 4 + 1 = 25 + 24 + 23 + 22 + 20 = 111101  

 (f) 93 = 64 + 16 + 8 + 4 + 1 = 26 + 24 + 23 + 22 + 20 = 1011101  

 (g) 125 = 64 + 32 + 16 + 8 + 4 + 1 = 26 + 25 + 24 + 23 + 22 + 20 = 1111101   (h) 186 = 128 + 32 + 16 + 8 + 2 = 27 + 25 + 24 + 23 + 21 = 10111010  

12. (a) 0.32 ≅ 0.00 + 0.25 + 0.0625 + 0.0 + 0.0 + 0.0078125 = 0.0101001   (b) 0.246 ≅ 0.0 + 0.0 + 0.125 + 0.0625 + 0.03125 + 0.015625 = 0.001111   (c) 0.0981 ≅ 0.0 + 0.0 + 0.0 + 0.0625 + 0.03125 + 0.0 + 0.0 + 0.00390625 = 0.0001101

9  

Chapter 2  

13. (a) 215 = 7, R = 1( LSB)   27 = 3, R = 1   23 = 1, R = 1   21 = 0, R = 1 (MSB)  

 (d) 234 = 17, R = 0 (LSB)  17 = 8, R = 1  

2

8 = 4, R = 0  

2

4 = 2, R = 0  

2

2 = 1, R = 0  

2

1 = 0, R = 1 (MSB)  

2

 

(g) 265 = 32, R = 1 (LSB)  32 = 16, R = 0  

2

16 = 8, R = 0  

2

8 = 4, R = 0  

2

4 = 2, R = 0  

2

2 = 1, R = 0  

2

1 = 0, R = 1(MSB)  

2

(b) 221 = 10, R = 1 (LSB)  10 = 5, R = 0  

2

5 = 2, R = 1  

2

2 = 1, R = 0  

2

1 = 0, R = 1 (MSB)  

2

(e) 240 = 20, R = 0 (LSB)  20 = 10, R = 0  

2

10 = 5, R = 0  

2

5 = 2, R = 1  

2

2 = 1, R = 0  

2

1 = 0, R = 1 (MSB)  

2

(h) 273 = 36, R = 1 (LSB)  36 = 18, R = 0  

2

18 = 9, R = 0  

2

9 = 4, R = 1  

2

4 = 2, R = 0  

2

2 = 1, R = 0  

2

1 = 0, R = 1 (MSB)  2

(c) 228 = 14, R = 0 (LSB)  14 = 7, R = 0  

2

7 = 3, R = 1  

2

3 = 1, R = 1  

2

1 = 0, R = 1 (MSB)  2

(f) 259 = 29, R = 1 (LSB)  29 = 14, R = 1  

2

14 = 7, R = 0  

2

7 = 3, R = 1  

2

3 = 1, R = 1  

2

1 = 0, R = 1 (MSB)

2

10  

Chapter 2  

14. (a) 0.98 ⋅ 2 = 1.96 1 (MSB) (b) 0.347 ⋅ 2 = 0.694 0 (MSB)   0.96 ⋅ 2 = 1.92 1 0.694 ⋅ 2 = 1.388 1   0.92 ⋅ 2 = 1.84 1 0.388 ⋅ 2 = 0.776 0   0.84 ⋅ 2 = 1.68 1 0.776 ⋅ 2 = 1.552 1   0.68 ⋅ 2 = 1.36 1 0.552 ⋅ 2 = 1.104 1   0.36 ⋅ 2 = 0.72 0 0.104 ⋅ 2 = 0.208 0  continue if more accuracy is desired 0.208 ⋅ 2 = 0.416 0  

 0.111110 continue if more accuracy is desired   0.0101100  

 (c) 0.9028 ⋅ 2 = 1.8056 1 (MSB)  

 0.8056 ⋅ 2 = 1.6112 1  

 0.6112 ⋅ 2 = 1.2224 1  

 0.2224 ⋅ 2 = 0.4448 0  

 0.4448 ⋅ 2 = 0.8896 0  

 0.8896 ⋅ 2 = 1.7792 1  

 0.7792 ⋅ 2 = 1.5584 1  

 continue if more accuracy is desired  

 0.1110011  

Section 2-4 Binary Arithmetic  

 

15.

11(a)

10(b)

101(c)

+

01

 

+

10

+

011

100

111(d)

100

(e) 1001

1000

(f) 1101

+

110

+

0101

+

1011

16.

1101

11(a)

1110

101(b)

11000

110(c)

01 10

100 001

101 001

(d) 1110

(e) 1100

(f) 11010

0011 1011

1001 0011

10111 00011

11

Chapter 2  

17.

11(a)

100(b)

111(c)

(d) 1001

11

10

101

110

11

11

1001

 

000 100

1000

111

000

111

100011

0000

1001

1001

110110

(e) 1101

(f) 1110

1101 1101

1101 1110

0000

1101

1101

10101001

0000

1110

1110

10110110

100 = 010 (b) 0011 

1001 = 0011 (c) 0100 

18. (a) 10 

1100 = 0011  

Section 2-5 1’s and 2’s Complements of Binary Numbers  19. Zero is represented in 1’s complement as all 0’s (for +0) or all 1’s (for −0).  20. Zero is represented by all 0’s only in 2’s complement.  

21. (a) The 1’s complement of 101 is 010.  

 (b) The 1’s complement of 110 is 001.  

 (c) The 1’s complement of 1010 is 0101.  

 (d) The 1’s complement of 11010111 is 00101000.  

 (e) The 1’s complement of 1110101 is 0001010.  

 (f) The 1’s complement of 00001 is 11110.  

22. Take the 1’s complement and add 1:  

 (a) 01 + 1 = 10 (b) 000 + 1 = 001   (c) 0110 + 1 = 0111 (d) 0010 + 1 = 0011   (e) 00011 + 1 = 00100 (f) 01100 + 1 = 01101   (g) 01001111 + 1 = 01010000 (h) 11000010 + 1 = 11000011

12  

Chapter 2  

Section 2-6 Signed Numbers  

23. (a) Magnitude of 29 = 0011101 (b) Magnitude of 85 = 1010101   + 29 = 00011101 −85 = 11010101  

 (c) Magnitude of 10010 = 1100100 (d) Magnitude of 123 = 1111011   +100 = 01100100 −123 = 11111011  

24. (a) Magnitude of 34 = 0100010 (b) Magnitude of 57 = 0111001   −34 = 11011101 +57 = 00111001  

 (c) Magnitude of 99 = 1100011 (d) Magnitude of 115 = 1110011   −99 = 10011100 +115 = 01110011  

25. (a) Magnitude of 12 = 1100 (b) Magnitude of 68 = 1000100  +12 = 00001100 −68 = 10111100  

(c) Magnitude of 10110 = 1100101 (d) Magnitude of 125 = 1111101   +10110 = 01100101 −125 = 10000011  

26. (a) 10011001 = −25 (b) 01110100 = +116 (c) 10111111 = −63  

27. (a) 10011001 = −(01100110) = −102  

 (b) 01110100 = +(1110100) = +116  

 (c) 10111111 = −(1000000) = −64  

28. (a) 10011001 = −(1100111) = −103  

 (b) 01110100 = +(1110100) = +116  

 (c) 10111111 = −(1000001) = −65  

29. (a) 0111110000101011 → sign = 0  

 1.11110000101011 ⋅ 214 → exponent = 127 + 14 + 141 = 10001101   Mantissa = 11110000101011000000000  

 01000110111110000101011000000000

 (b) 100110000011000 → sign = 1  

 1.10000011000 ⋅ 211 → exponent = 127 + 11 = 138 = 10001010   Mantissa = 11000001100000000000000  

 11000101011000001100000000000000

30. (a) 11000000101001001110001000000000  

 Sign = 1  

 Exponent = 10000001 = 129 − 127 = 2  

 Mantissa = 1.01001001110001 ⋅ 22 = 101.001001110001  

 −101.001001110001 = −5.15258789  

 (b) 01100110010000111110100100000000  

 Sign = 0  

 Exponent = 11001100 = 204 − 127 = 77  

 Mantissa = 1.100001111101001  

 1.100001111101001 ⋅ 277

13

Chapter 2  

Section 2-7 Arithmetic Operations with Signed Numbers  

31. (a) 33 = 00100001 00100001   15 = 00001111 + 00001111  00110000  

 (c) 46 = 00101110 11010010   −46 = 11010010 + 00011001  25 = 00011001 11101011  

(b) 56 = 00111000 00111000   27 = 00011011 + 11100101 −27 = 11100101 00011101  

(d) 11010 = 01101110 10010010  −11010 = 10010010 + 10101100  84 = 01010100 100111110   −84 = 10101100

32. (a) 00010110 (b) 01110000   + 00110011 + 10101111  01001001 100011111  

33. (a) 10001100 (b) 11011001   + 00111001 + 11100111  11000101 11000000  

34. (a) 00110011 00110011   − 00010000 + 11110000  1 00100011  

35. 01101010 01101010  ⋅ 11110001 ⋅ 00001111  01101010   01101010   100111110   01101010   1011100110   01101010   11000110110  

(b) 01100101 01100101  − 11101000 + 00011000  01111101

 Changing to 2’s complement with sign: 100111001010  01000100 = 00000010  

36.00011001 

68 = 2, remainder of 18  

25

Section 2-8 Hexadecimal Numbers  

37. (a) 3816 = 0011 1000  

 (b) 5916 = 0101 1001  

 (c) A1416 = 1010 0001 0100  

 (d) 5C816 = 0101 1100 1000  

 (e) 410016 = 0100 0001 0000 0000  

 (f) FB1716 = 1111 1011 0001 0111  

 (g) 8A9D16 = 1000 1010 1001 1101

14  

Chapter 2  

38. (a) 1110 = E16 

 (b) 10 = 216 

 (c) 0001 0111 = 1716 

 (d) 1010 0110 = A616 

 (e) 0011 1111 0000 = 3F016 

 (f) 1001 1000 0010 = 98216 

39. (a) 2316 = 2 ⋅ 161 + 3 ⋅ 160 = 32 + 3 = 35  

 (b) 9216 = 9 ⋅ 161 + 2 ⋅ 160 = 144 + 2 = 146  

 (c) 1A16 = 1 ⋅ 161 + 10 ⋅ 160 = 16 + 10 = 26  

 (d) 8D16 = 8 ⋅ 161 + 13 ⋅ 160 = 128 + 13 = 141   (e) F316 = 15 ⋅ 161 + 3 ⋅ 160 = 240 + 3 = 243  

 (f) EB16 = 14 ⋅ 161 + 11 ⋅ 160 = 224 + 11 = 235   (g) 5C216 = 5 ⋅ 162 + 12 ⋅ 161 + 2 ⋅ 160 = 1280 + 192 + 2 = 1474   (h) 70016 = 7 ⋅ 162 = 1792  

40. (a) 168 = 0, remainder = 8  

 hexadecimal number = 816 

 (c) 1633 = 2, remainder = 1 (LSD)   162 = 0, remainder = 2  

 hexadecimal number = 2116 284 = 17, remainder = 12 = C16 (LSD)  

 (e) 16

 1617 = 1, remainder = 1  

 161 = 0, remainder = 1  

(b) 1614 = 0, remainder = 14 = E16 

hexadecimal number = E16 

(d) 1652 = 3, remainder = 4 (LSD)  

3 = 0, remainder = 3  

16

 hexadecimal number = 3416 

2890 = 180, remainder = 10 = A16 (LSD)  

(f) 16

180 = 11, remainder = 4  

16

11 = , remainder = 11 = B16 

16

0

 hexadecimal number = 11C16 

4019 = 251, remainder = 3 (LSD)  

(g) 16 

251 = 15, remainder = 11 = B16 

16

15 = 0, remainder = 15 = F16 

16

 hexadecimal number = FB316 

41. (a) 3716 + 2916 = 6016 

 (b) A016 + 6B16 = 10B16 

 (c) FF16 + BB16 = 1BA16

 hexadecimal number = B4A16 6500 = 406, remainder = 4 (LSD)  

(h) 16 

406 = 25, remainder = 6  

16

25 = 1, remainder = 9  

16

1 = 0, remainder = 1  

16

 hexadecimal number = 196416 

15

Chapter 2  

42. (a) 5116 − 4016 = 1116 

(b) C816 − 3A16 = 8E16 

 (c) FD16 − 8816 = 7516 

Section 2-9 Octal Numbers  

43. (a) 128 = 1 ⋅ 81 + 2 ⋅ 80 = 8 + 2 = 10  

 (b) 278 = 2 ⋅ 81 + 7 ⋅ 80 = 16 + 7 = 23  

 (c) 568 = 5 ⋅ 81 + 6 ⋅ 80 = 40 + 6 = 46  

 (d) 648 = 6 ⋅ 81 + 4 ⋅ 80 = 48 + 4 = 52  

 (e) 1038 = 1 ⋅ 82 + 3 ⋅ 80 = 64 + 3 = 67  

 (f) 5578 = 5 ⋅ 82 + 5 ⋅ 81 + 7 ⋅ 80 = 320 + 40 + 7 = 367   (g) 1638 = 1 ⋅ 82 + 6 ⋅ 81 + 3 ⋅ 80 = 64 + 48 + 3 = 115   (h) 10248 = 1 ⋅ 83 + 2 ⋅ 81 + 4 ⋅ 80 = 512 + 16 + 4 = 532   (i) 77658 = 7 ⋅ 83 + 7 ⋅ 82 + 6 ⋅ 81 + 5 ⋅ 80 = 3584 + 448 + 48 + 5 = 4085  

44. (a) 815 = 1, remainder = 7 (LSD)   81 = 0, remainder =1   octal number = 178 

 

(c) 846 = 5, remainder = 6 (LSD)   85 = 0, remainder = 5   octal number = 568 

 

 (e) 8100 = 12, remainder = 4 (LSD)   812 = 1, remainder = 4   81 = 0, remainder = 1   octal number = 1448 

 

(g) 8219 = 27, remainder = 3 (LSD)   827 = 3, remainder = 3   83 = 0, remainder = 3   octal number = 3338 

(b) 827 = 3, remainder = 3 (LSD)  3 = 0, remainder = 3  

8

 octal number = 338 

(d) 870 = 8, remainder = 6 (LSD)  8 = 1, remainder = 0  

8

1 = 0, remainder = 1  

8

 octal number = 1068 

(f) 8142 = 17, remainder = 6 (LSD)  17 = 2, remainder = 1  

8

2 = 0, remainder = 2  

8

 octal number = 2168 

(h) 8435 = 54, remainder = 3 (LSD)  54 = 6, remainder = 6  

8

6 = 0, remainder = 6  

8

 octal number = 6638

16  

45. (a) 138 = 001 011  

 (b) 578 = 101 111  

 (c) 1018 = 001 000 001  

 (d) 3218 = 011 010 001  

 (e) 5408 = 101 100 000  

 (f) 46538 = 100 110 101 011  

 (g) 132718 = 001 011 010 111 001  

 (h) 456008 = 100 101 110 000 000  

 (i) 1002138 = 001 000 000 010 001 011  

46. (a) 111 = 78 

 (b) 010 = 28 

 (c) 110 111 = 678 

 (d) 101 010 = 528 

 (e) 001 100 = 148 

 (f) 001 011 110 = 1368 

 (g) 101 100 011 001 = 54318 

 (h) 010 110 000 011 = 26038 

 (i) 111 111 101 111 000 = 775708 

Section 2-10 Binary Coded Decimal (BCD)  

47. (a) 10 = 0001 0000  

 (b) 13 = 0001 0011  

 (c) 18 = 0001 1000  

 (d) 21 = 0010 0001  

 (e) 25 = 0010 0101  

 (f) 36 = 0011 0110  

 (g) 44 = 0100 0100  

 (h) 57 = 0101 0111  

 (i) 69 = 0110 1001  

 (j) 98 = 1001 1000  

 (k) 125 = 0001 0010 0101  

 (l) 156 = 0001 0101 0110  

48. (a) 10 = 10102 4 bits binary, 8 bits BCD   (b) 13 = 11012 4 bits binary, 8 bits BCD   (c) 18 = 100102 5 bits binary, 8 bits BCD   (d) 21 = 101012 5 bits binary, 8 bits BCD   (e) 25 = 110012 5 bits binary, 8 bits BCD   (f) 36 = 1001002 6 bits binary, 8 bits BCD   (g) 44 = 1011002 6 bits binary, 8 bits BCD   (h) 57 = 1110012 6 bits binary, 8 bits BCD   (i) 69 = 10001012 7 bits binary, 8 bits BCD   (j) 98 = 11000102 7 bits binary, 8 bits BCD   (k) 125 = 11111012 7 bits binary, 12 ibts BCD  

 (l) 156 = 100111002 8 bits binary, 12 bits BCD

17  

Chapter 2  

49. (a) 104 = 0001 0000 0100  

 (b) 128 = 0001 0010 1000  

 (c) 132 = 0001 0011 0010  

 (d) 150 = 0001 0101 0000  

 (e) 186 = 0001 1000 0110  

 (f) 210 = 0010 0001 0000  

 (g) 359 = 0011 0101 1001  

 (h) 547 = 0101 0100 0111  

 (i) 1051 = 0001 0000 0101 0001  

50. (a) 0001 = 1 (b) 0110 = 6   (c) 1001 = 9 (d) 0001 1000 = 18   (e) 0001 1001 = 19 (f) 0011 0010 = 32   (g) 0100 0101 = 45 (h) 1001 1000 = 98   (i) 1000 0111 0000 = 870  

51. (a) 1000 0000 = 80  

 (b) 0010 0011 0111 = 237  

 (c) 0011 0100 0110 = 346  

 (d) 0100 0010 0001 = 421  

 (e) 0111 0101 0100 = 754  

 (f) 1000 0000 0000 = 800  

 (g) 1001 0111 1000 = 978  

 (h) 0001 0110 1000 0011 = 1683  

 (i) 1001 0000 0001 1000 = 9018  

 (j) 0110 0110 0110 0111 = 6667  

52. (a) 0010   + 0001  0011  

 (d) 1000   + 0001  1001    

 (g) 01000000   + 01000111  10000111  

(b) 0101  

 + 0011 

 1000  

(e) 00011000   + 00010001  00101001  

(h) 10000101   + 00010011  10000111  

(c) 0111  

 + 0010 

 1001  

(f) 01100100   + 00110011  10010111

18  

Chapter 2  

53. (a)    

+

 

1000 0110 1110

invalid  

(b)  

+

 

0111 0101 1100

invalid  

+

0110

+

0110

 (c)  

00010100 1001

(d)  

00010010 1001

+

1000

+

0111

 

10001

invalid  

10000

 

invalid  

+

0110

+

0110

 (e)  

00010111 00100101

(f)  

00010110

01010001

+

00100111

+

01011000

 

01001100

invalid invalid  10101001

+

0110

+

0110

(g)  

01010010 10011000

(h)  

000100001001

010101100001

+

10010111

+

011100001000

 

100101111

invalid invalid  

110001101001

+

01100110

+

0110

000110010101

0001001001101001

19

Chapter 2  

54. (a) 4 + 3  0100

(b) 5 + 2  0101

 

+

0011 0111

+

0010 0111

 (c) 6 + 4  0110

(d) 17 + 12  00010111

+

 

0100 1010

+

00100010 00101001

+

0110

(f) 65 + 58  

00010000

+

 (e) 28 + 23  

00101000

01100101 01011000 10111101

+

00100011

+

01100110

 

01001011

000100100011

+

0110

(h) 295 + 157  

01010001

 

+

(g) 113 + 101  

000100010011

001010010101 000101010111 001111101100

 

+

000100000001

+

01100110

001000010100

Section 2-11 Digital Codes  

010001010010

55. The Gray code makes only one bit change at a time when going from one number in the  sequence to the next number.  

 Gray for 11112 = 1000  

 Gray for 00002 = 0000  

56. (a) 1 + 1 + 0 + 1 + 1 Binary (b) 1 + 0 + 0 + 1 + 0 + 1 + 0 Binary  1 0 1 1 0 Gray 1 1 0 1 1 1 1 Gray  

 (c) 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 Binary   1 0 0 0 1 1 0 0 1 1 0 0 1 Gray

57. (a) 1 0 1 0 Gray (b) 0 0 0 1 0 Gray  1 1 0 0 Binary 0 0 0 1 1 Binary

 (c) 1 1 0 0 0 0 1 0 0 0 1 Gray

 1 0 0 0 0 0 1 1 1 1 0 Binary

58. (a) 1 → 00110001 (b) 3 → 00110011   (c) 6 → 00110110 (d) 10 → 0011000100110000   (e) 18 → 0011000100111000 (f) 29 → 0011001000111001   (g) 56 → 0011010100110110 (h) 75 → 0011011100110101   (i) 107 → 001100010011000000110111

20  

Chapter 2  

59. (a) 0011000 → CAN (b) 1001010 → J

 (c) 0111101 → = (d) 0100011 → #

 (e) 0111110 → > (f) 1000010 → B

60. 1001000 1100101 1101100 1101100 1101111 0101110 0100000   H e l l o . #  

 1001000 1101111 1110111 0100000 1100001 1110010 1100101   H o w # a r e  

 0100000 1111001 1101111 1110101 0111111  

 # y o u ?  

61. 1001000 1100101 1101100 1101100 1101111 0101110 0100000   48 65 6C 6C 6F 2E 20  

 1001000 1101111 1110111 0100000 1100001 1110010 1100101   48 6F 77 20 61 72 65   0100000 1111001 1101111 1110101 0111111  

 20 79 6F 75 3F  

62. 30 INPUT A, B  

 

 3 0110011 3316 

 0 0110000 3016 

 SP 0100000 2016 

 I 1001001 4916 

 N 1001110 4E16 

 P 1010000 5016 

 U 1010101 5516 

 T 1010100 5416 

 SP 0100000 2016 

 A 1000001 4116 

 , 0101100 2C16 

 B 1000010 4216 

Section 2-12 Error Detection Codes  

63. Code (b) 011101010 has five 1s, so it is in error.  

64. Codes (a) 11110110 and (c) 01010101010101010 are in error because they have an even  number of 1s.  

65. (a) 1 10100100 (b) 0 00001001 (c) 1 11111110

21

Chapter 2  

66. (a) 1100

(b) 1111

(c) 100011100

+

1011 0111

+

0100 1011

+

 10011001 110000101

67. (a) 1100

(b) 1111

 (c) 100011100

+

0111 1011

+

1011 0100

+

110000101 010011001

 In each case, you get the other number.  

68. 101100100000 1010

1001

1010

1100

1010

1100

1010

1100

1010

1100

1010

Remainder 0110 =

Append remainder to data.

101100100110

1010

1001

1010

1100

1010

1101

1010

1111

1010

1010

1010

0000

CRC is 101100100110.

69. Error in MSB of transmitted CRC:  

001100100110

1010

1001

1010

1100

1010

1101

1010

1110

1010

1000

1010

1011

1010

10

 Remainder is 10, indicating an error.

22  

CHAPTER 3  

LOGIC GATES

Section 3-1 The Inverter  

1. See Figure 3-1.  

2. B: LOW, C: HIGH, D: LOW, E: HIGH, F: LOW

3. See Figure 3-2.  

FIGURE 3-2

Section 3-2 The AND Gate

4. See Figure 3-3.  

FIGURE 3-3  

23  

Chapter 3  

5. See Figure 3-4.  6. See Figure 3-5.  7. See Figure 3-6.  

FIGURE 3-4  

FIGURE 3-5  

FIGURE 3-6

24  

Chapter 3  

8. See Figure 3-7.  

FIGURE 3-7  

Section 3-3 The OR Gate

9. See Figure 3-8.  10. See Figure 3-9.  

A  B  

X  

A  B  C  

X  

FIGURE 3-8  

FIGURE 3-9

25  

Chapter 3  

11. See Figure 3-10.  

12. See Figure 3-11.  

13. See Figure 3-12.  14.  

FIGURE 3-10  

FIGURE 3-11  

FIGURE 3-12

A B C

X

0  

0  

0  

1  

0  

0  

0  

1  

0  

1  

1  

0  

0  

0  

1  

1  

0  

1  

0  

1  

1  

1

1  

1  

0  

1  

1  

1  

1  

1  

1  

1

26  

Chapter 3  

Section 3-4 The NAND Gate  

15. See Figure 3-13.  

FIGURE 3-13  

16. See Figure 3-14.  17. See Figure 3-15.  

FIGURE 3-14  

FIGURE 3-15

27  

Chapter 3  

18. See Figure 3-16.  

 

FIGURE 3-16  

Section 3-5 The NOR Gate  

19. See Figure 3-17.  20. See Figure 3-18.  

FIGURE 3-17  

FIGURE 3-18

28  

Chapter 3  

21. See Figure 3-19.  22. See Figure 3-20.  

FIGURE 3-19  

FIGURE 3-20  

Section 3-6 The Exclusive-OR and Exclusive-NOR Gates  

23. The output of the XOR gate is HIGH only when one input is HIGH. The output of the OR gate  is HIGH any time one or more inputs are HIGH.  

 XOR = AB + AB

 OR = A + B

24. See Figure 3-21.  

FIGURE 3-21

29  

Chapter 3  

25. See Figure 3-22.  26. See Figure 3-23.  

FIGURE 3-22  

FIGURE 3-23

Section 3-7 Fixed-Function Logic  

27. The power dissipation of CMOS increases with frequency.  I I V ⎛ ⎞ + ⎛ ⎞ + ⎜ ⎟ = ⎜ ⎟ ⎝ ⎠ ⎝ ⎠ = 16.5 mW  

28. (a) P = CCH CCLCC1.6 mA 4.4 mA 5.5 V 2 2

 (b) VOH(min) = 2.7 V  

 (c) tPLH = TPHL = 15 ns  

 (d) VOL = 0.4 V (max)  

 (e) @ VCC = 2 V, tPHL = tPLH = 75 ns; @ VCC = 6 V, tPHL = tPLH = 13 ns  

30  

Chapter 3  

29. See Figure 3-24.  

FIGURE 3-24

30. Gate A can be operated at the highest frequency because it has shorter propagation delay times  than Gate B.  

31. PD = VCCIC = (5 V)(4 mA) = 20 mW  

32. ICCH = 4 mA; PD = (5 V)(4 mA) = 20 mW  

Section 3-8 Troubleshooting  

33. (a) NAND gate OK  

 (b) AND gate faulty  

 (c) NAND gate faulty  

 (d) NOR gate OK  

 (e) XOR gate faulty  

 (f) XOR gate OK  

34. (a) NAND gate faulty. Input A open.  

 (b) NOR gate faulty. Input B shorted to ground.  

 (c) NAND gate OK  

 (d) XOR gate faulty. Input A open.  

35. (a) The gate does not respond to pulses on either input when the other input is HIGH. It is  unlikely that both inputs are open. The most probable fault is that the output is stuck in  the LOW state (shorted to ground, perhaps) although it could be open.  

 (b) Pin 4 input or pin 6 output internally open.  

31  

Chapter 3  

36. The timer input to the AND gate is open. Check for 30-second HIGH level on this input when  ignition is turned on.  

37. An open seat-belt input to the AND gate will act like a constant HIGH just as if the seat belt  were unbuckled.  

38. Two possibilities: An input stuck LOW or the output stuck HIGH.  

Section 3-9 Programmable Logic  

39. X1 = AB

X2 = AB

X3 = AB

40. X1 = BCA

Row 1: blow and ,,,, CCBBA column fuses  

Row 2: blow and ,,,, CCBAA column fuses  

Row 3: blow and ,,,, CBBAA column fuses  

X2 = CAB

Row 4: blow , column fuses and ,,, CCBBA

Row 5: blow , and ,,, CCBAA column fuses  

Row 6: blow AABB C , , , , and column fuses  

X3 = CBA

Row 7: blow , column fuses and ,,, CCBBA

Row 8: blow , and ,,, CCBAA column fuses  

Row 9: blow , column fuses and ,,, CBBAA

Special Design Problems  

41. See Figure 3-25.  

FIGURE 3-25

32  

Chapter 3  

42. See Figure 3-26.  

FIGURE 3-26

43. Add an inverter to the Enable input line of the AND gate as shown in Figure 3-27.  FIGURE 3-27

44. See Figure 3-28.  

FIGURE 3-28

45. See Figure 3-29.  

FIGURE 3-29

33  

Chapter 3  

46. See Figure 3-30.  

FIGURE 3-30

47. See Figure 3-31.  

 

FIGURE 3-31

Multisim Troubleshooting Practice  

48. Input A shorted to output.  

49. Inputs shorted together.  

50. No fault.  

51. Output open.  

34  

CHAPTER 4  

BOOLEAN ALGEBRA AND LOGIC SIMPLIFICATION

Section 4-1 Boolean Operations and Expressions  

1. X = A + B + C + D

 This is an OR configuration.  

2. Y = ABCDE

3. X = ++ CBA

4. (a) 0 + 0 + 1 = 1 (b) 1 + 1 + 1 = 1  

 (c) 1 ⋅ 0 ⋅ 0 = 1 (d) 1 ⋅ 1 ⋅ 1 = 1  

 (e) 1 ⋅ 0 ⋅ 1 = 0 (f) 1 ⋅ 1 + 0 ⋅ 1 ⋅ 1 = 1 + 0 = 1  

5. (a) AB = 1 when A = 1, B = 1  

 (b) CBA = 1 when A = 1, B = 0, C = 1  

 (c) A + B = 0 when A = 0, B = 0  

 (d) ++ CBA = 0 when A = 1, B = 0, C = 1  

 (e) ++ CBA = 0 when A = 1, B = 1, C = 0  

 (f) A + B = 0 when A = 1, B = 0  

 (g) CBA = 1 when A = 1, B = 0, C = 0  

6. (a) X = (A + B)C + B  

A B C A + B (A + B)C X

0  

0  

0  

0  

0  

0  

0  

0  

0  

1  

0  

0  

1  

0  

1  

0  

1  

0  

1  

1  

1  

1  

1  

0  

0  

0  

1  

0  

0  

1  

1  

1  

1  

1  

0  

1  

1  

0  

1  

0  

1  

1  

1

1  

1  

1  

1  

1  

 (b) X = + )( CBA

A B C A + B X

0  

0  

0  

1  

0  

0  

0  

1  

1  

1  

0  

1  

0  

0  

0  

0  

1  

1  

0  

0  

1  

0  

0  

0  

0  

1  

0  

1  

0  

0  

1  

1  

0  

0  

0  

1  

1  

1  

0  

0

35  

Chapter 4  

 (c) X = CBA + AB

A B C CBA AB X

0  

0  

0  

0  

0  

0  

0  

0  

1  

0  

0  

0  

0  

1  

0  

0  

0  

0  

0  

1  

1  

0  

0  

0  

1  

0  

0  

0  

0  

0  

1  

0  

1  

1  

0  

1  

1  

1  

0  

0  

1  

1  

1  

1  

1  

0  

1  

1

 (d) X = (A + B)( A + B)  

 

A B A + B A + B X

0  

0  

0  

1  

0  

0  

1  

1  

1  

1  

1  

0  

1  

0  

0  

1  

1  

1  

1  

1

 (e) X = (A + BC) + CB )(

 

A B C A + BC + CB X

0  

0  

0  

0  

1  

0  

0  

0  

1  

0  

1  

0  

0  

1  

0  

0  

1  

0  

0  

1  

1  

1  

0  

0  

1  

0  

0  

1  

1  

1  

1  

0  

1  

1  

1  

1  

1  

1  

0  

1  

1  

1  

1  

1  

1  

1  

0  

0

Section 4-2 Laws and Rules of Boolean Algebra  

7. (a) Commutative law of addition  

 (b) Commutative law of multiplication  

 (c) Distributive law  

8. Refer to Table 4-1 in the textbook.  

 (a) Rule 9: = AA

 (b) Rule 8: AA = 0 (applied to 1st and 3rd terms)   (c) Rule 5: A + A = A

 (d) Rule 6: + AA = 1  

 (e) Rule 10: A + AB = A

 (f) Rule 11: AA B A +=+ B (applied to 1st and 3rd terms)

36  

Chapter 4  

Section 4-3 DeMorgan’s Theorems  

9. (a) A B AB ==+ BA

 (b) AB A B +=+= BA

 (c) ++ CBA = CBA

 (d) ABC ++= CBA

 (e) CBACBA )()( +=++=+ CBA

 (f) CDAB +++=+ DCBA

 (g) =+ CDABCDAB ++= DCBA ))(()()(

 (h) ( ))( DCBADCBA +=+++=++ DCBA

10. (a) DCBADCBA )()( ++=++=+ DCBA

 (b) ++=++=+ EFCDBAEFCDABEFCDAB )()()()(  = ++++ FEDCBA ))((

 (c) ( ) DABCDCBA ++++=++++ DCBADCBA  (d) ( +++ = )(()() +++ DCBADCBADCBADCBA )  = DCBADCBA ++++=++++ DCBADCBA

 (e) ++++=++ CDABFECDABCDABFECDAB )()())((  = + + CDABFECDAB ))(())((

 = ( ))( ++++ ABCDFEDCAB

11. (a) EFGABC + KLMHIJ ))(()()( +++= KLMHIJEFGABC  = KLMHIJEFGABC =+++ KLMHIJEFGABC ))()()((  = ( )( )( )( ++++++++ MLKJIHGFECBA )

 (b) ( =+++ =+ ))(())(() + BCCDCBABCCDCBABCCDCBA  = ( ) )1( ++=++=++ BCDCBABCDCBACBABCDCCBA  = + BCCBA

 (c) ++++ HGFEDCBA ))()()((

 = HGFEDCBA ))()(()( =++++ HGFEDCBA

37  

Chapter 4  

Section 4-4 Boolean Analysis of Logic Circuits  

12. (a) AB = X

 (b) A= X

 (c) A + B = X

 (d) A + B + C = X

13. See Figure 4-1.  

X

X

14. See Figure 4-2.  

38  

15. See Figure 4-3.  

Chapter 4  

FIGURE 4-3  

16. (a) See Figure 4-4(a).  

 (b) See figure 4-4(b).  

FIGURE 4-3

17. See Tables 4-1 and 4-2.  

 

Table 4-1 Table 4-2  

INPUTS

OUTPUT

VCR

CAMI

RDY

RECORD

0

0

0

0

0

0

1

1

0

1

0

0

0

1

1

1

1

0

0

0

1

0

1

1

1

1

0

1

1

1

1

1

39  

INPUTS

OUTPUT

RTS

ENABLE

BUSY

SEND

0

0

0

1

0

0

1

1

0

1

0

1

0

1

1

1

1

0

0

1

1

0

1

1

1

1

0

0

1

1

1

1

Chapter 4  

18. (a) X = A + B

A B X

0  

0  

0  

0  

1  

1  

1  

0  

1  

1  

1  

1

 (c) X = AB + BC

 

A B C X

0  

0  

0  

0  

0  

0  

1  

0  

0  

1  

0  

0  

0  

1  

1  

1  

1  

0  

0  

0  

1  

0  

1  

0  

1  

1  

0  

1  

1  

1  

1  

1

 (e) X = ++ CBBA ))((  

(b) X = AB

A B X

0  

0  

0  

0  

1  

0  

1  

0  

0  

1  

1  

1

(d) X = (A + B)C  

A B C X

0  

0  

0  

0  

0  

0  

1  

0  

0  

1  

0  

0  

0  

1  

1  

1  

1  

0  

0  

0  

1  

0  

1  

1  

1  

1  

0  

0  

1  

1  

1  

1

A B C A + B + CB X

0  

0  

0  

0  

1  

0  

0  

0  

1  

0  

1  

0  

0  

1  

0  

1  

0  

0  

0  

1  

1  

1  

1  

1  

1  

0  

0  

1  

1  

1  

1  

0  

1  

1  

1  

1  

1  

1  

0  

1  

0  

0  

1  

1  

1  

1  

1  

1

Section 4-5 Simplification Using Boolean Algebra  19. (a) A(A+ B) = AA + BB = A + AB = A(1 + B) = A  (b) )( AABAAABAA 0 AB =+=+=+ AB

 (c) +=+ BBCCBBC )( = C(1) = C

 

 (d) ( = ) +=+ BAAAABAAA A + (0)B = A + 0 = A  

 (e) )( +=++=++ CACBABBCACBACBABCACBA )1(  = BACBAACCACBA )()( +=+=+=+ CBCA

40  

Chapter 4  

20. (a) ( ))( +++=+++=++ CBBAACACBBAACAACABA  = ( )1()1 CBACBBCA +=+=+++ CBA

 (b) +++ 1( =+++= BAEDCCDCBAEDCBABCDACBABA )1()  = BA

 (c) ( ) +++=+++=++ ACBCAABACBAABACABAB  )1( ++=++=++=+++ BCACBCACBCAACBCABA )1(  = A + C

 (d) ( )( ) +++=++ CABAABACAABAABCABABAA

 = CABAB CAB )1(00 =+=+++ AB

 (e) )( ++=+++=+++ )( CBAABABCBCAABABCBAAB  = CABAB +=+ CAB

21. (a) ( )() ++++=++++ FDDDBEBDBDFDDEDBBD  = 0 FDBEBD ++=+++ FDBEBD

 (b) ( ) +=++=++++ DCBACBADCBACBACBADCBACBACBA  = DCBADCCBA )()( +=+=+ DBACBA

 (c) +++=+++ DBCBCBDBCBBBCB ))()(1())()((

 = ) =++ + + = + )(())(())(( + DBBCBDBBCBBDBCBB  = B(1 + C)(B + D) = B(B + D) = BB + BD = B + BD = B(1 + D) = B  (d) )()( CDABCDABABCD ++++=++ )()( CDBADCABABCD  = ++++ CDBCDADABCABABCD

 = ( ) )( ++++=++++ DABCABBABCDDABCABBAABCD  = )1( CDABCDDABCABCDDABCABACD )( +=+=++=+++ ABCD  (e) ACBCCABABC )]([ ABABC +=++ + ACBCCABC )(  = ABC + 0(BC + AC) = ABC

41  

Chapter 4  

22. First develop the Boolean expression for the output of each gate network and simplify.   (a) See Figure 4-5.  

FIGURE 4-5  

X = ( ) )( ++=++=++ DACCAABBADACCBABDCACBA

 = ( ) ACDCAB ++=++ DACCBBA

 (b) See Figure 4-6.  

FIGURE 4-6  

 X = ( )1 DACCBACBADACBA +=++=++ DACBA  (c) See Figure 4-7.  

FIGURE 4-7

 X = + DCBBA No further simplification is possible.  

42  

Chapter 4  

 (d) See Figure 4-8.  

 

FIGURE 4-8

 X = + DACBA No further simplification is possible.  

Section 4-6 Standard Forms of Boolean Expressions  

23. (a) ( ))( BABBBCACBCBA ++=+++=++ BABCAC  (b) ( ) CCBACCCBA +=+=+ CBAC

 (c) (A + C)(AB + AC) = AAB + AAC + ABC + ACC = AB + AC + ABC + ACC   = (AB + AC)(1 + C) = AB + AC

24. (a) ( ) CDBAABCDBACDAB CDCD ++=++=++ CDCDBAAB  = ( )1 CDBAAB +=+ CDAB

 (b) ( = ) ABBDCBABBDCBAB 0 +=+=+ ABD ABD  (c) ])([ +++=+++ )( BDCBABCADCBACBA

 = )1( ++=+++=+++ CBDADCBBDBCADCBBDABCA )1(  = A + BD

25. (a) The domain is A, B, C

 The standard SOP is: +++ BCAABCCBACBA

 (b) The domain is A, B, C

 The standard SOP is: ++ CBACBAABC

 (c) The domain is A, B, C

 The standard SOP is: ++ CBACABABC

26. (a) AB + CD = ABCD ++++++ CDBABCDACDBADCABDCABDABC  (b) ABD = + DCABABCD

 (c) A + BD = +++++ DCABDCABCDBADCBADCBADCBA  + +++ BCDADCBAABCDDABC

43  

Chapter 4  

27. (a) +++ BCAABCCBACBA : 101 + 100 + 111 + 011  

 (b) ++ CBACBAABC : 111 + 101 + 001  

 (c) ++ CBACABABC : 111 + 110 + 101  

28. (a) ABCD ++++++ CDBABCDACDBADCABDCABDABC :  1111 + 1110 + 1101 + 1100 + 0011 + 0111 + 1011  

 (b) + DCABABCD : 1111 + 1101  

 (c) +++++ DCABDCABCDBADCBADCBADCBA

 + +++ BCDADCBAABCDDABC :

 1000 + 1001 + 1010 + 1011 + 1100 + 1101 + 1110 + 1111 + 0101 + 0111  

29. (a) )(( )( ++++++++ CBACBACBACBA ))(

 (b) )(( )( )( ++++++++++ CBACBACBACBACBA ))(

 (c) )(( )( )( ++++++++++ CBACBACBACBACBA ))(

30. (a) ( )( )( )( )( +++++++++++++++ DCBADCBADCBADCBADCBA )  ( )( )( )( ++++++++++++ DCBADCBADCBADCBA ) (b) ( )( )( )( ++++++++++++ DCBADCBADCBADCBA )

( ) A B C DA B C DA B C DA B C DA B C D +++ +++ +++ +++ +++ ( )( )( )( ) ( )( )( )( )( +++++++++++++++ DCBADCBADCBADCBADCBA ) (c) ( )( )( )( ++++++++++++ DCBADCBADCBADCBA )

( )( ++++++ DCBADCBA )

Section 4-7 Boolean Expressions and Truth Tables  

31. (a) Table 4-3 (b) Table 4-4

A B C

X

0  

0  

0  

0  

0  

1  

0  

1  

0  

0  

1  

1  

1  

0  

0  

1  

0  

1  

1  

1  

0  

1  

1  

1

0  

0  

1  

0  

0  

1  

0  

1

44  

X Y Z

Q

0  

0  

0  

0  

0  

1  

0  

1  

0  

0  

1  

1  

1  

0  

0  

1  

0  

1  

1  

1  

0  

1  

1  

1

1  

1  

0  

1  

0  

1  

1  

0

Chapter 4  

32. (a) Table 4-5 (b) Table 4-6  

A B C D

X

0  

0  

0  

0  

0  

0  

0  

1  

0  

0  

1  

0  

0  

0  

1  

1  

0  

1  

0  

0  

0  

1  

0  

1  

0  

1  

1  

0  

0  

1  

1  

1  

1  

0  

0  

0  

1  

0  

0  

1  

1  

0  

1  

0  

1  

0  

1  

1  

1  

1  

0  

0  

1  

1  

0  

1  

1  

1  

1  

0  

1  

1  

1  

1

1  

0  

0  

0  

0  

1  

1  

0  

0  

1  

0  

0  

0  

0  

0  

0

W X Y Z

Q

0  

0  

0  

0  

0  

0  

0  

1  

0  

0  

1  

0  

0  

0  

1  

1  

0  

1  

0  

0  

0  

1  

0  

1  

0  

1  

1  

0  

0  

1  

1  

1  

1  

0  

0  

0  

1  

0  

0  

1  

1  

0  

1  

0  

1  

0  

1  

1  

1  

1  

0  

0  

1  

1  

0  

1  

1  

1  

1  

0  

1  

1  

1  

1

0  

0  

0  

0  

0  

0  

0  

1  

0  

0  

0  

1  

0  

1  

1  

1

33. (a) ++++=+++ CBACBACABCBABCACBACACABBA

 (b) X +++ = + + + Y Z WZ XYZ W XY Z W XYZ W XY Z W XYZ  + +++ ZYXWZYXWZXYWZYXW  + ++++ WXYZZWXYZYWXYZXWZYXW

 Table 4-7 Table 4-8

A B C

X

0  

0  

0  

0  

0  

1  

0  

1  

0  

0  

1  

1  

1  

0  

0  

1  

0  

1  

1  

1  

0  

1  

1  

1

1  

0  

1  

1  

0  

1  

1  

0

45  

W X Y Z

Q

0  

0  

0  

0  

0  

0  

0  

1  

0  

0  

1  

0  

0  

0  

1  

1  

0  

1  

0  

0  

0  

1  

0  

1  

0  

1  

1  

0  

0  

1  

1  

1  

1  

0  

0  

0  

1  

0  

0  

1  

1  

0  

1  

0  

1  

0  

1  

1  

1  

1  

0  

0  

1  

1  

0  

1  

1  

1  

1  

0  

1  

1  

1  

1

1  

1  

1  

1  

0  

1  

1  

0  

1  

1  

1  

1  

0  

1  

1  

1

Chapter 4  

34. (a) Table 4-9 (b) Table 4-10  

A B C

X

0  

0  

0  

0  

0  

1  

0  

1  

0  

0  

1  

1  

1  

0  

0  

1  

0  

1  

1  

1  

0  

1  

1  

1

0  

1  

0  

1  

1  

1  

1  

0

A B C D X

0  

0  

0  

0  

0  

0  

0  

1  

0  

0  

1  

0  

0  

0  

1  

1  

0  

1  

0  

0  

0  

1  

0  

1  

0  

1  

1  

0  

0  

1  

1  

1  

1  

0  

0  

0  

1  

0  

0  

1  

1  

0  

1  

0  

1  

0  

1  

1  

1  

1  

0  

0  

1  

1  

0  

1  

1  

1  

1  

0  

1  

1  

1  

1

1  

1  

1  

1  

1  

0  

0  

1  

1  

0  

0  

1  

1  

1  

1  

1

35. (a) Table 4-11 (b) Table 4-12  

A B C

X

0  

0  

0  

0  

0  

1  

0  

1  

0  

0  

1  

1  

1  

0  

0  

1  

0  

1  

1  

1  

0  

1  

1  

1

0  

0  

0  

1  

1  

1  

1  

1

36. (a) X = +++ ABCCBACBACBA

A B C D X

0  

0  

0  

0  

0  

0  

0  

1  

0  

0  

1  

0  

0  

0  

1  

1  

0  

1  

0  

0  

0  

1  

0  

1  

0  

1  

1  

0  

0  

1  

1  

1  

1  

0  

0  

0  

1  

0  

0  

1  

1  

0  

1  

0  

1  

0  

1  

1  

1  

1  

0  

0  

1  

1  

0  

1  

1  

1  

1  

0  

1  

1  

1  

1

1  

0  

1  

1  

0  

0  

0  

0  

1  

0  

0  

1  

1  

1  

1  

1

 X = )(( )( ++++++++ CBACBACBACBA ))(

 (b) X = ++ ABCCBACAB

 X = )(( )( )( ++++++++++ CBACBACBACBACBA ))(  (c) X = ++++++ DCABDCBADBCADCBACDBADCBADCBA  X = ( )( )( )( )( +++++++++++++++ DCBADCBADCBADCBADCBA )  ( )( )( )( ++++++++++++ DCBADCBADCBADCBA )

46  

Chapter 4  

 (d) X = ++++++ ABCDDCABCDBABCDADCBADCBADCBA  X = ( )( )( )( )( +++++++++++++++ DCBADCBADCBADCBADCBA )  ( )( )( )( ++++++++++++ DCBADCBADCBADCBA )

Section 4-8 The Karnaugh Map  

37. See Figure 4-9.  

38. See Figure 4-10.  

39. See Figure 4-11.  

  FIGURE 4-9 FIGURE 4-10 FIGURE 4-11  

Section 4-9 Karnaugh Map SOP Minimization  

40. See Figure 4-12.  FIGURE 4-12

47  

Chapter 4  

41. See Figure 4-13.  

X DF += EF

FIGURE 4-13

42. (a) ( ) +++=++ ABCCBACCABABCCBAAB

 = +++ ABCCBACABABC

 = ++ CABCBAABC

 (b) ++++=++++=+ )())(()())(( BCAACCBAABBCAACCBBABCA  = +++++ ABCBCACBACBACABABC

 = ++++ BCACBACBACABABC

 (c) +++ DBCADCBDACDCBA

 = ( = )() +++++ DBCADCBAACDBBADCBA

 = ++=++ DBCADCBADCABDCBADABCDCBA

 (d) ++++ ABCDDCBCDDCBABA

 = ( ))( )())(( +++++++++ ABCDDCBAACDBBAADCBADDCCBA  = +++++++ BCDACDBAABCDDCBAABCDDABCDCBADCBA   ++++ ABCDDCBADCABCDBA

 = ++++++++ DCBADCABCDBABCDACDBAABCDDABCDCBADCBA  = ABCDDCABCDBADCBADCBABCDADCBACDBA ++++++++ DABC

48  

Chapter 4  

43. See Figure 4-14.  

FIGURE 4-14  

44. See Figure 4-15.  

FIGURE 4-15

49  

Chapter 4  

45. Plot the 1’s from Table 4-11 in the text on the map as shown in Figure 4-16 and simplify.  

FIGURE 4-16  

46. Plot the 1’s from Table 4-12 in the text on the map as shown in Figure 4-17 and simplify.  FIGURE 4-17  

47. See Figure 4-18.  

FIGURE 4-18

50  

Chapter 4  

Section 4-10 Five-Variable Karnaugh Maps  

48. X = + ABCDE A BCDE.

 See Figure 4-19.  

FIGURE 4-19

49. See Figure 4-20.  

FIGURE 4-20  

51  

Chapter 4  

50. See Figure 4-21.  

FIGURE 4-21

Section 4-11 Describing Logic with an HDL  

51. entity AND_OR is  

 port (A, B, C, D, E, F, G, H, I: in bit; X: out bit);  

end entity AND_OR;  

architecture Logic of AND_OR is

begin

 X <= (A and B and C) or (D and E and F) or (G and H and I);  end architecture Logic;  

52. The VHDL program:  

entity SOP is  

 port (A, B, C: in bit; X: out bit);  

end entity SOP;  

architecture Logic of SOP is  

 begin

 Y <= (A and not B and C) or (not A and not B and C) or  

 (A and not B and not C) or (not A and B and C);  

end architecture Logic;

System Application Activity  

53. An LED display is more suitable for low-light conditions because LEDs emit light and LCDs  do not.  

54. The purpose of the invalid code detector is to detect the codes 1010, 1011, 1100, 1101, 1110,  and 1111 to activate the display for letters.  

52  

Chapter 4  

55. The standard SOP expression for segment c is:  

c = HHHH HHHH HHHH 3210 3210 3210 + +

 This expression is minimized in Figure 4-22.  

The standard expression requires three 4-input AND gates, one 3-input OR gate, and 3 inverters.  The minimum expression requires two 2-input AND gates, one 2 input OR gate, and 2 inverters.  

FIGURE 4-22  

56. The standard SOP expression for segment d is:  

d = HHHH HHHH HHHH HHHH 3210 3210 3210 3210 +++

 This expression is minimized in Figure 4-23.  

The standard expression requires four 4-input AND gates, one 4-input OR gate, and 3 inverters.  The minimum expression requires one 2-input AND gates, one 3-input AND gate, one 2-input  OR gate, and 2 inverters.

FIGURE 4-23  

53  

Chapter 4  

The standard SOP expression for segment e is:  

e = HHHH HHHH HHHH HHHH HHHH 3210 3210 3210 3210 3210 ++++  This expression is minimized in Figure 4-24.  

The standard expression requires five 4-input AND gates, one 5-input OR gate, and 3 inverters.  The minimum expression requires one 3-input AND gate.  

FIGURE 4-24  

The standard SOP expression for segment f is:  

f = HHHH HHHH HHHH HHHH 3210 3210 3210 3210 +++

 This expression is minimized in Figure 4-25.  

The standard expression requires four 4-input AND gates, one 4-input OR gate, and 3 inverters.  The minimum expression requires one 2-input AND gate.

FIGURE 4-25  

54  

Chapter 4  

The standard SOP expression for segment g is:  

g = HHHH HHHH HHHH HHHH 3210 3210 3210 3210 +++

 This expression is minimized in Figure 4-26.  

The standard expression requires four 4-input AND gates, one 4-input OR gate, and 3 inverters.  The minimum expression requires one 2-input AND gates, one 3-input AND gate, one 2 input  OR gate, and 2 inverters.

FIGURE 4-26  

Special Design Problems  

57. Connect the OR gate output for each segment to an inverter and then use the inverter output to  drive the segment with a HIGH.  

58. See Figure 4-27. F = 1111  

 The expression for segment a to include the letter F is:  

a = HHHH HHHH HHHH HHHH 3210 3210 3210 3210 +++

 The expression is minimized in Figure 4-27.  

 

FIGURE 4-27  

55  

Chapter 4  

59. See Figure 4-28. Segment b is used for letters A and d.  

b = HHHH HHHH 3210 3210 +

FIGURE 4-28  

See Figure 4-29. Segment c is used for letters A, b, and d.  

c = HHHH HHHH HHHH 3210 3210 3210 + +

FIGURE 4-29

56  

Chapter 4  

 See Figure 4-30. Segment d is used for b, C, d, and E.  

d = HHHH HHHH HHHH HHHH 3210 3210 3210 3210 +++

FIGURE 4-30  

 See Figure 4-31. Segment e is used for A, b, C, d, E, and F.  

e = HHHH HHHH HHHH HHHH HHHH HHHH 3210 3210 3210 3210 3210 3210 +++++

Since segment e is active-LOW for all letters, e = 0.

FIGURE 4-31  

57  

Chapter 4  

 See Figure 4-32. Segment f is used for A, b, C, E, and F.   f = HHHH HHHH HHHH HHHH HHHH 3210 3210 3210 3210 3210 ++++

FIGURE 4-32  

 See Figure 4-33. Segment g is used in A, b, d, E, and F.  

g = HHHH HHHH HHHH HHHH HHHH 3210 3210 3210 3210 3210 ++++

FIGURE 4-33

58  

Chapter 4  

60. The invalid code detector must disable the display when any numerical input (0-9) occurs. A  HIGH enables the display and a LOW disables it. A circuit that detects the numeric codes and  produces a LOW is shown in Figure 4-34.  

FIGURE 4-34

Multisim Troubleshooting Practice  

61. Input A inverter output open.  

62. Input A of segment e OR gate open.  

 

63. Segment b OR gate output open.  

59  

CHAPTER 5  

COMBINATIONAL LOGIC ANALYSIS  

Section 5-1 Basic Combinational Logic Circuits  

1. See Figure 5-1.  

2. (a) X = ++ ACABA

 (b) X = ++ DDBCDABA

3. (a) X = ABB  

(b) X = AB + B

 (c) X = A + B

 (d) X = (A + B) + AB

 (e) X = ABC

 (f) X = ++ CBBA ))((

4. See Figure 5-2 for the circuit corresponding to each expression.  

 (a) X = (A + B)(C + D) = AC + AD + BC + BD

 (b) X = =+ ( )())( +=+= CDBCDACCDBACDCABCDCAB

 (c) X = (AB + C)D + E = ABD + CD + E

 (d) X = ( ))(()() ++=+++=++=++ DBADBCBADBCBADBCBA  (e) X = )()( ++=++=++ EDCABDEDCABEDCAB

 (f) X = +++=++=++ GHEFCDABGHEFCDABGHEFCDAB )()())(())((  = + GHEFCDAB ))(())((

 = ))(())(( +++++++=+++++ HFHEGFGEDBDACBCAHGFEDCBA

60  

Chapter 5  

5. (a) X = ABB  

A B X

0 0 1  

0 1 0  

0 0 0  

1  

1  

1

 (d) X = (A + B) + AB  

A B X

0 0  

0 1  

0 1  

1 1  

0 1  

1 1

(b) X = AB + B

A B X

0 0  

0 1  

0 1  

1 1  

0 1  

0 1

(e) X = ABC

A B C X

1 1  

0 1  

0 0  

0 0  

1 0 1  

0 1 0  

1 1 0  

0 0 1  

1 1 1

1 0 1  

0 1 1  

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61  

(c) X = A + B

A B X

0 0  

0 1  

1 1  

1 1  

0 1  

0 1

(f) X = ++ CBBA ))((

A B C X

0 0  

0 1  

0 0  

0 0  

0 1 1  

0 1 0  

1 1 0  

0 0 1  

1 0 1

1 0 1  

0 1 1  

1 1 1  

Chapter 5  

6. (a) X = (A + B)(C + D) (b) X = + CDCAB

A B C D X

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A B C D X

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(c) X = (AB + C)D + E (d) X = ( ))( ++ DBCBA

A B C D E X

A B C D E X

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62  

A

B

C

D

X

0  

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Chapter 5  

(e) X = ( ) ++ EDCAB(f) X = ++ GHEFCDAB ))((

A B C D E X

A B C D E X

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7. X = =+ ++= BABABABABABA ))(())(( Section 5-2 Implementing Combinational Logic  

A

B

C

D

E

F

G

H

I

0  

X  

0  

X  

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X  

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X

X  

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X  

X  

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X  

X

X

X  

0  

0  

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X  

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0  

0  

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0

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0

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For all other entries X = 0.  

X = don’t care  

An abbreviated table is shown because  there are 256 combinations.  

8. Let G = guard, S = switch, M = motor temp, and P = power. See Figure 5-3.  P = GS MS +

63  

Chapter 5  

9. X = ABCD EFGH +

10. See Figure 5-4.  

FIGURE 5-4

64  

Chapter 5  

11. See Figure 5-5.  

FIGURE 5-5

65  

Chapter 5  

12. See Figure 5-6.  

FIGURE 5-6  

13. X = ++++ ABCCABCBACBACBA

 See Figure 5-7.  

FIGURE 5-7

66  

Chapter 5  

14. X = CDBADCBADCBADCBADCBACDBADCBA +++++++ ABCD  See Figure 5-8.  

FIGURE 5-8  

15. X = AB + ABC = AB(1 + C) = AB  

 Since C is a don’t care variable, the output depends only on A and B as shown by the two variable truth table above which is implemented with the AND gate in Figure 5-9.  

X  

FIGURE 5-9

67  

Chapter 5  

16. X = +=+=+=++ ))(())(())(())(( CCBBACCBABCCBABCCBAB  = ( ) ACBCBCBACCBCBA )1( =+=+=+ CB

 See Figure 5-10.  

X  

FIGURE 5-10  

17. (a) X = + CBAB

The output is dependent  only on B and C. The value  of A does not matter. The  NOR gate behaves as a  negative-AND.  

 No simplification. See Figure 5-11.  

X = + AB BC

FIGURE 5-11  

 (b) X = A B C AB AC ( ) += +

 No simplification. Equation can be expressed in another form, as indicated   in Figure 5-12.  

 

X  

FIGURE 5-12

 (c) X = +=+ BBABAAB )( = A  

 A direct connection from input to output. No gates required.  

68  

Chapter 5  

(d) X = ( ) ++++=++ GBBEFCBAGEFBABC  = GBBEFCA ++++=++++ GEFBCA

 See Figure 5-13.  

FIGURE 5-13  

(e) X = A(BC(A + B + C + D)) = ABCA + ABCB + ABCC + ABCD  = ABC + ABC + ABC + ABCD = ABC + ABC(1 + D)   = ABC + ABC = ABC

 See Figure 5-14.  

FIGURE 5-14  

(f) X = ( + ())( +=+ ++ CBAFGEBEDBCCABFGEEDCB ))(  = +++ FGEBCEDBCFGEBAEDBCA

 = ( )1 +++ FGEBCFGEBAAEDBC

 = + + FGEBCFGEBAEDBC

 See Figure 5-15.  

FIGURE 5-15

69  

Chapter 5  

18. (a) X = )(( ++++ BEACDBACDBA ) = ++ ( ++ EBACDBACDBA )  = ( ) +++=+++ EBACDBBAEBABACDBA  = ( )1 CDEBACDEBAA +=++=++ CDA

 See Figure 5-16.  

FIGURE 5-16  

 (b) X = +++=++ FAEFDDCABAFFEDDCAB  = +++ EDFDCBA

 See Figure 5-17.  

FIGURE 5-17  

 (c) X = ())(( ECDCBAEDCBA ) ++=++=++ ECADCABA  

 See Figure 5-18.  

FIGURE 5-18

70  

Chapter 5  

19. The SOP expressions are developed as follows and the resulting circuits are shown in Figure 5-19.  

 (a) X = (A + B)(C + D) = AC + AD + BC + BD

 (b) X = =+ ( )())( CCDBACDCABCDCAB +=+= CDBCDA

 (c) X = (AB + C)D + E = ABD + CD + E

 (d) X = ( )( ) ( )( ) A B BC D A B BC D A B BC D + + = + + =++ +  

 = ( )1 DCBA ++=+++ DBA

 (e) X = ( )() EDCABEDCAB ++=++=++ EDCABD

 (f) X = ()())(())(( +++=++=++ GHGEFCDABGHEFCDABGHEFCDAB )  = ( )( ) ( )( ) ( )( ) ( )( ) AB CD EF GH A B C D E F G H + =+ +++ +

 = AC BC AD BD EG FG E H F H ++++++ +

FIGURE 5-19

71  

Chapter 5  

Section 5-3 The Universal Property of NAND and NOR Gates  20. See Figure 5-20.  

FIGURE 5-20  

21. X = ( ))( ++ CCBAB

 See Figure 5-21.  

X  

))(( ++= CCBABX

FIGURE 5-21  

22. See Figure 5-22.  

FIGURE 5-22

72  

Chapter 5  

23. See Figure 5-23.  

FIGURE 5-23  

Section 5-4 Combinational Logic Using NAND and NOR Gates  

24. (a) X = ABC

 See Figure 5-24.  

(b) X = ABC

 See Figure 5-25.  

X X  

FIGURE 5-24 FIGURE 5-25  

 (c) X = A + B  See Figure 5-26.  

(d) X = ++ CBA

 See Figure 5-27.  

X

FIGURE 5-26 FIGURE 5-27

73  

Chapter 5  

 (e) X = + CDAB

 See Figure 5-28.  

FIGURE 5-28  

 (f) X = (A + B)(C + D)  

 See Figure 5-29.  

FIGURE 5-29  

(g) X = ++ BCEABDECAB ])([

 See Figure 5-30.  

 See Figure 5-29.  X 

FIGURE 5-30

74  

Chapter 5  

25. (a) X = ABC

 See Figure 5-31.    

(b) X = ABC

See Figure 5-32.  

X X  

FIGURE 5-31 FIGURE 5-32  

(c) X + A + B

 See Figure 5-33.  

(d) X = ++ CBA

See Figure 5-34.  

X X  

FIGURE 5-33 FIGURE 5-34  

(e) X = + CDAB

See Figure 5-35.  

X  

FIGURE 5-35  

(f) X = (A + B)(C + D)  

See Figure 5-36.  

X  

FIGURE 5-36

75  

Chapter 5  

(g) X = ++ BCEABDECAB ])([

See Figure 5-37.  

X  

FIGURE 5-37  

26. (a) X = AB

 See Figure 5-38.  

(b) X = A + B

 See Figure 5-39.  

X X  

FIGURE 5-38 FIGURE 5-39  

 (c) X = AB + C   See Figure 5-40.  

(d) X = ABC + D

 See Figure 5-41.  

X X  

FIGURE 5-40 FIGURE 5-41

76  

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