Class Note for ECE 380 at UA-Digital Logic(13)
Class Note for ECE 380 at UA-Digital Logic(13)
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This 3 page Class Notes was uploaded by an elite notetaker on Friday February 6, 2015. The Class Notes belongs to a course at University of Alabama - Tuscaloosa taught by a professor in Fall. Since its upload, it has received 15 views.
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Date Created: 02/06/15
ECE380 Digital Logic Number Representation and Arithmetic Circuits Fast Adder Designs Tradeoffs and Examples Electrical amp Computer Engineering Dr D J Jackson Lecture 18 1 Performance issues 0 Addition amp subtraction are fundamental operations preformed frequently in the course of a computation Performance speed of these operations has a strong impact on the overall performance of a computer 0 Consider again the addersubtractor unit yn l Y1 yo 7 Add ub Ll con rol xii iiquot S7 V V 97 n bit adder C0 1 l l 5m 51 50 Electrical amp Computer Engineering Dr D J Jackson Lecture 18 2 Addersubtractor performance c We are interested in the largest delay from the time the operands X and Yare presented as inputs until the time all bits of the sum S and the final carryout cn are valid 0 Assume the adder is constructed as a ripple carry adder and that each bit in the adder is constructed as a full adder as shown Ci1 Electrical amp Computer Engineering Dr D J Jackson Lecture 18 3 Addersubtractor performance o The delay for the carryout in this circuit At is equal to two gate delays 0 From the discussion of the ripplecarry adder we know that the final result of an nbit addition is valid after a delay of nAt This is 2n gate delays 0 In addition to the delay in the ripplecarry path there is also a one gate delay introduced in the XOR gates that provide either the true or complement form of Yto the adder inputs The total gate delay for the addersubtractor circu t is 2n1 o The speed of any circuit is limited by the longest delay along the paths through the circuit The longest delay is called the criticalpathdelay and the path that causes this delay is called the critical path Electrical amp Computer Engineering Dr D J Jackson Lecture 18 4 Carrylookahead adder c To reduce delay caused by the effect of carry propagation through the ripple carry adder we will attempt to evaluate quickly for each adder stage whether the carry in from the previous stage will have a value of O or 1 If we can do this quickly we can improve the performance of the complete adder o Essentially we are attempting to reduce the critical path delay Electrical amp Computer Engineering Dr D J Jackson Lecture 18 5 Carrylookahead adder 0 Recall the carryout function for stage I can be realized as CilXiyiXiCiini Ci1 iyiXiyiCi 39 LEt giXiyiand piXiyil SO Ci1 gipiCi o The function g1 when both xand y are 1 regardless of the incoming carry c Since in this case stage i is guaranteed to generate a carry out 9 is called the generate function 0 The function p1 when either Xand y are 1 A carryout is produced if c1 The effect is that the carry in of 1 is propagated through stage i p is called the propagate funct on Electrical amp Computer Engineering Dr D J Jackson Lecture 18 6 Carrylookahead CLA adder 0 Let us generate an expression for the output carry of an nbit adder glVenr 5n gns1Pns1Cns1 and Cna1 gna2Pna26na2 therefore Cn gnrlpnrlgn72pn725n72 5n gm Pns1gns2 Pmpnszcnsz o The same expansion for other stages ending with stage 0 gives on gnopnognaz pnaipnazgnaodrpnopn72quotpigodrpnopnazuDoCo staunca AcomvmerEnglneerlng Dr D J Jackson taaunaiov Carrylookahead CLA adder carry generated in carry generamd in stage nsz and stage 0 and propagated propagamd through remaining through remaining stages stages ale 6n gnoDnognaz pnopnazgnaohpnopn72vigownopnnoupoCo T TT f carry generated in carry generated in stage quot3 and Innut carry cc last stage 39 propagated pmpagate j th h H ta through remaining quotmg a S ges stages accinca s conouia tnoinoonna Dr D J Jeclson taaunaioo Ripplecarry adder critical path 3 gate delays for c X 5 gate delays for c2 In general 2n1 delays Stage 1 Stage 0 for not ripplescarry adder 51 50 staunca AcomvmerEnglneerlng Dr D J Jackson taaunaios Carrylookahead critical path x y x y 3 gate delays for c 3 gate delays for c2 3 gate delays for CH c Total delay for nrbit Z CLA adder is 4 gate delays All g and p one delay All 9 two more delays One more delay for the sums s 5 0 accinca AEoNDmaEngmearlng Dr D J Jeclson Lacturei 1D Carrylookahead limitations o The expression for carry in a CLA adder c gnawnagnnz r PnniPnn nno r PnniPnn2 Pogownapna PuCu obviously results in a fast solution since it is only a 2 level ANDOR function 0 Fanin limitations may effectively limit the speed ofa CLA adder s Devices with known fanrin Iim tat ons such as an FPGA often include ded cated circuitry for implementation of fast adders o The complexity of an nbit CLA adder increases rapidly as 17 becomes large s To reduce this complexity we can use a hierarchical approach in designing large adders staunca AcomvmerEnglneerlng Dr D J Jackson taaunaioii 32bit adder design 0 Suppose we want to design a 32bit adder 0 Divide this adder into 4 blocks such that s Bts b are block 0 s Bts lo1er are block 1 s Bts bms are block 1 s Bts b3 are block 1 0 Each block can be constructed as an 8bit CLA adder s The carrysout signals from the four blocks are c5 C15 c and C32 0 There are 2 basic approaches for interconnecting these four blocks s Ripplescarry between blocks a Second level carryrlookahead circu t accinca AEoNDmaEngmearlng Dr D J Jeclson taaunaioiz Ripplecarry between blocks szinHn Xisrzavlsrza Xarlsvarls ern Y7rn C32 Block C Block cm Block CB Block cquot 3 2 1 0 SZJVSI 516723 5345 S77 seam AcomvmerEngmaymg Dr D J Jackson La urel 13 Second level carrylookahead circuit x x x 31724 y31 24 158y1578 7 0 y7 0 p Secondrlevel lookahead seam mm Engineering Dr D J Jaclsun Ledurel m Second level carrylookahead circuit 0 For the second level circuit PoP7P5p5pJp3p2p1po Go97P7QsP7PsgsP7P5P5P4P3P2P1go cEG0POcO c15 G1P1ca G1P1GOP1POcO c24 G2P2G1P2P1GOP2P1POCO c32 G3P3G2P3P2G1P3P2P1GOP3P2P1POcO seam AcomvmerEngmaymg Dr D J Jackson La urel 15 Hierarchical CLA analysis 0 Assuming a fanin constraint of four inputs the time to add two 32bit numbers involves five gate delays to develop the G and P terms three gate delays for the secondlevel lookahead and one delay XOR to produce the final sum bits Actually the final sum bit is computed after eight delays because c32 is not used to determine the sum bits The complete operation including overflow detection c31 c32 takes nine gate delays compared to 65 for the ripple carry adder seam mm Engineering Dr D J Jaclsun Laciurel ls
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