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# Class Note for ECE 380 at UA-Digital Logic(14)

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This 3 page Class Notes was uploaded by an elite notetaker on Friday February 6, 2015. The Class Notes belongs to a course at University of Alabama - Tuscaloosa taught by a professor in Fall. Since its upload, it has received 22 views.

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Date Created: 02/06/15
ECE380 Digital Logic Synchronous Sequential Circuits State Diagrams State Tables eemnca AcumvmerEngineying Dr D J Jackson LedureZTi Synchronous sequential circuits o Circuits where a clock signal is used to control operation are called synchronous sequential circuits 7 The term active clock edge refers to the clock edge that causes a change in state pos tive or negative 0 Realized using combinational logic and one or more flipflops 0 Two models for synchronous sequential circuits 7 Moore model circuit outputs depend only on the present slam of the circuit 7 Mealy model circu toutputs depend on the present sham of the circuit and the primary inputs 0 Sequential circuits are also called finite state machines FSM eemnca AEomDmaEngmesrmg Dr D J Jeclsun Lyman Moore versus Mealy machines w Combinational I n Combinational 4 circuit F39p p5 circut Q r 7 clock Moore state machine W combinational combinational Fllprflops gt Circuit Clrcu t 4 Q f Mealy state machine eemnca AcumvmerEngineying Dr D J Jackson LedureZTCl Basic design steps c We will introduce techniques for sequential circuit design via a simple example 0 Design a circuit that meets the following specifications The circuit has one input w and one output 2 All changes in the circuit occur on the positive edge of the clock signal Output z1 if the input w was 1 during the two immediately preceding clock cycles 0 From this specification it is obvious that 2 cannot depend solely of the value of w eemnca AEomDmaEngmesrmg Dr D J Jeclsun LedureZTA Sequences of signals o The example input and output sequence below aides in the description of the circuit Clock cycle to 3911 t2 t3 t4 5 ts t7 ta 9 E10 w 0 1 0 1 z 0 0 0 0 0 1 0 eemnca AcumvmerEngineying Dr D J Jackson LectureZT State diagram o The first step in designing an FSM is determining how many states are needed and which transitions are possible from one state to another No preset procedure for this The designer must think about what the circuit is to accomplish o A good beginning is to define a reset state that the circuit should enter when power is applied or when a reset signal is received eemnca AEomDmaEngmesrmg Dr D J Jeclsun Lecturesz State diagram o For our example assume the starting state is called A c As long as w0 the circuit should do nothing and 20 stance AcumvmerEnglneerlng ur in J Jackson LectureZTT State diagram c When wl the circuit should remember this by transitioning to a new state B o This transition should occur at the next positive edge of the clock signal reset ur in J Jeelson LectureZTE stance s Curvva Engineering State diagram c When in state B and wl the circuit should remember this by transitioning to a new state C stance AcumvmerEnglneerlng ur in J Jackson LectureZTS Complete state diagram Moore model state diagram stance AEoNDmaEngmearlng ur in J Jeelson LactureZTl State table o A state diagram describes circuit functionality but does not describe circuit implementation 0 Translation to a tabular form is necessary 0 The state table should contain a All transitions from each present state to each next state for all valuations of the input signals 7 The output 1 is specified w th respect to me present state Present Nextsbate 0utput state we wel z A A B 0 B A c 0 c A c 1 stance AcumvmerEnglneerlng ur in J Jackson La ureZTM State assignment o The states are defined in terms of variables A B and C 0 Each state is represented by a particular valuation of state variables 0 Each state variable is implemented with a flipflop 0 Since three states have to be realized it is sufficient to use two state variables Use y2y1 for the present state present state variables Use Y2Y1 for the next state next state variables stance AEoNDmaEngmearlng ur in J Jeelson LactureZTl Stateassigned table Present Ne State Output slate w0 w1 Z M YZY YZY A 00 00 01 0 01 00 10 0 c 10 00 10 1 11 dd dd d Note the addition of the y2y111 state Although it is not used it is needed for completeness Eemrica AEoNDmerEngmesnng Dr D J Jackson Lecture271 Nextstate and output maps o Kmaps are constructed from the state table for Circuit outputs z in this case Inputs for the flipflops nextstate Kmaps 0 Constructing the nextstate maps depends on the type of flipflop D T JK used for the implementation D is the most straightforward nextstate maps are constructed directly from the state table since Qt1QD T and JK implementations will be covered later Eemrica AEoNDmaEngmesnng Dr D J Jaclson Lecture271 State table and nextstate maps yayz W 00 01 11 10 Nextstate 0 0 0 d 0 Present 0 t t state w0 w1 Zpu 1 0 d 0 Y2Y1 Y2 Y2 Y1wv1 v2 A 00 00 01 0 var 01 00 10 0 W 00 01 11 10 c 10 00 10 1 0 0 0 d 0 11 dd dd d 1 o 1 Y2Wv1v2 Eemrica AEoNDmerEngmesnng Dr D J Jackson Lecture271 State table and output map Next state Present Out t state w0 w1 Z M YZY YZY A 00 00 01 0 01 00 10 0 10 00 10 1 11 dd dd d Eemrica AEoNDmaEngmesnng Dr D J Jaclson Lecture271 Circuit diagram um um Eemrica AEoNDmerEngmesnng Dr D J Jackson Lecture271 Timing diagram ClocngFUFlil le39Ul39 W lii I Lr t OHOHOH Eemrica AEoNDmaEngmesnng Dr D J Jaclson Lecture271

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