Class Note for ECE 380 at UA-Digital Logic(16)
Class Note for ECE 380 at UA-Digital Logic(16)
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This 3 page Class Notes was uploaded by an elite notetaker on Friday February 6, 2015. The Class Notes belongs to a course at University of Alabama - Tuscaloosa taught by a professor in Fall. Since its upload, it has received 20 views.
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Date Created: 02/06/15
Introduction to CAD tools ECE380 Digital Logic Introduction to Logic Circuits CAD Tools and VHDL o A CAD system usually includes the following tools Design entw Synthesis and optimization Simulation Physical design Seaan 5 some egmeenng Dr D J Jacison Leauresl Seaan 5 some egmeenng Dr D J Jacison LeaureSZ Design entry Design entry with truth tables o The process of entering into the CAD system a description of a circuit being designed is called design entry 0 Three common design entry methods Using truth tables I User ehters a truth tabie Th Diarh text format Or draws a waveform that represehts the desrred fuhct oha behawor Schematic capture User graphrcaHy enters a desrred ogrc crrcurt Hardware description languages User enters a programrmhg ahguagenhke descnptron of a desrred ogrc crcu t o Commonly use a waveform editor to enter a timing diagram that describes a desired functionality for a logic circuit 7 CAD system transforms thrs rhto equwa eht ogrc gates 7 Not appropnate for arge crrcurts but can be used for a smaH Tog c tunctron that rs to be part of a Targer crcurt Name T 100 Uns 200 Bus 3130 Bus x1 NPUT K2 NPUT f COME Seaan 5 some egmeenng Dr D J Jacison Leauresl Seaan 5 some egmeenng Dr D J Jacison LeaureSA Schematic capture Schematic capture Most common type of CAD tool Schematic refers to a diagram of a circuit in which circuit elemenis logic gates are shown as graphical symbols and connections between them are drawn as lines Tool provides a collection of symbols that represent gates of various types with different inputs and outpuis Alibrary Previously designed circuits can be represented with a graphical symbol and used in larger circuits Known as hierarchical design and provides a way of dealing with complexities of large circuits Name T mu uns 2mm Bus 3m uns x1 NPUT x2 NWT 1 COME Seaan 5 some egmeenng Dr D J Jacison Leaures Seaan 5 some egmeenng Dr D J Jacison Leauress Hardware description languages o A hardware description language HDL is similar to a computer program except that it is used to describe hardware 0 Common HDLs VHDL VHSIC Hardware Description Language Verilog Many others vendor specific 0 VHDL and Verilog are standards Offer portability across different CAD tools and different types of programmable chips tiaonca Acomvmer Engineering Dr D J Jackson LectureST Synthesis 0 Synthesis CAD tools perform the process of generating a logic circuit from some stated functional behavior 0 Translating compiling VHDL code into a network of logic gates is a part of synthesis 0 Not only will the CAD tool produce a logic circuit but it can also optimize that circuit s In terms of speed andor size logic optimization 7 Called logic synthesis or logic optimization 0 Finally technology mapping and layout synthesis physical design complete the synthesis process acclnca sconomatnonoonno Dr D J Jacison Lectures Simulation 0 Once designed it is necessaw to verify that the design circuit functions as expected 0 In a functional simulation the user specifies valuations of the circuits inputs and the CAD tool generates the outputs commonly in the form of a timing diagram 7 User verifies generated outputs against expected outpuls 0 Functional simulators assume the time needed for signals to propagate through the logic gates is negligible 7 For a real implemenladon this is not suffcient s Use a timing simulator to obtain accurate complete simulao39on tiaonca Acomvmer Engineering Dr D J Jackson LecturesS Introduction to VHDL 0 Designer writes a logic circuit description in VHDL source code 0 VHDL compiler translates this code into a logic circuit 0 Representation of digital signals in VHDL Logic signals in VHDL are represented as a data object VHDL includes a data type called BIT BIT objects can assume only two values 0 and 1 acclnca sconomatnonoonno Dr D J Jacison Lectures in Writing simple VHDL code 0 First step in writing VHDL code is to declare the input and output signals 0 Done using a construct called an entity Name of the entity Input and output signals ports defined ENTITY examplel IS PORT x1x2x3 7 IN BIT f OUT BIT END examplel Mode of the port Type of the port IN input OUT output tiaonca Acomvmer Engineering Dr D J Jackson LectureSM Writing simple VHDL code Name of the entity Input and output signals ports defined ENTITY examplel IS PORT x1x2x3 IN BIT f OUT BIT END examplel Mode of the port Type of the port IN input OUT output x1 x2 x3 acclnca sconomatnonoonno Dr D J Jacison Lectures 2 Writing simple VHDL code 0 The entity specifies the inputs and outputs for a circuit but does not dEcribe the circuit function Circuit functionality is specified using a VHDL construct called an architecture Arch tecture nam Entity used by LDgicFunc ARCHITECTURE LogicFunc or examplel lS BEGIN FltLgtlt1AND A2 or NOT x2 AND x3 END LogicFunc VHDL statement that describes the Elrmlt mncudnai ty amumouuvuorawnunnn a in mmquot mums p Complete VHDL code example x1 x2 ENTlTVexamplellS PORTgtlt1gtlt2gtlt3 lN an x3 r oUTaiT END example ARCHITECTURE LDgicFunc 0E example 15 mm R x AND x2 OR Nowz AND x3 END Lag prune amumouuvuorawmnnn a in mmquot mm m Boolean operators in VHDL VHDL nas builtrin support for the following operators a AND logical AND a OR logical OR a NOT logical NOT a NAND NOR XOR xNoR covered later Assignment operator lt a A variable dsdauy an Dutput should be assigned the resdu thhe lag c express an an the right nand side thhe operator VHDL does not assume any precedence or logic operators Use parentheses in expressions to determine precedence in VHDL a logic expression is called a Simple assignmentxtatement There are other types that Will be introduced that are useful for more complex circuits amumomworawnunni a in mmquot mums d Example VHDL code 0 Write the VHDL code entity and architecture constructs for the adder circuit Name the entity Add and name the architecture AddFunc 0 Write the VHDL code for the majority circuit Name the entity Majorityand name the architecture MajorityFunc an Lomvuor awnNW a in mmquot mm d
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