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# Class Note for ECE 380 at UA-Digital Logic(18)

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COURSE
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KARMA
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This 4 page Class Notes was uploaded by an elite notetaker on Friday February 6, 2015. The Class Notes belongs to a course at University of Alabama - Tuscaloosa taught by a professor in Fall. Since its upload, it has received 20 views.

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Date Created: 02/06/15
Masterslave D flipflop ECE380 Digital Logic Flip Flops Registers and Counters Flip Flops Consists of 2 gated D latches The first master changes its state while clock1 The second slave changes its state while clock0 Master Slave m s D D Q D Q Q Clock CkQ CkQ 5 38 transistors Elainel a Cunning Enunmng m n J helmquot Lemsz 1 z lmnul a calming Enunml39 nrnJJclsm Lain 251 Flipflops Masterslave D flipflop The gated latch circuits presented are level sensitive and can change states more than once during the active period of the clock signal Circuits storage elements that can change their state no more than once during a clock period are also useful 0 Two types of circuits with such behavior Masterslave flipflip Edgetriggered flipflop 0 When clock1 the master tracks the values of the D input signal and the slave does not change Thus Qm follows any changes in D and Q5 remains constant 0 When the clock signal changes to 0 the master stage stops following the changes in the D input signal 0 At the same time the slave stage responds to the value of Qm and changes states accordingly 0 Since Qm does not change when clock0 the slave stage undergoes at most one change of state during a clock cycle 0 From an output point of view the circuit changes QS its output at the negative edge of the clock signal Elainel a Cunning Enunmng m n J helmquot Lemsz 2 z lmnul a calming Enunml39 nrnJJclsm Len25 Masterslave D flipflop Edgetriggered flipflop Clock l l l I l l Qml ll clock 4C 6 The previous circuit responds on the positive edge of the clock signal 0 A negative edge triggered D flip flop can be constructed by replacing the NAND with NOR gates 7D Q7 7D Q7 clock Q clock 0 Q Positiveedgetriggered D type flipflop Negativeedgetn39ggered D type flipflop Elainel a cumnu Enunmng m n J Jclam Lectusz 5 Elainel a comma Enunmlm m n J mm Lain 25 1 Edgetriggered flipflop Comparing D storage elements o A circuit similar in functionality to the masterslave D flipflop can be constructed with 6 NAND gates D Q clock Q Positiveedgetriggered D type flipflop 24 transistors clock ool l T Elainel a cumnu Enunmng m n J Jclam Lectusz s Elainel a comma Enunmlm m n J mm Lain 25 n Clear and preset inputs T flipflop It may be desirable to specifically set Q1 or clear Q0 a flip flop Practical flip flops often have preset and clear inputs Generally these inputs are asynchronous they do not depend on the clock signal The name T derives from the behavior of the circuit which toggles its state when T1 This feature makes the T flipflop a useful element when constructing counter circuits T Qt1 Clock 0 Qt T Preset 9 1 Q t Q D Q As long as Preset390 Q1 T Q CIDCk 7 Q7 As long as Clear390 Q0 J Clear CIDCk Q Positive edge triggered nemmmmmmng nrnJJclam Lean25 a ElmnclampCnnvmuEnunealm nrnJJclsm Lame 2511 T flipflop JK flipflop 0 Another flipflop type the TfIipflap can be derived from the basic D flipflop presented 0 Feedback connections make the input signal D equal to the value of Q or Q39 under control of a signal labeled T T 7gt 6 Q Clock The JK flip op can also be derived from the basic D flip flop such that DJQ39K39Q The JK flip flop combines aspects of the SR and the T flip flop It behaves as the SR flipflop where JS and KR for all values except JK1 For JK1 it toggles like the T flipflop Elainel a cannula Enunmng m n J imam Lamisz 1n Elainel a calming Enunmlm m n J Jclsm Lain 25 12 JK flipflop D Q 5 6 J 0 0 Qt J Q 0 1 0 clock 1 0 1 K 6 1 1 Q t Positive edge triggered Elmncnlxcmminunmng nrnJJclmn Lemsz n JK flipflop timing diagram Complete the following timing diagram 1 cIk0 L K I I I I I L J I I II 1 Q0 1 Q0 4gtTime Elainel a Cunning Enunmng m n J helmquot Lemsz 1o

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