Class Note for ECE 380 at UA-Digital Logic(19)
Class Note for ECE 380 at UA-Digital Logic(19)
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This 5 page Class Notes was uploaded by an elite notetaker on Friday February 6, 2015. The Class Notes belongs to a course at University of Alabama - Tuscaloosa taught by a professor in Fall. Since its upload, it has received 33 views.
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Date Created: 02/06/15
Design using schematic capture ECE380 Digital Logic Number Representation and Arithmetic Circuits Design of Arithmetic Circuits Using CAD Tools 0 One way to design an arithmetic circuit is via schematic capture drawing all necessary logic gates 0 To create an nbit adder Start with a single full adder Chain together n instances of this to produce the nbit adder If a CLA adder is desired add carry lookahead logic 0 Design process becomes complex rapidly o A better approach to to use predefined subcircuits CAD tools provide a library of basic logic gates Most CAD tools also provide a library of commonly used circuits such as adders Each subcircuit is provided as a module that can be imported into a schematic and used as a part of a larger circuit Elwmul a cannula Ensquotagar m n r Jclam Latin 19 1 Elmncl a calming mungn1 m n r mm ran 19 2 Macro and megafunctions LPMADDSUB o In some CAD systems such as Altera s MAXPLUSZ these library functions are called macrofunctions or megafunctions 0 Two primary types of macrofunctions Technologydependent designed to suit a specific type of chip such as a particular FPGA Technologyindependent implemented in any type of chip with different circuils for different typs of chips 0 A good example of a library of macrofunctions is the Library of Parameterized Modules LPM as a part of the MAXPLUSZ system Each module is technology independent Each module is parameterized it can be used in a variety of ways 0 The LPM library includes an n bit adder named LPMADDSUB Implements a basic addsubtract circuit The number of bits n is set by a parameter LPMWIDTH Another parameter LPMREPRESENTATION determines whether the numbers are treated as unsigned or signed Elwmul a cannula Ensquotagar m n r Jclam Latin 19 a Elmncl a calming mungn1 m n r mm ran 19 a An adder using LPMADDSUB Adder simulation Rel l488ns lEEl Tlme llsl5ns l lnlerval l2l5ns LPM AEl VIE Damnquot add sub New yam i 48 HS 888quot 1288quot addsub cm arm D CIquot grew sub 1 P clataul r s 339 0 fXHS 8 HAAAA 5555 AAAA 5555 WLi SIIS 03 9415 8 HDDDD 2222 DDDD 2222 VHSUOI eyemow V o mow ism 8 H7777 7777 r r r 8887 W 3333 om Co 4 Cum 8 Ovar uw El gamma Deumpumsngmenng Dr D J Jscksun Lemmas slams Deumpumsngmeenng Dr D J Jscksun Lemmas DeSIgn USIng VHDL VHDL ful adder 0 We can use a hierarchical approach in designing VHDL code LIBRARV ieee 7 First construct a VHDL entity for a full adder USE ieeestd7logic71164all 7 Use multiple instances to create a multisbit adder ENTI f n dd IS TV u a 0 gr l ltDL a logic signal ls represented as a data pORT Ciquot X V IN STDiLOGIC J s Cout OUT STDiLOGIC s We used a BIT data type before that could only take on the values 0 and 1 7 Another data type STDiLOGIC is actually preferable because it can assume several di ferent values 0 1 2 high impedance 7 don39t care 0 We must declare the library where the data type exists and declare that we will use the data type LIBRARV ieee USE ieeestd7logic71164al Electrical 5 cDmDmerzngmeennD Dr D J Jackson Lecture 15 7 END fulladd ARCHITECTURE LogicFunc OF fulladd IS BEGIN s lt x XORyXOR Cin Cout lt x AND y OR Cin AND x OR Cin AND y END LogicFunc Electrical 5 cDmDmer Engineering Dr D J Jackson Lecture 15 s VHDL 4bit ripple carry adder VHDL 4bit ripple carry adder ENTITY construct LIBRARY ieee USE ieee5tdlogic1164all ENTITY adder4 IS PORT Cin IN STDLOGIC x3 x2 x1 x0 IN STDLOGIC y3 y2 yl yD IN STDLOGIC 53 52 51 50 OUT STDLOGIC Cout OUT STDLOGIC END adder4 ARCHITECTURE construct ARCHITECTURE Structure OF adder4 IS SIGNAL 1 c2 c3 STDLOGIC COMPONENT fulladd PORT Cin x y IN STDLOGIC s Cout OUT STDLOGIC END COMPONENT BEGIN stageu fulladd PORT MAP Cin x0 yo 5 c1 5tage1fulladd PORT MAP 1 x1 yl 51 c2 stageZ fulladd PORT MAP 2 x2 y2 52 c3 5tage3 fulladd PORT MAP Cin gt 3 Cout gt Cout x gt x3y gt y3 5 gt 53 END Structure Dn nlnllclmn Leduew E lmtncl a cunning Ensquotequip Elmncll a Carmina Ensquotawn in n J Jclsm Lain is in New VHDL syntax New VHDL syntax There are several new constructs in the previous VHDL code SIGNAL 1 c2 c3 STDLOGIC 7 Appears in the ARCHITECTURE construct a BasicaHv de nes signais that Wiii be used internai to the design i e not specifcaHv an IN or an OUT signai as appears in the PORT statement 0 COMPONENT fulladd 7 Appears in the ARCHITECTURE construct a De nes the pom tor a sdpcircdit component that is de ned in another ie rdiiadd vhd in this examp e a The VHDL ie tdiiadd vhd shodid normaHv be in the sarne directorv as the ie adder4 vhd o stageu fulladd PORT MAP Cin x0 yo 5 c1 a De nes an instance or the cornponent quadd narned stageo 7 Uses positional association because the inputs and outputs iisted in the PORT MAD appear in the exact sarne order as in the COMPONENT staternent 5tage3 ulladd PORT MAP Cin gt c3 Cout gt Cout x gt x3y gt y3 5 gt 53 a De nes an instance or the cornponent quadd narned stage3 7 Uses named association because each input and output iisted in the PORT MAD is associated With a specitc narned signai in the COMPONENT statement imam a cunning Ensquotequip in n J Jclam Levine is 11 Elmncll a Carmina Ensquotawn in n J Jclsm Lain is 12 VHDL packages VHDL packages A VHDL package can be created for a component subcircuit such that the COMPONENT statement is not explicitly required when creating instances of the component in another file LIBRARY ieee USE ieeestdlogic1164all PACKAGE fulladdpackage IS COMPONENT fulladd PORT cinxy IN STDLOGIC s Cout OUT STDLOGIC END COMPONENT END fulladdpackage Usually compiled as a separate file in the same directory as fulladdvhd nrnJchlam Leduew E lwtnul a Cunning Enunmll Elainel a Carmina Enunmlm m n J Jclsm Lain is 10 VHDL packages Numbers in VHDL LIBRARY ieee USE ieeestdogic1164all USE workfuladdpackageall ENTITY adder4 IS PORT Cin IN STDiLOGIC x3 x2 x1 x0 IN STDiLOGIC v3 V2 V1 yo 1N STDiLOGIC s3 s2 s1 so OUT STDiLOGIC Cout OUT STDiLOGIC END adder4 ARCHITECTURE Structure 0F adder4 IS SIGNAL c1 c2 c3 STDiLOGIC BEGIN stageo fulladd PORT MAP Cin x0 v0 so c1 stage1fulladd PORT MAP c1 x1 y1 s1 c2 stagez fulladd PORT MAP c2 x2 V2 s2 c3 stages fulladd PORT MAP Cingt c3 Cout gt cout x gt x3 v gt v3 s gt 53 END Structure Elainel a Cunning Ensuesis m n J helmquot Levine is 15 o A number in VHDL is a multibit SIGNAL data object SIGNAL C STDLOGICVECTOR1 TO 3 o C is a 3bit STDiLOGIC signal C a 3bit quantity c lt 100quot C 1 a 1bit quantity the mOst significant bit CZ a 1bit quantity C3 a 1bit quantity the least significant bit 0 The ordering of the bits can be reversed SIGNAL X STDLOGICVECTOR3 DOWNTO D o X is a 4bit STDiLOGIC signal X3 is the mOst significant bit X0 is the least significant bit Elainel a Carmina Enunmlm m n J Jclsm Lain is is Numbers in VHDL Behavioral VHDL descriptions LIBRARv ieee USE ieeestdogic1154aii USE workfuiiaddpackageaii ENTITv adder4 IS PORT Cin IN STDiLOGIC x v IN STDLOGICVECTOR3 OOWNTO o S OUT STDLOGICVECTOR3 OOWNTO o Cout OUT STDiLOGIC END adder4 ARCHITECTURE Structure OE adder4 IS SIGNAL C STDLOGICVECTOR1 TO 3 BEGIN stageo fulladd PORT MAP Cin gtlto vo So C1 stage1fulladd PORT MAPC1 gtlt1 v1 S1 C2 stage2 fulladd PORT MAP C2 gtlt2 v2 S2 C3 stage3 fulladd PORT MAP C3 gtlt3 v3 S3 Cout END Structure Allows use of STDLOGIC LIBRARV ieee signals as signed values USE ieeestdiogic1154aii USE ieeestdogicsignedai l ENTITv adder15 IS PORT x v IN STDLOGICVECTOR15 OOWNTO o S OUT STDLOGICVECTOR15 OOWNTO 0 END adder15 ARCHITECTURE Behavior OE adder15 IS BEGIN S lt x v END Behavior We are really descr39b39ng the behavior of the circuit Elwtnul a cannula tugquotequiv Dr B J helmquot Leme is 11 Elmnul a calming managing Dr B J mm Lain is in The VHDL arithmetic package LIBRARv ieee USE ieeestdogic1154aii USE ieeestdogicarithaii ENTITv adder15 IS PORT Cin IN STDiLOGIC x v N SIGNED15 OOWNTO o S UT SIGNED15 OOWNTO o Cout Overflow OUT STDiLOGIC END adder15 ARCHITECTURE Behavior OE adder15 IS SIGNAL Sum SIGNED16 OOWNTO 0 BEGIN Sum lt 39039ampgtlt v Cin S lt Sum15 OOWNTO o Cout lt Sum16 Over ow lt Sum16 gtltOR gtlt15 gtltOR v15 gtltOR Sum15 END Behavior Elwtnul a cannula tugquotequiv Dr B J helmquot Leme is is
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