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# Class Note for ECE 380 at UA-Digital Logic(23)

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This 3 page Class Notes was uploaded by an elite notetaker on Friday February 6, 2015. The Class Notes belongs to a course at University of Alabama - Tuscaloosa taught by a professor in Fall. Since its upload, it has received 27 views.

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Date Created: 02/06/15
ECE380 Digital Logic Synchronous Sequential Circuits Implementations using Dtype Ttype and JKtype FlipFlops zlaonca sconomanznolnoonno Dr in J Jackson LedureZSl Counter design example 0 Design a 2bit counter that counts 7 in the sequence 0123 0 if a given control signal u1 or s in the sequence 03210 if a given control signal u0 o This represents a 2bit binaw updown counter 7 An input u to control to count direction 7 A RESET input to reset the counter to the value Zero 7 Two outputs ZJZD representing the output 03 7 Counter counts on positive edge trans tons of a common clock signal 0 Design this counter as a synchronous sequential machine using 7 Dstype Tstype JKstype flipsflops acclnca sconomaznonoonno Dr in J Jaclson LedureZSZ Counter state diagram zlaonca sconomanznolnoonno Dr in J Jackson LedureZSCl Counter state table Present Next state Output state U 0 U s 1 zzu A D B 00 B A c 01 c B D 10 D c A 11 acclnca sconomaznonoonno Dr in J Jaclson LedureZEA Stateassigned state table 0 Choosing a state assignment of A00 B01 C10 and D11 makes sense here because the outputs 212O become the outputs from the flipflops directly Present Next state slam u0 u1 output y y ZJZEI 2 1 YZY YZY A 00 11 01 00 B 01 00 10 01 c 10 01 11 10 D 11 10 00 11 zlaonca sconomanznolnoonno Dr in J Jackson LedureZS Dtype flipflop implementation c When D flipflops are used to implement an FSM the nextstate entries in the state assigned state table correspond directly to the signals that must be applied to the D inputs 0 Thus Kmaps for the D inputs can be derived directly from the stateassigned state table 0 This will not be the case for the other types of flipflops T JK acclnca sconomaznonoonno Dr in J Jaclson LedureZSS State table and nextstate maps Y2Y1 u oo 01 11 1o 039 1 o o 1 39 Present Next state OUtpUt j r sJaJe U0 U1 2120 1 o o 21 YY YY I 2 1 2 1 Y1y1 A 00 11 01 oo Y2Y1 B 01 oo 1o 01 u oo 01 11 10 c 1o 01 11 1o 0 o o D 11 10 oo 11 1 o o Z1Y2 ZoY1 Y2Y2Y1Ul Circuit diagram D flipflop VCC Electrical amp Computer Engineering Dr D J Jackson Lecture 28 7 Design using other flipflop types o For the T or JK type flip flops we must derive the desired inputs to the flip flops 0 Begin by constructing a transition table for the flip flop type you wish to use This table simply lists required inputs for a given change of state 0 The transition table is used with the state assigned state table to construct an excitation table The excitation table lists the required flipflop inputs that must be excited to cause a transition to the next state Electrical amp Computer Engineering Dr D J Jackson Lecture 28 9 20 21 u clock reset Transition tables JKQQ QQJK TQQ QQT 0000 0000 000 000 0011 0110 011 011 0100 1001 101 101 0110 1100 110 110 100 1 JKtransition Ttransition 101 1 table table 110 1 111 0 The transition table lists required flipflop inputs to affect a specific change Electrical amp ComputerEngineering Dr D J Jackson Lecture 2810 Ttype flipflop implementation Use entries from the transition table to derive the flipflop inputs based on the stateassigned state table excitation table Present Flipflop inputs state U0 U1 1 YzY TzT YzY U 00 11 11 01 01 00 01 00 01 10 11 01 10 01 11 11 01 10 11 10 01 00 11 11 Output 2120 QQ oo 01 1o 11 OHHOl Electrical amp Computer Engineering Dr D J Jackson Lecture 2811 Excitation table and Kmaps yZy 1 00 01 11 10 U Fl39 fl 39 t 0 Ip op Inpus Present state U0 U1 03 1 10 m U U 00 11 01 oo yzyl 01 01 11 01 u oo 01 11 10 1o 11 01 1o 03 o o E 11 01 11 11 1 0 0 Z1Y2 ZoY1 T2Y1UY1IUIY1UI Electrical amp ComputerEngineering Dr D J Jackson Lecture 2812 Circuit diagram T flipflop Vcc Vcc Z0 21 clock reset Electrical amp Computer Engineering Dr D J Jackson Lecture 28 13 JKtype flipflop implementation Q 0 Present FIIp flop Inputs OUt Ut state Uo U1 21 0 VI an LKZJJQ Ygg hKZJlm 1 OO 11 1D 1D 01 OD 1D 00 1 01 00 OD D1 10 1D D1 01 JK transition 10 01 D1 1D 11 DO 1D 10 table 11 10 D0 D1 00 D1 D1 11 JKtype flipflop implementation 0 Use entries from the transition table to derive the flip flop inputs based on the state assigned state table This must be done for each input J and K on each flipflop Next state Pgiasfgt UO U1 oats 0 0 0 D YZYI YZY1 YZY1 0 1 1 D 00 11 01 00 1 0 D 1 01 00 1o 01 1 1 D 0 10 01 11 10 JK transition 11 10 00 11 table Electrical amp Computer Engineering Dr D J Jackson Lecture 28 14 Electrical amp Computer Engineering Dr D J Jackson Lecture 28 15 Excitation table and Kmaps Flipflop inputs Present Output state U 0 U 1 leo M Y2Y1 1sz 11K Y2Y1 1sz 11K 00 11 1D 1D 01 OD 1D 00 01 00 OD D1 10 1D D1 Ol 10 01 D1 1D 11 DO 1D 10 11 10 D0 D1 00 D1 D1 11 Y2yl Y2Y1 u oo 01 11 10 u oo 01 11 1o 0 1 D D 1 0 D 1 1 D 1 L1 D D 1 1 LD 1 1 D J11 K11 Dr D J Jackson Lecture 28 16 Electrical amp Computer Engineering Excitation table and Kmaps Flipflop inputs Present Output state U 0 U 1 leo VZVI YZYI JZKZ JlKl YZYI JZKZ JlKl oo 11 1D 1D 01 OD 1D oo 01 00 OD D1 10 1D D1 01 1o 01 D1 1D 11 DO 1D 10 11 10 D0 D1 00 D1 D1 11 Y2Y1 Y2Y1 u oo 01 11 10 u oo 01 11 1o 0 D D 03 D o E D 1 D EE 0 J2 Y1C Bu K2Y1 Ul Electrical amp Computer Engineering Dr D J Jackson Lecture 28 17 Circuit diagram JK flipflop Vcc Vcc ZO clock reset Electrical amp Computer Engineering Dr D J Jackson Lecture 28 18

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