Class Note for ECE 380 at UA-Digital Logic(25)
Class Note for ECE 380 at UA-Digital Logic(25)
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This 3 page Class Notes was uploaded by an elite notetaker on Friday February 6, 2015. The Class Notes belongs to a course at University of Alabama - Tuscaloosa taught by a professor in Fall. Since its upload, it has received 15 views.
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Date Created: 02/06/15
ECE380 Digital Logic FlipFlops Registers and Counters FlipFlops Eemnca AcomvmerEngmeymg Dr D J Jackson La urez l Masterslave D flipflop 0 When clock 1 the master tracks the values of the D input signal and the slave does not change 7 Thus Qm follows any changes in D and Q5 remains constant 0 When the clock signal changes to 0 the master stage stops following the changes in the D input signal 0 At the same time the slave stage responds to the value of Qm and changes states accordingly 0 Since Qm does not change when clock0 the slave stage undergoes at most one change of state during a clock cycle 0 From an output point ofview the circuit changes QS its output at the negative edge of the clock signal Eemnca sconomaznonoonno Dr D J Jaclson comma Flipflops o The gated latch circuits presented are level sensitive and can change states more than once during the active period of the clock signal 0 Circuits storage elements that can change their state no more than once during a clock period are also useful 0 Two types of circuits with such behavior Masterslave flipflip Edgetriggered flipflop Eemnca AcomvmerEngmeymg Dr D J Jackson La urez z Masterslave D flipflop Clock I I I Qm l l l clock 4c 67 Eemnca sconomaznonoonno Dr D J Jaclson comma Masterslave D flipflop o Consists of 2 gated D latches The first master changes its state while clock1 The second slave changes its state while cloc k0 Master slave Q m S D D Q D Q Q clock Clk Q Clk Q 6 38 transistors Eemnca AcomvmerEngmeymg Dr D J Jackson La urez l Edgetriggered flipflop o A circuit similar in functionality to the masterslave D flipflop can be constructed with 6 NAND gates 70 Q7 clock Q Positivesedgestnggered D type flipaflop Z4 transistors Dr D J Jaclson caucus Eemnca c conoma Enonoonng Edgetriggered flipflop o The previous circuit responds on the positive edge of the clock signal 0 A negativeedge triggered D flipflop can be constructed by replacing the NAND with NOR gates D Q D Q clock 7 Q 7 clock 70 Q 7 Pos tivesedgestriggered D type fliprflop Negativesedgestriggered D type fliprflop Eemrica AcomvmerEngineying Dr D J Jackson LedureZ T T flipflop 0 Another flipflop type the Tflipflap can be derived from the basic D flipflop presented 0 Feedback connections make the input signal D equal to the value of Q or Q39 under control of a signal labeled T l7gt Ed Q Clock Eemrica sconomaznonoonno Dr D J Jackson LedureZ l Comparing D storage elements clock Clk 4c 67 Eemrica AcomvmerEngineying Dr D J Jackson La ureZ S Clear and preset inputs o It may be desirable to specifically set Q1 or clear Q0 a flipflop 0 Practical flipflops often have preset and clear inputs Generally these inputs are asynchronous they do not depend on the clock signal Preset D Q As long as Preset390 Q1 CIOCk 7 37 As long as Clear390 Q0 cleor397 f Eemrica AcomvmerEngineying Dr D J Jackson LectureZ S T flipflop o The name T derives from the behavior of the circuit which toggles its state when T1 This feature makes the T flipflop a useful element when constructing counter circuits T Qt 1 Clock 0 Qt T 1 Q39t Q T Q clock7 6 Pos tive edge triggered Eemrica sconomaznonoonno Dr D J Jackson La ureZSM JK flipflop o The JK flipflop can also be derived from the basic D flipflop such that DJQ39K39Q o The JK flipflop combines aspects of the SR and the T flipflop It behaves as the SR flipflop where JS and KR for all values except JK1 For JK 1 it toggles like the T flipflop Eemrica sconomaznonoonno Dr D J Jackson LedureZ l JK flipflop OI J Q 7 K 6 Pos tive edge triggered OI seem a Computer Engineering Dr D J Jackson La urez l JK flipflop timing diagram Complete the following timing diagram Clk L ll l OHOHOHOHOH seem a Computer Engineering L gtTime Dr D J Jackson La urez l
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