Class Note for ECE 380 at UA-Digital Logic(26)
Class Note for ECE 380 at UA-Digital Logic(26)
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This 2 page Class Notes was uploaded by an elite notetaker on Friday February 6, 2015. The Class Notes belongs to a course at University of Alabama - Tuscaloosa taught by a professor in Fall. Since its upload, it has received 23 views.
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Date Created: 02/06/15
ECE380 Digital Logic Design of Finite State Machines Using CAD Tools stance AEuNDmerEngmearlng Dr D J Jackson La urelll FSM design using CAD tools o VHDL provides a number of constructs for designing finite state machines 0 There is not a standard way for defining an FSM 0 Basic approach 7 Create a userrdefined data type m represent the possible slams of an FSM a This signal represents the outputs state variables of the fliprflops that implement the states in the FSM a VHDL compiler chooses the appropriate number of fliprflops during me synthesis process 7 The state assignment can be done by the compiler or can be user specified stance AEomDmaEngmearlng Dr D J Jaclsun Lacturellz User defined data types o The TYPE keyword will be used to define a new data type used to represent states in the FSM TYPE Statetype IS A B C Data type A userdefined name data type definition the data type Valid values for Defines a data type called Statetype that can take on three distinct Values A B or C stance A Computer Engineering Dr D J Jackson LaciureCMCl Representing states o A SIGNAL is defined of the userdefined Statetype to represent the flipflop outputs TYPE Statetype IS A B C SIGNAL y Statetype The signal y can be used to represent the flipflop outputs for an FSM that has three states stance AEomDmaEngmearlng Dr D J Jaclsun LaciureCMA Design example o Create a VHDL description for a circuit that detects a 391139 input sequence on an input w reset Recall the Moore state diagram for the circuit stance AEuNDmerEngmearlng Dr D J Jackson Lacturell VHDL design example LIBRARY ieee USE ieeestdlog c71164all ENTlTY detect IS PORT clk resetn w IN STDiLOGIC z OUT STDiLOGIC END detect ARCHlTECTURE Behavior 0F detect IS TYPE Shamitype IS ABC SIGNAL y Shamitype BEGIN stance AEomDmaEngmearlng Dr D J Jaclsun La urells VHDL design example cont nued PROCESS resetl39l clk ELSE BEGIN V lt C lFreSetrl 039 THEN END 1 V lt Al WHEN C ELSlE clk EVENT AND clk 1 THEN F W CASE v lS WHEN A gt V lt lEW 039 THEN ELSE v lt A v lt C ELSE END lE END CASE END lE END PROCESS z lt 139 WHEN vC ELSE 039 END Behav or aeme AEDNDmerEnglneylng Dr D J Jackson La ureCMT Alternative style of VHDL code 0 Another form for describing the circuit in VHDL is to define two signals to represent the state of the FSM a One signal ypresent defines the present state of the FSM a The second ynext defines the next state of the machine 0 This notation follows the y present state and Y next state notation used previously 0 Two PROCESS statements will be used to describe the machine a The first describes the STATE TABLE as a combinational circuit a The second describes the fliprflops stating that ypresent should take on the value of ynext after each pos tive clock edge aeme scampmeznamenna Dr D J Jeclson La urell Alternate VHDL description ARcHrrEcruRE Behavior OF detect Is WHEN c gt quotPE Stateitype Is ABc IFw n39 THEN SIGNAL yipresent yinext Stateitype yinext lt A BEGIN EisE PRocEsswypresem Liven lt c BEGIN END cAsE cAsE yipresent Is END PROCESS PRocEssclkreseAn BEG IN IF resetquot yipres m lt A ELSIF 39EVENI AND cl yipresent lt yinext END IF END PROCESS x lt l39 WHEN yipresemc ELSE 039 END Behavior 139IHEN aeme AEDNDmerEnglneylng Dr D J Jackson La ureCMS Specifying a state assignment 0 With the previous designs state assignment is done by the VHDL compiler 0 State assignments can be user specified using the following constructs ARGHIIEcruRE Behavior or simple Is 139va Stateitype Is A B c AIIRIBuIE ENUMiENmDING STRING AIIRIBuIE ENUMiENmDING or Stateitype 139va Is quoton DI IIquot sIGNAi yipresent yinext Stateitype BEGIN Dr ARCHIIEcruRE Behavior OF simple Is ext er LOGIC vEcroRu DOWNI aeme scampmeznamenna Dr D J Jeclson La urelll VHDL code of a Mealy FSM o A Mealy FSM can be described in a similar manner as a Moore FSM o The state transitions are described in the same way as the original VHDL example 0 The major difference in the case ofa Mealy FSM is the way in which the code for the output is written 0 Recall the Mealy state diagram for the 391139 sequence d etector reset 10 Wquot 0 0 0031 00 aeme a Computer Enamennv Dr D J Jackson Lecture 11 Mealy 391139 detector VHDL code ARCHITECTURE Behav or oE detect lS WHEN B I gt TYPE Stateitype lS AB F W 0 THEN vlt A SlGNAL v Stateitype 3155 B BEGIN END CASE PROCESSreSetnclk END IF BEG N END PROCESS lE reset 039 THEN pROCESSW W A BEGIN ELSElFclk EENT AND clk 1 THEN CASE v lS CASE v lS WHEN A gt lE W o39 THEN vlt A ELSE vlt B ZltW END IF END CASE END PROCESS END Behavlor aeme scampmeznamenna Dr D J Jeclson La urelll
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