Class Note for ECE 380 at UA-Digital Logic(6)
Class Note for ECE 380 at UA-Digital Logic(6)
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This 4 page Class Notes was uploaded by an elite notetaker on Friday February 6, 2015. The Class Notes belongs to a course at University of Alabama - Tuscaloosa taught by a professor in Fall. Since its upload, it has received 12 views.
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Date Created: 02/06/15
Introduction to CAD tools ECE380 Digital Logic Introduction to Logic Circuits CAD Tools and VHDL o A CAD system usually includes the following tools a Design entry 7 Synthesis and optimization 7 Simulation 7 Physical design new acmaltrtramtnra a n J hckmn rem Elewlczl a maul Ergmelvg Dr D J lsasm um 52 Design entry Design entry with truth tables o The process of entering into the CAD system a description of a circuit being designed is called design entry 0 Three common design entry methods 7 Using truth tables User enters a truth table ln plaln textformator draws a waverorm that represents the deslred functlonal behavlor 7 Schematic capture User graphlcally enters a deslred loglc clrcult 7 Hardware description languages User enters a programmlng languagerllke descrlptlon ora deslred loglc clrcult Commonly use a waveform editor m enter a timing diagram that describes a desired functionality for a logic circuit 7 CAD system transforms thls ll lto equwalent loglc gates 7 Not appropnate for large Cll culB but can be used for a small loglc functlon that l to be part of a larger Cll cult Name T a lnn uns 2mm uns auu uns m lNPUT x2 lNPUT l COME new acmaltrtramtnra a n J hckmn lemme Elewlczl a maul Ergmelvg Dr D J lsasm mm M Schematic capture Schematic capture 0 Most common type of CAD tool 0 Schematic refers to a diagram of a circuit in which circuit elements logic gates are shown as graphical symbols and connections between them are drawn as lines 0 Tool provides a collection of symbols that represent gates of various types with different inputs and outputs Alibrary Previously designed circuits can be represented with a graphical symbol and used in larger circuits Known as hierarchical design and provides a way of dealing with complexities of large circuits Name T mo ons zoo Elns anti Ins m INPUT x2 INPUT 1 COMB Eleariml s Eomvma Engineamg Dr D J Jackmn Leaures same a Eomvma Eigineaing Dr D J Jaclson Lawless Hardware description languages Synthesis o A hardware description language HDL is similar to a computer program except that it is used to describe hardware 0 Common HDLs VHDL OIHSIC Hardware Description Language Verilog Many others vendor specific 0 VHDL and Verilog are standards Offer portability across different CAD tools and different types of programmable chips 0 Synthesis CAD tools perform the process of generating a logic circuit from some stated functional behavior 0 Translating compiling VHDL code into a network of logic gates is a part of synthesis 0 Not only will the CAD tool produce a logic circuit but it can also optimize that circuit 7 In terms of speed andor SlZe logic Optimizatio e Called logic synthesis or logic optimization 0 Finally technology mapping and layout synthesis physical design complete the synthesis process Eleariml s Eomvma Engineamg Dr D J Jackmn Leaures7 same a Eomvma Eigineaing Dr D J Jaclson Leaues Simulation Introduction to VHDL 0 Once designed it is necessary to verify that the design circuit functions as expected 0 In a functional simulation the user specifies valuations of the circuits inputs and the CAD tool generates the outputs commonly in the form of a timing diagram User verifies generated outpuls against expected outpuls 0 Functional simulators assume the time needed for signals to propagate through the logic gates is negligible Fora FEI implementation this is not sufficient Use a timing simulator to obtain accurate complete simulation 0 Designer writes a logic circuit description in VHDL source code VHDL compiler translates this code into a logic circuit 0 Representation of digital signals in VHDL Logic signals in VHDL are represented as a data object VHDL includes a data type called BIT BIT objects can assume only two values 0 and 1 mama a Emma Ensquotagar m n i imam Levine s a mama a comma Ensquotaqua m n i imam ram a 1n Writing simple VHDL code Writing simple VHDL code First step in writing VHDL code is to declare the input and output signals 0 Done using a construct called an entity Name of the entity Input and output signals ports defined ENTITY examplel IS PORT x1x2x34 IN BIT f OUT BIT END examplel Mode of the port Type of the port IN input OUT output mama a Emma Ensquotagar m n i imam Levine s 11 Name of the entity Input and output signals poms defined ENTITY examplel IS PORT x1x2x3 7 IN BIT f OUT BIT END examplel Mode of the port Type of the port IN input OUT output x1 x2 x3 mama a comma Ensquotaqua m n i imam ram is 12 Writing simple VHDL code Complete VHDL code example o The entity specifies the inputs and outputs for a circuit but does not describe the circuit function 0 Circuit functionality is specified using a VHDL construct called an architecture Archrtecmre name Entrty used by togrcFunc ARCHITECTURE LngcEunc DE examp el IS BEGIN flt LXI AND K21 OP NUT K2 ANL XS END togrcFunc VHDL statement that desc bes the crrcurt iuncuonahty X1 X2 ENTlTV examp el lS PORTgtlt1gtlt2gtlt3 lN BIT x3 r OUTBIT END examp el ARCHITECFURE togrcFunc or examp el 5 BEGIN rlt x1 AND x2 OR NOT gtlt2 AND x3 END togrcFunc EwummLonmvuorEHmnmni V Di 4mm mums o ammmpwmm V Di mm man u Boolean operators in VHDL Example VHDL code VHDL has buhtrm support for the foHovymg operators 7 AND ogrca AND 7 OR ogrca OR 7 NOT ogrca NOT NAND NOR XOR XNOR covered ater Assrgnment operator lt7 7 Ayanaore usuaHy an output shouro be assrgneo the resurt orthe ogrc expressron on the nght hand sroe orthe operator VHDL does not assume any precedence of ogrc operators Use parentheses m expressrons to determme precedence In yHDt a ogrc expressron rs caHed a simple assignment statement There are other types that M be rntroduced that are usefu for more comp ex crrcurts nun wwwmmwnn V Di 4mm mums u 0 Write the VHDL code entity and architecture constructs for the adder circuit Name the entity Add and name the architecture AddFunc 0 Write the VHDL code for the majority circuit Name the entity Majority and name the architecture Majoritych ammmpwmm V Di mm man ts
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