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# Class Note for ECE 380 at UA-Digital Logic(8)

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This 5 page Class Notes was uploaded by an elite notetaker on Friday February 6, 2015. The Class Notes belongs to a course at University of Alabama - Tuscaloosa taught by a professor in Fall. Since its upload, it has received 17 views.

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Date Created: 02/06/15
Storage elements ECE380 Digital Logic Flip Flops Registers and Counters Latches Previously we have considered combinational circuits where the output values depend only on the values of signals applied to the inputs 0 Another class of logic circuits have the property that the outputs depend not only on the current inputs but also on the past behavior of the circuit 0 Such circuits include storage elements that store the values of logic signals mama a Emma mamau m n i imam Lemmy 1 mama a comma Ensquotaqua m n i imam Lam m Sequential circuits Alarm control system Contents of the storage elements represent the state of the circuit 0 Input value changes may leave the circuit in the same state or cause it to change to a new state 0 Over time the circuit changes through a sequence of states as a result of changes in the inputs Circuits that exhibit this behavior are referred to as sequential circuits 0 Suppose we wish to construct an alarm circuit such that the output remains active on even after the sensor output that triggered the alarm goes off A typical car alarm is representative of this type of circuit 0 The circuit requires a memory element to remember that the alarm has to be active until a reset signal arrives Set Reset Memory OnOff39 element Alarm mama a Emma mamau m n i imam Lemmy i mama a comma Ensquotaqua m n i imam Lam 2w A simple memory element Basic SR latch AEBE Simple memory element feedback path provides basis for the remembering39 of data Load Load 0 TGzon providing a feedback path DE Output FS lgto lgt Load 1 TG1on providing a way to load new data gto Elainel a Cunning Enunmng m n J 101am Lemmy 5 o A similar circuit constructed with NOR gates can also be constructed 0 Inputs Set and Reset provide the means to changing the state Q of the circuit 0 This circuit is referred to as a basic latch Reset R Set 5 Elainel a calming Enune lm m n J mm Lain m Basic SR latch Basic SR latch timing diagram 0 When RS0 the circuit remains in if current state either Qa1 and Qb0 or Qa0 and Qb1 0 When 51 and R0 the latch is set into a state Where Qa1 and Qb0 0 When 50 and R 1 the latch is reset into a state Where Qa0 and Qb1 0 Where 51 and R1 QaQb0 there are actually problems with this state as we will see R Q s R Q Q a 0 0 01 10 no change 0 1 0 1 1 0 1 0 5 On 1 1 o 0 t4 to Q3 Qb OHOHOHOH gtTme Elainel a Cunning Enunmng m n J 101am Lemmy 1 Elainel a calming Enune lm m n J mm Lain m Basic SR latch timing diagram Gated SR latch If the propagation delays from Qa and Qb are exactly the same the oscillation at time t10 would continue indefinitely In a real circuit there would probably be some mostly insignificant difference in the delays and the latch would eventually settle into one of its two stable states but we don t know which one it would be 0 Thus the SR1 combination is generally considered an unallowed combination in the SR latch The basic SR latch changes its state whenever its inputs change 0 It may be desirable to add an enable signal to the basic SR latch that allows us to control when the circuit can change states 0 Such a circuit is referred to as a gated SR latch mama a Emma Ensnan m n i imam Lemmy a mama a comma Ensquotaqua m n i imam Lam 2m Gated SR latch circuit Gated SR latch timing diagram R R CLK s o x Clk 1 0 1 0 Q 1 1 5 9 1 1 S Q Qtpresent state i Clk Qt1next state Clk o m OHOHOHOHOH O l 4gtTime mama a Emma Ensnan m n i imam Lemmy 11 mama a comma Ensquotaqua m n i imam Lam 2m Gated SR latch with NAND gates S Clk R Elmnul a cannula Enunmng m n J Jclam Lemmy n Gated D latch 0 Another useful latch has a single data input D and it stores the value of this input under the control of a clock signal 0 This is referred to as a gatedD latch Useful in circuils where we want to store some value The output of an addersubtractor circuit would be one example S Data Q Ok 6 Elmnul a calming Enune lm m n J Jclsm Lain um Gated D latch CLK D Qt1 7 D Q 7 1 0 0 clk Q 1 1 1 t1 t2 t3 t4 cIkll D l Il ll39LlL Q I gtTme Level versus edge sensitivity 0 Since the output of the D latch is controlled by the level 0 or 1 of the clock input the latch is said to be level sensitive All of the latches we have seen have been level sensitive It is possible to design a storage element for which the output only changes a the point in time when the clock changes from one value to another 0 Such circuits are said to be edge triggered Elmnul a cannula Enunmng m n J Jclam Lemmy 15 Elmnul a calming Enune lm m n J Jclsm Lain 2m Effects of propagation delays Setup and hold times 0 Previously we have ignored the effects of propagation delay In practical circuits it is essential to account for these delays 0 For the gated D latch and others as well it is important that the value of D not change at the time the clock clk goes from 1 to 0 The designer must make sure the signal is stable when the critical change in the clock takes place 0 The minimum time the D signal must remain stable prior to the negative edge 1gt0 of the clock signal is called the setup time tsu o The minimum time the D signal must remain stable after the negative edge of clock is the hold time t Typical CMOS values are t5u3ns and th2ns Clk D Q l Elainel a cannula Enunmng m n J Jclam Lemmy 11 Elainel a calming Enune lm m n J mm Lain 2m

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