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Date Created: 12/22/15
Vil Bahadur (408) 230-2443 Email: email@example.com http://www.linkedin.com/in/vilbahadur Objective: VPTestEngineering|| Operations Education: MBA 1988 Major Operations & Management REGIS University, Colorado BSEE 1979 San Francisco, CA BS 1975 Major Physics & Mathematics Professional Summary: Manager of Analog Test Engineering organizations. Managing staff of 25+ in 4 different product lines. 28+ years of experience. NPI releases…. Tracked all aspects and drove the schedule from Design to Market Introduction, coordinated with Design, layout, Masks, FAB, Test, REL & Qual. Program/Project Management. Ran the NPI meeting. Interfaced with 2 different Business Units who were our customers for Test Engineering Services we delivered. Program schedules, tracking and delivering to commitments……… for 10 years my group never slipped a schedule. Customer interaction and managed relationships, technically handled customer inquiries and application questions on data Acquisition products, helped them design interface circuitry and layout of PC Boards. Managed foundry customers who were our fab service customer. (Honeywell). MSA (measurement system analysis), Gage R&R………. and statistical 6 sigma practices in manufacturing. Set up departments and wrote and implemented procedures for groups here and offshore. Hands on leader who leads from the front, empowered my group with clear objectives, the touch sense line worked around the clock to deliver robust solution in 4 months, 3 to 4 times faster than normal… Even though we worked more, every activity was planned and coordinated (we were not stressed)….group inspired to deliver a robust test solution. (improved Time to Market, trimmed samples in one week) Trained and built up groups. Built the test eng and product eng group here in US and a 7 member team in Philippine. Re-engineered Test Solutions for robustness and Test Time. Redid 300 problem Test program release, changed hardware design, improved Test Program, characterized and transferred offshore. Test Cost was improved. US Test Engineering? 5 times more expensive than offshore engineers, US engineers should only do what offshore can’t. Tried for last 4 years to narrow the gap between Test and Design, TE were sent to Verilog school, hired verification engineers in test, development of test program in simulation. This is now a major initiative in Maxim. Innovation & out of the box thinking. From coming up with methods with curvature trimming to coming up with methods to write test programs in simulation environment i.e. defining Verilog BFM methodology where all test sequences are confirmed in simulation with device database prior to silicon. Delivering trimmed parts in 48 hours after receipt of silicon. Significantly improved Post Silicon NPI time/ Time to Market. (this activity was result of difficulty in accessing inner nodes in SOC devices ). The first 16 years of my career were in developing test packages on several Mixed Signal ATE platforms. LTX, Teradyne, HP9491, Analog Devices LT2020, Genrad, KVD and Eagle. Developed Test packages for Analog, Digital and Mixed Signal SOC’s. Still work alongside Test Engineers on ANALOG TEST PROGRAM. Heavily involved in difficult analog measurement issues, low noise layout of test hardware and in improving the test methodology. Recently released an 18 bit DAC program with LSB of 15.0 uvolts. Correlated to within 2 uvolts. Page 1 Experience: Maxim Integrated 1999 to Nov 2012 (13 years) San Jose, CA. Exec Director, Test/Product Engineering (MAXIM) 2009 to Present Four lines reported to me, the op-amp group, the reference line, DAC line and the touch/cap sense line. 1. Touch sense/cap line: Led multi-engineer teams to develop test programs with complex touch sense parts. Devices with multiple drivers, sense comparators, ADC, flash memory and processor. Multi site Test programs released in 4 months. This was 3 to 4 times faster than any part at Maxim of this complexity. BFM (Bus Functional Models), DVT, confirmation of test sequences with Verilog and top level behavioral model of entire chip in system Verilog helped us prepare for silicon. We generated trimmed samples in 3 days after silicon. Worked with assembly vendor Corwil. Test time of 1.6 secs. Capability to test 8 Million units/Quarter…. 2. The DAC group: High precision DAC group. 18bit DAC, 12, 14 and 16 bit DAC family. Incorporated universal hardware, universal modularized software to promote reuse, improved quality and control of program. In September released an 18 bit DAC with lsb of 2.5uvolts. 3. Op-amp group: Took over this group in Tucson Arizona in Nov 2011, Test Strategy, hardware and software, standardization. Multi site conversion to 32x on WLP parts, in cost reduction alone have saved the company $700,000. 4. The Reference line: Evaluated, reviewed the test strategy, consolidated test programs, redid hardware and transferred the entire line of 255 line items offshore. (no issues). 5. Offshore Test Engineering & Monitoring: Offshore engineers work with our group for cost reduction activity. We get quarterly targets from finance and we exceed our plan by 10 to 20%. Test time reduction, multi-site conversion, review of the test program and qualification of flows to eliminate Cold and HOT Testing. Monitored offshore Metrics, QA fails, test time, average yield, test engineering time (TEMM) i.e. time to support existing products, setup time and QA fails. Implemented systems to improve. Director, Test/Product Engineering (MAXIM) 2002 to 2009 Ran the Laser Wafer Sort line for 5 years, several improvements. Achieved zero miss-trim and burn. Innovation, on a 16 bit DAC ‘s laser cutting. Straight line laser cuts trims effect gets coarser and coarser as we approach the target. A cut on a curve would get us the desired straight line transfer function. Using finite element mathematics and sheet rho, calculated the shape of the curve. Trimming on a curve, increased the yield from 60 to 92%. This was a patentable idea……… Transferred Laser wafer sort operations offshore, trained offshore engineers, we have no issues with this transfer. Manager, Test/Product Engineering (MAXIM) 1999 to 2002 Led a group to transfer LTX final test products offshore, some 270 projects. These were difficult projects that could run only in US, needed constant engineering support. Systematically improved the Test Method/Hardware focused on 20 products at a time and transferred offshore. Took 18 months, but were all done…no issues. Linear Technology Corp. 1996 to 1999 (3 years) Milpitas, CA. Staff Test Engineer: Test Program Development on 16 bit, 14 bit and a 10 bit 40 MHz ADC. Worked on both FT and Sort. These parts were laser trimmed. Sustaining support of 8 high volume products. Page 2 Arithmos 1995 to 1996 Santa Clara, CA. Director Test Engineering & Operations. Startup, complex 300+ pin mixed signal smart LCD panel driver. Developed test program with custom hardware on Credence tester at ISE labs. Worked with vendors in Japan with Yokogawa tester on production testing. Planned for several million units ramp-up. The IC had a gradient issue across channels, which could not be solved in time. IP sold to ST microelectronics. Raytheon Co. 1992 to 1995 350 Ellis St., Mountain View, CA. Manager Test Engineering. Managed and Led a group who designed/developed test hardware and testprograms for 33 new products. Defined TEST Strategy/Test plan and helped in the design of the TEST HARDWARE. ContinuouslyworkedonstandardizingandimprovingtheTEST hardware andsoftware generationprocess. Instituted many short term projects to improve the a) Handler interfacing of High Speed products, b) Standardization of hardware for a single PC board layout for wafer, final test & bench. This resolved the Final Test, Wafer sort and Bench correlation issues. PersonallyDevelopedTestProgramsfor8bitVideoA/Dconverteranda5poleactivefilter.Bothdevicesemployed DSP techniques in the Test algorithms. StrategicallyplannedforthelongtermobjectivesoftheTESTEngineering.Evaluatedandmonitorednewtechnology/TESTERS and maderecommendationsforimprovementsto meetthepresentand longtermneeds. The mixed signal HP tester was upgraded. Standardized the characterization reportand presentation format, initiated a formal characterization policy and automated the 3 temperature characterization of new products. Fully characterized and released many new products. Harris Corporation. (Now Intersil) 1990 to 1992 2450 Walsh Ave. Santa Clara, CA 95051 Staff Product & Test Development Developedthecapabilitytododynamic testingofHighSpeed10and 12bitsA/D converters. SNR, Noise and Harmonic distortion. Led a Group to transfer the entire Final Test Production Test line from Santa Clara to Findlay Ohio. (300 products) Elantec Inc. (Now Intersil) Feb 1989 to Feb 1990 Milpitas, CA Manager Test Engineering As Elantec and its product line grew, it exerted pressure on Test Eng. The company had grown from a few to 70 different products. When I joined, new products were awaiting test programs and release to productionandproductionwashaving problemstestingexistingproductsthroughtheline.Therewereseriousconsiderations about adding an additional tester for about 1 million dollars. Imposed control by adding schedules, reports, tracking of all Hardware, Software, repairs and downtime to better manage and to identify the weak spots. StreamlinedtheTestSustainingeffort,institutedTestset-uprepairproceduresandTestoperators training program. Reduced the down-time for production set-ups. Increased the Test Capacity by 1.5X with existing machines. Saved the Co. $1 Million for the costof new machine. Redefined the ACTestStrategy with stand-alone Rack &Stacktesting, integrated Time and Freq Domain Testing. May 1985 to Feb 1989 (4 years) Honeywell Inc. (Signal Processing Technologies) Colorado Springs, CO 80906 Page 3 Manager Product Engineering 5/85 to 5/88 Worked onTestStrategy, InstrumentalinTester evaluationfor our productlines, worked withdifferentvendors, evaluation of our needs, criteria for selection of testers, worked with 3 major vendors. Established bench data lab, New product characterization and Introduction. Monitored yields & production. Foundry Management of our design center and Honeywell's factories in Colorado and Minnesota. Ran the NPI weekly meeting, tracked fromdesign to market introduction. Principal Applications Engineer 5/88 to 2/89 Developed dynamic bench testing of High Speed A/D convertors, Developed a FAE training program on data convertors. Seminars and teaching Field Application Engineers. 1979 to 1985 (6 years) Micro Power Systems, (now EXAR) Santa Clara, CA Supervisor Test Engineering. Application engineering on Flash ADC, Dynamic testing with bench system. Designed hardware and wrote Test programs for DAC’s, ADC and numerous analog SOC products. Designed a Standalone TESTER using proms as controller to TEST an ASIC part. Publication: AuthoredanarticleonHighSpeedA/DConverters,ComparativestudyofdifferenttypesofADCconvertors,publishedinthe Feb92issueof"NewElectronics" magazine. Page 4
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