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# 398 Note for ECE 27000 with Professor Meyer at Purdue

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Static and Dynamic Behavior of Digital Circuits Lecture Workbook Page 11 200607 Edition by D G Meyer Introduction to Digital System Design Module 1 Static and Dynamic Behavior of Digital Circuits Module 1 o Desired Outcome An ability to analyze static and dynamic behavior of digital circuits Part A Review of Basic Electronic Components Part B Logic Signals and Gates Part C Steady State Electrical Behavior of CMOS Circuits Part D Dynamic Behavior of CMOS Circuits Part E Other CMOS InputOutput Structures and Logic Families Little Bits ofDigital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook Page 12 200607 Edition by D G Meyer Introduction to Digital System Design Module lA Review of Basic Electronic Components Basic Electronic Concepts 0 VOLTAGE difference in electrical potential expressed in 0 CURRENT the flow of charge in a conductor between two points having a difference in potential expressed in amps o Waterfall analogy voltage is proportional to of waterfall current is proportional to of waterfall 0 POWER amount of energy expressed in typically calculated as the product of the drop across a device and the flowing through it Little Bits ofDigital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook Page 13 Basic Electronic Concepts o RESISTOR a device that limits the amount of current flowing through a circuit measured in Q o Resistance is also referred to as o The inverse of impedance is o Fundamental relationship the voltage drop VR across a resistor is equal to the product of the current flowing through it IR and the value of the a resistance R 2 called E VRIRxR Basic Electronic Concepts o CAPACITOR a device that stores an electric charge measured in F o Fundamental relationships a resistorcapacitor RC network charges and discharges exponentially the voltage across a capacitor cannot change instantaneously the product of R and C is called the Vc VIN X 1 39 e39tRC V39 LV Little Bits of Digital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook Page 14 Basic Electronic Concepts o DIODE a device that restricts the flow of current to a single direction from its to its I I o Fundamental relationships a diode through which current is flowing because the voltage at the anode is greater than at the cathode is if current is not flowing through a diode because the voltage at the cathode is greater than at the anode the diode is Basic Electronic Concepts o LIGHT EMITTING DIODE LED a diode that emits visible redyellowgreenlblue or invisible infrared light when forwarded biased i I D o Fundamental relationships gt the brightness of an LED is proportional to the amount of current flowing through it called the a is placed in series with an LED to limit the amount of current flowing through it the voltage drop across an LED when it is forward biased is called the Little Bits of Digital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook Page 15 Basic Electronic Concepts 0 FIELD EFFECT TRANSISTOR FET a 3terminal device gate source drain that provides a controlled impedance 0 Two basic types Nchannel potential on gate causes transistor to turn on low impedance between source and drain Pchannel potential on gate causes transistor to turn on channel Pchannel mi at Basic Electronic Concepts 0 FET acts as a controlled switch VCC Voltagecontrolled resistance R increase VGS a decrease RDS 39 Note normall V 20 Nchannel D V GS G I As RDS decreases power S delivered to load RL increases FETs are used to construct Complementary Metal Oxide Semiconductor CMOS logic circuits and can also be used to switch DC loads Little Bits of Digital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook 7 Page 16 Basic Electronic Concepts 0 BIPOLAR JUNCTION TRANSISTOR BJT a 3terminal device base emitter collector that provides a controed impedance 0 Two basic types Nchannel current flowing into base through emitter causes large current to flow from collector to emitter Pchannel current flowing out of base through emitter causes large current to flow from emitter to collector Ncha nel Pchannel C C B B E E Basic Electronic Concepts 0 BJT acts like a currentcontrolled switch a N P N LARGE C E small CURRENT B gtE current BJTs are used to construct TransistorTransistor Logic TTL and can also be used to switch high voltagecurrent DC loads Little Bits ofDigital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook 7 Page 17 Basic Electronic Concepts 0 INTEGRATED CIRCUIT IC a collection of logic gates andor other electronic circuits fabricated on a single silicon chip 0 PROGRAMMABLE LOGIC DEVICE PLD an integrated circuit onto which a generic logic circuit can be programmed and be subsequently erased and reprogrammed o COMPUTER a digital device that sequentially executes a stored program 0 MICROPROCESSOR a singlechip embodiment of the major functional blocks of a computer Basic Electronic Concepts 0 MICROCONTROLLER a complete computer on a chip including integrated peripherals memory analogtodigital conversion serial communications pulse width modulation timers network interface 0 SOCIALLY REDEEMING something that has inherent value like studying digital systems design 0 DIGIJOCKETTE a person who enjoys learning about digital systems Little Bits ofDigital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook Page 18 200607 Edition by D G Meyer Introduction to Digital System Design Module lB Logic Signals and Gates Reading Assignment 3rd Ed pp 7995 4th Ed pp 7996 Instructional Objectives 0 To learn a definition of Boolean algebra c To learn about the three major operators in Boolean algebra and the symbols used to represent them 0 To learn about the basic logic gates that are used to implement digital circuits 0 To learn about the circuits that are used to implement logic gates Little Bits ofDigital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook Page 19 Outline 0 Definition of Boolean Algebra 0 Logic signals and assertion levels 0 Combinational digital logic circuits 0 Boolean s big three operators 0 Logic families 0 CMOS logic 0 Switch analogies and implementations Boolean Algebra 0 Definition A Boolean Algebra is a triplet K 0 consisting of a finite set of elements K subject to an equivalence relationship and two binary operators denoted OR and 0 AND such that for every element X and Y contained in K the operations X Y and X 0 Y are uniquely defined and described later are satisfied Little Bits of Digital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook Page 110 Boolean Algebra 0 Definition An equivalence relation is some relation R defined on a set K which satisfies the following three basic properties for every X in the set K the relationship XRX holds for every X and Y in the set K the relationship YRX holds whenever the relationship XRY holds for every X Y and Z in the set K if the relationships XRY and YRZ hold then the relationship XRZ holds Boolean Algebra 0 Definition A binary variable X is a two valued quantity such that ifX 1thenX0 ifX 0 thenX1 oK01 Little Bits of Digital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook Page 111 Boolean Algebra 0 Huntington s Postulates P1 The operations are closed For all X and Y e K a X Y e K b X Y e K P2 For each operation there exists an identity element a There exists an element 0 e K such thatforallXe KX 0X b There exists an element 1 e K such thatforallXe KX1X Boolean Algebra 0 Huntington s Postulates P3 The operations are commutative For all X and Y e K a X Y Y X b X Y Y o X P4 The operations are distributive For all X Y and Z 6 K aXY ZXY XZ bX0YZXoYXoZ Little Bits of Digital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook Page 112 Boolean Algebra 0 Huntington s Postulates P5 For every element X e K there exists an element X e K called the complement of X such that a X X 1 b X o X 0 P6 There exist at least two elements X and Y e K such that X at Y Logic Signals o A logic value 0 or 1 is often referred to as a ginary digit or o The words LOW and HIGH are often used in place of 0 and 1 to refer to LOW a signal in the range of lower voltages eg for CMOS logic which is interpreted as a logic 0 HIGH a signal in the range of higher voltages eg for CMOS logic which is interpreted as a logic 1 Little Bits of Digital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook Page 113 Logic Signals 0 Note The assignment of 0 and 1 to LOW and HIGH respectively is referred to as a or simply positive logic a positive logic signal that is is in the HIGH state and is therefore referred to as an active high signal a positive logic signal that is is in the LOW state Logic Signals o The opposite assignment 1 to LOW and 0 to HIGH is referred to as a logic convention or negative logic a negative logic signal that is asserted is in the LOW state and is therefore referred to as an signal a negative logic signal that is negated is in the HIGH state Little Bits of Digital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook Page 114 Logic Signals o A logic circuit can be represented as simply a black box with a certain number of inputs and outputs 39 KM o Since the inputs of a digital logic circuit can be viewed as discrete 0 and 1 values the circuit s logical operation can be described using a table that lists discrete 0 and 1 Combinational Circuits o A logic circuit whose outputs depend only on its current inputs is called a o A can be used to fully describe the operation of a combinational logic circuit a Three basic logic functions AND OR and NOT can be used to build digital combinational logic circuit idea of Little Bits of Digital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbooki Page 115 Boolean s Big Three 0 An only if all of its inputs are 1 0 An or more of its inputs are 1 o A opposite of its input value 1w v xon x E lt x i Aiaax Aaiolt a l l l gate produces a 1 output if and gate produces a 1 output if one gate usually called an inverter produces an output value that is the x NOTX a l t u inversion bubble Another 10 Two 0 A AND gate s output 0 A OR gate s output x n X a T in V x v XNANDY o u l o 1 x a l l l o cicax gate produces the opposite of an gate produces the opposite of an v Avo N3R uwl XNORY 1 o a o Little Bits ofDigital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook Page 116 Time Matters 0 Logic gates require a certain amount of think time to produce a new output in response to changing inputs referred to as the of the gate 0 The propagation delay of a logic circuit may vary depending on whether its output signal is transitioning from lowtohigh rise propagation delay or from hightolow fall propagation delay 0 A can be used to show how a logic circuit responds to timevarying input signals Time Matters 0 Time response ofa combinational circuit X V XV X39 r XV xwvwz V39 xnvw il j TlME gt Little Bits of Digital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior ofDigilal Circuits Lecture Workbook 7 Page 1717 Logic Families 0 There are many ways to design a digital logic gate from mechanical relays and vacuum tubes to microscopic transistors o The most successful bipolar logic family is TransistorTransistor Logic o Complementary MetalOxide Semiconductor circuits now account for the vast majority of the worldwide Integrated Circuit market 0 CMOS logic is both the most capable and the easiest to understand commercial al logic technology CMOS Logic 0 CMOS logic levels Suv Loom iHlGHl m Lani a mom voltages e n the voltage range 5 Little 5m ofngm Wisdom 2006707 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook 7 Page 118 CMOS Logic 0 MOS transistor Modeled as a 3terminal device that acts like a In digital logic applications a MOS transistor is operated so that its resistance is either very high transistor is quot or very low transistor is quot CMOS Logic 0 There are two types of MOS transistors Nchannel MOS NMOS 62 Voltagecontrolled resistance Vos a Ros Note norrmiiy v65 2 o G Gate S Pchannel MOS PMOS 7 S Voltagecontrolledresistance G we VGS RDS we diam Note normally Vos 5 0 D Littlz Bits 0fDigital VWsdom 200507 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook Page 119 m suv Vrm Qt Indianth quv v H or mm H Basic CMO m m 9 a n J Mann2 on L a on 50 Hr 5 o H on an 00 1L VouFL M V1 M u v S Inverter Circuit 2U WE RE am when w xv 5 Law W W My my th w III 739 gt a Q 0 w w 2 L off on aquot on H H c on an on H L on oquot OH on H H on aquot on cquot L Little Bits of Digital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior ofDigital Circuits Lecture Workbook 7 Page 120 Basic CMOS NOR Gate 0quot Vi 7 m A W44 g2 W E 439 23222353 A o u o QDH L H L on oi oi on H mm Home New io Ixrr rrr N on o on o Exercise Transform this 2input NOR gate into a 3input NOR gate bn A FA o a il ow LZZZIE Bu Uszgztal Wlsdum 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook Page 121 200607 Edition by D G Meyer Introduction to Digital System Design 1 Module 1C Steady State Electrical Behavior of CMOS Circuits Reading Assignment 3rd Ed pp 96113 4th Ed pp 96114 Instructional Objectives 0 To be able to read and understand device data sheets and specifications in order to create reliable and robust realworld circuits and systems 0 To be able to use data on logic levels to calculate the DC noise margin of a circuit 0 To be able to use data on sourcing and sinking currents to calculate fanout c To learn about the deleterious side effects of excessive output loading unused inputs noise spikes and electrostatic discharge Little Bits ofDigital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook Page 122 Outline 0 Overview 0 Data sheets 0 Noise 0 Logic levels and noise margins o Sourcing and sinking current 0 Nonideal inputs 0 Fanin and Fanout 0 Effects of loading 0 Unused inputs 0 Current spikes and decoupling o Electrostatic discharge Overview o Obiective To be able to design real circuits using CMOS or other logic families need to ensure that the is valid for a given circuit need to provide adequate engineering to ensure that a circuit will work properly under a variety of conditions need to be able to read and understand data sheets and specifications in order to create reliable and robust realworld circuits and systems Little Bits of Digital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuim Lecture Workbook 7 Page 123 Data Sheet for a Typical CMOS Device or m Ermmi cummmmmcs OVER OPERATING RANGE nu numle onmuum Apply mlh mlwmlse pmnm Commercial A r4nc in awe m v 5 wow Mllimry 1 45m m lust v L a ll v 4er Sym Parameter Test canuluansv MIquot 1 2 Maxi Unit rm Input mu m Guaranteed iugir HlGH Ml 3 11 v m lnpul iuw lrvri Guaranteed luvir mw my 7 l V IN Input man runrm l M 1 lnpul iuw i39w renl 4 M rm mm mm wing 39 4 z 4 2 v the mm m ull l urnm 39 74 m i 4 41545 v wquot Qumul men vnlmg 3 m 4 3 v um I v y Qumul LOW mirage m I l m a 17 a IEr Qulvwml mw 2 m M Apply mnml T n im 1U 0 SWITCHING rHARMTERmrcs ova oPERA L lNG RANGE r an F sym pmmmm m cmmm mm Typ Max Unit 1 minimum rlehv A or a w v 9 m n q 1mm Lap inn lWUV a in FF 4 Powr rdisupnunn a iilnmnu w gala Nn ml 22 pF Noise 0 The main reason for providing engineering design margins is to ensure proper operation in the presence of 0 Examples of noise sources cosmic rays magnetic fields generated by machinery power supply disturbances the of the logic circuits themselves Little Bits ofDigital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook 7 Page 124 Logic Levels and Noise Margins 0 Typical inputoutput transfer characteristic of a CMOS inverter Problem Typical NOT guaranteed LOW ed HlGH Logic Levels and Noise Margins 0 Factors that cause the transfer characteristic to vary power supply voltage temperature output loading conditions under which a device was fabricated 0 Sound engineering practice dictates that we use more specifications for LOW and HIGH Little Bits ofDigital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior ofDigital Circuits Lecture Workbook 7 Page 125 Logic Levels and Noise Margins 0 Definitions VOH the minimum volta e mm 9 in the state VIH the minimum voltage mm guaranteed to be recognized as a VIL the maximum volta e max 9 guaranteed to be recognized as a VOL the maximum volta e max 9 in the state Logic Levels and Noise Margins I CMOS levels are typically a function of the power supply rails W VOHmm Vcc 01 v H s m v VHmm 70 of Vcc ABNORMAL VLmax 30 of Vcc l W V0Lmax GND o1v a Low DC noise margin is a measure of how much noise it takes to a worst case output voltage into a value that may not be recognized properly by an input Lme 5m ofDngtal Wisdom 2005 07 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook Page 126 Logic Levels and Noise Margins 0 Calculation of DC noise margin or the noise immunity margin DCNM min VOHmin Vlein VILmalx VOLmalx 0 Example HCseries CMOS DCNM Sourcing and Sinking Current a CMOS gate inputs have a very high impedance and consume very little current from the circuits that drive them IL the maximum that flows into the in the state IH the maximum that flows into the in the state For CMOS logic the input current is very small it takes very little power to maintain a CMOS input in either the HIGH or LOW state Little Bits of Digital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook Page 127 Sourcing and Sinking Current o Often times gate outputs need to drive devices that require a nontrivial amount of current to operate called a load or load a When driving a resistive load the output of a CMOS circuit is not nearly as as described previously o In either output state the CMOS output transistor that is on has a nonzero resistance and a load connected to its output terminal will cause a voltage drop across this resistance Sourcing and Sinking Current o lC manufacturers specify a maximum load for the output in each state HIGH or LOW and guarantee a worstcase output voltage for that load OLmax the maximum that the can sink in the state while still maintaining an output voltage no greater than VOLmax OHmax the maximum that the can source in the state while still maintaining an output voltage no less than VOHmin Little Bits of Digital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook 7 Page 128 Sourcing and Sinking Current 0 Circuit definitions of 0Lmax and 0Hmax lli vw W m I CMOS emit CMOS E lt 8 ltgt i m ltgt n rm m y m 444m F H 39mm ie ve Hm 1mm W 1 i i current arrow NOTE Convention is for the inputoutput current arrows to point in Sourcing and Sinking Current 0 Most CMOS devices have two sets of loading specifications device output connected to other CMOS inputs which consume very little current device output connected to resistive loads devices that consume significant current Note With DC loads the output voltage swing of a CMOS circuit may significantly Little Bits ofDigital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook 7 Page 129 Nonideal Inputs o If the inputs to a CMOS circuit are not close to the Vcc I GND rails the on transistor may not be on and the of transistor may not be off causing power dissipation of the device to 1SUV m lt 3 won tquothle39W 1 uvnmuw lt 2in Fanin 0 Definition The number of inputs a gate can have in a particular logic family is called the logic family s o CMOS gates with more than two inputs can be obtained by extending the series parallel circuit designs eg for NAND and NOR gates illustrated in the previous lecture o In practice the additive on resistance of series transistors limits the fanin of CMOS gates to a relatively small number 0 Gates with a large number of inputs can be made faster and smaller by cascading gates with fewer inputs Little Bits ofDigital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuim Lecture Workbook 7 Page 130 Fanout 0 Definition The number of gate inputs that a gate output can drive its worstcase loading specifications depends on characteristics of both the output device and the inputs being driven must be examined for both the sourcing and sinking cases practical limitations due to capacitive loading AC vs DC fanout Fanout min IOHmaXI IIH 0Lmax I IIL Data Sheet for a Typical CMOS Device or m Ermmi CHARACTERISHCS OVER OPERATING RANGE Thr following mulmum apply mum m we pln rd Commrrzml 7A ltmr to mm m 5 mum mum rA 755W in 425T i L 5 nv mm sym hamlet Test cannulang m mm Max Uml v Input man We Guarantean lagir um um 31 v v Input mw lad Guarantean lam LDWlevul Ms V IN Input mm mme l d 1 Input um mmquot 7 d vK Ham mm voltage U r 71 2 v 1m Shun quotum rurrenl vLL Mnx l l ur ND 735 mA 11 Oulpul man wing I 72quot i 4 391 39x 99 V luuzrhnK m H v vH Oulpul row voltage I t 2quot A mquot n 39 V 1w 4 m a n ms in Quincequot lower 2 m m supply mmm um an or v 1U 0 swncHiNG mmacmzmxcs ova anRmNn 3mm 5 an pF sym parmmra Test Enndlu39ons Mln Typ Mu um 1 Prlvpugnlmn inlay A MB m y s m m r lupulmmumnli n nv 3 in FF L1 Powermsupnmm upnulnm w W Nu lnml 21 p Little Bits ofDigital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook Page 131 Fanout o Example HCseries CMOS Fanout min IOHmax IIH IOLmalx IIL Note DC fanout is considerably greater in this case if the output voltage swing is degraded but DCNM is lower and signal transitions times are longer causing speed degradation Practical Fanout o In a practical application a gate output may drive a mixture of loads a HIGHstate fanout The sum of the Ileax values of all the driven inputs must be less than or equal to the IOHmax of the driving output a LOWstate fanout The sum of the Ileax values of all the driven inputs must be less than or equal to the IOLmax of the driving output The practical fanout is the of the HIGH and LOWstate fanouts Little Bits of Digital Wisdom 200607 Edition by D G Meyer Static and Dwamic Behavior of Digital Circuits Lecture Workbook 7 Page 132 Effects of Loading 0 Loading a gate output beyond its rated fanout can have several deleterious effects in the LOW state the output voltage VOL may increase beyond VOLmax in the HIGH state the output voltage VOH may fall below VOHmin output rise and fall times may increase beyond their specifications the operating temperature of the device may increase thereby the of the device and eventually causing device Unused Inputs 0 Unused spare CMOS inputs should never be left unconnected o A small amount of circuit noise can temporarily make a floating input look HIGH 0 Instead unused inputs should be tied to another input of the same gate tied HIGH for AND and NAND gates tied LOW for OR and NOR gates 5V lat lhl T icy x Z lt gm mm m c xz k W n 2 x7 Little Bits ofDigital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook Page 133 Current Spikes and Decoupling a When a CMOS gate output changes state the p and nchannel transistors are both partially on simultaneously causing a a Current spikes often show up as on the power supply and ground connections a between Vcc and GND must be distributed throughout a printed circuit board PCB to supply extra current during transitions to CMOS le VERY IMPORTANT FOR SENIOR DESIGN PROJECTS Electrostatic Discharge a CMOS device inputs are subject to damage from electrostatic discharge ESD o Apply these precautions in lab before handling a CMOS device touch a source of transport CMOS devices in or tubes handle circuit boards containing CMOS devices by the touch a ground terminal on the board to earth ground before poking around with it Little Bits of Digital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook Page 134 200607 Edition by D G Meyer Introduction to Digital System Design 1 Module 1D Dynamic Behavior of CMOS Circuits Reading Assignment 3rd Ed pp 113122 4th Ed 114128 Instructional Objectives 0 To learn what factors influence the performance of a CMOS circuit 0 To learn the definition of transition time and how to measure it c To learn how to analyze and estimate the transition times of a CMOS circuit 0 To learn about the effects of capacitive loading on a CMOS circuit 0 To learn the definition of propagation delay and how to measure it c To learn about the sources of power dissipation in a CMOS circuit Little Bits ofDigital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook Page 135 Outline 0 Overview 0 Transition time o Capacitive loading 0 Propagation delay 0 Power consumption Overview o The and of a CMOS device depend on the dynamic AC characteristics of the device and its load a Logic designers must carefully examine the effects of output loading and redesign where the loading is too high a Speed performance depends on two characteristics Little Bits of Digital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook 7 Page 1 as Transition Time n The amount of time that the fa logic circuit takes to change from one state to another rise time tr OrtTLH the an output signal takes to from lowtohigh fall time tf OrtTHL the an output signal takes to from hightolow 0 Gate outputs can change state ie with a transition time of zero because they need to of the wig and other components they drive Transition Time ideal less ideal L 4 rp l V reality l i f M Little 8125 Ongxtal VWsdom 200507 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook Page 137 Transition Time a To avoid difficulties in defining the endpoints are normally measured one of two different ways at the boundaries of the valid logic levels ie VIHmin and Vleax at the 10 and 90 points of the output waveform o Using the first convention above the rise and fall times indicate how long it takes for an output signal to pass through the undefined between LOW and HIGH Transition Time a The transition times of a CMOS circuit depend mainly on two factors o called an arises from at least three different sources output circuits including transistors internal wiring and packaging wiring that connects a gate output to other gate inputs input circuits including transistors internal wiring and packaging Little Bits of Digital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior ofDigital Circuits Lecture Workbookr Page 133 Transition Time 0 A gate output39s load can be modeled by an equivalent load circuit with 3 components RL and VL represent the they determine the steady state voltages and currents present and do not have much effect on transition times CL represents the AC load It determines the voltages and currents present while the output is changing as well as how long it takes to change from one state to another Equivalent Circuit for Transition Time Analysis of a CMOS Output in A Y n V game mu m umumw was 4 Itquot V Rl aw in m AAAK lt lt It i Little 3m afngxtal Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook Page 139 Model of a CMOS LOWtoHIGH Transition with Negligible DC oad v in v v 51 V g u Carin l 1 W m lt g gt Mi 3 1mm Av load Act land 1 mm W Hm llN Dquot ll D u 1U 41 lt lt I gt an gt z IMQ 03911 y lt I Inopl 3 mupr 1quot 2am gt v m l M11 in 2 l n Model of a CMOS HIGHtoLOW Transition with Negligible DC Load tucmw x 1Tiuv m A lll lt 3 1mm 3 gt um AC om AC loam V ltU V V um v um rm l D m 5 1 IN U C lt l y gtgtIMn gt mnn 0 lt lt mu p17 l E me Little Bits of Digital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook 7 Page 140 Example 0 Given that a CMOS inverter s Pchannel MOSFET has an ON resistance of 2000 that its Nchannel MOSFET has an ON resistance of 1000 and that the capacitive or AC load CL 200 pF calculate the fall time ll rilH i Jam l w l V m 3m lt i39 39l v r39l39i iiww l mu i L UM i r gt min loan W T lelllil 1 my D l t l j v v Example 0 Fall time calculation t RnquotCL39ln VowVon t1012tn Vnut I 50 2010399n vnut I 50 t35 2010399n l50 713 ns t15 2010399n l50 2408 ns fall time ns Little Bits ofDigital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook Page 141 Transition Time a Conclusion An increase in load capacitance causes an increase in the RC time constant and a corresponding increase in the output transition risefall times a Load capacitance must be to obtain high circuit performance this can be achieved by minimizing the number of inputs driven by a given signal creating multiple copies of the signal using buffers careful of the circuit Transition Time a Rule of Thumb In practical circuits the transition time can be using the RC time constant of the charging or discharging circuit a Final note Calculated transition times are to the choice of logic levels ie VIHmin and Vleax Little Bits of Digital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook Page 142 Example 0 Given that a CMOS inverter s Pchannel MOSFET has an ON resistance of 2009 that its Nchannel MOSFET has an ON resistance of 1009 and that the capacitive or AC load CL 200 pF estimate the fall time and rise time Fall time estimate Rise time estimate RN X CL X RP X CL X ns ns Propagation Delay o Definition The electrical path from a particular input signal of a logic element to its output signal is called a o Definition The amount of it takes for a change in an input signal to cause a corresponding change in a gate s output signal is called the tp o The propagation delay for an output signal going from to tPLH may be different than the propagation delay of that signal going from to tPHL Little Bits of Digital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior ofDigital Circuits mm Workbook 7 Page 143 Propagation Delay Ignoring V rise and fall times yum NH f llll Measured at V mid oints of Vom MH f vlll Emma mquot m m m W um mamqu Propagation Delay 0 Several factors lead to propagation delays in CMOS circuits the rate at which transistors change state is in uenced both by semiconductor physics and the circuit environment input signal transition time input capacitance and output loading multistage devices eg noninverting gates may require several intemal transistors to change state before the output can change state Little 3m afngxtal Wisdom 200507 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook Page 144 Example Find each of the X following rounded to the nearest 12 ns assume each division is 1 ns Rise propagation delay tPLH ns Fall propagation delay tPHL ns Rise time tTLH based on Wakerly s de nition ns 30 70 Rise time tTLH based on standard 1090 definition ns Fall time tTHL based on Wakerly s de nition ns 70GO Fall time tTHL based on standard 90 10 definition ns Power Consumption 0 Definition The power consumption dissipation of a CMOS circuit whose output is not changing is called quiescent power dissipation 0 Most CMOS circuits have static power dissipation o CMOS circuits only dissipate a significant amount of power during this is called dynamic power dissipation Little Bits of Digital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook Page 145 Power Consumption o Sources of dynamic power dissipation the partial shortcircuiting of the CMOS output structure eg when the input voltage is not close to one of the power supply rails called PT power due to output the capacitive load on the output power is dissipated in the on resistance of the active transistor to chargedischarge the capacitive load called PL power due to chargingdischarging Power Consumption a Total dynamic power dissipation PT PL is proportional to the of the power supply voltage times the transition frequency a Conclusions power dissipation increases as the frequency of operation increases reducing the power supply voltage results in a reduction of the power dissipation Little Bits of Digital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook Page 146 Example o A microcontroller dissipates 100 mW of power when operated at a clock frequency of 10 MHz What will be the its power dissipation if the clock frequency is reduced to 2 MHz Answer X 100 mW mW Example o A microcontroller dissipates 100 mW of power when operated at a supply voltage of 5 VDC What will be the its power dissipation if the supply voltage is reduced to 3 VDC Answer X 100 mW mW Little Bits of Digital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook Page 147 200607 Edition by D G Meyer Introduction to Digital System Design l Module lE Other CMOS InputOutput Structures and Logic Families Reading Assignment 3 Ed pp 123142 149154 166171 4th Ed pp 129154 158170 Instructional Objectives 0 To learn about specialized CMOS circuit structures including Schmitttrigger inputs threestate outputs open drain outputs 0 To learn what wired logic is and how it works 0 To lean how to interface TTL and CMOS gates Little Bits ofDigital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook Page 148 Outline 0 Overview 0 Schmitttrigger inputs 0 Tristate outputs 0 Open drain outputs 0 Driving LEDs 0 Wired logic 0 TTLICMOS interfacing Overview o The basic CMOS circuit has been tailored in many ways to produce gates for specific applications a This circuit tailoring has been motivated by the need for higher performance than can be achieved with standard NANDNOR gates conditioning noisy slowly changing logic signals allowing logic elements to communicate via buses Little Bits of Digital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook 7 Page 149 SchmittTrigger Inputs 0 Definition A is a special circuit that shifts the switching threshold depending on whether the input is changing from LOWtoHIGH or from HIGHtoLOW o The difference between the two thresholds is called mm Symbol r g quot usedto denote hysteresis ll 19 Hi Comparison of an Ordinary Inverter to a Schmitt Trigger for a Noisy Slowly Changing Input Signal in W quotum I HlGH Regular Inverter Low mm Schniitt trigger LOW little Bits of Digital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook Page 150 Schmitt Trigger Inputs o Observations Schmitttrigger inputs have margin than ordinary gates for Distorted logic signals of this type typically occur in such as NO buses and computer interface cables Rule of Logiclevel signals can be sent reliably over a cable for only a ThreeState Logic o Definition A gate output that has a third electrical state is called a output or output a This third electrical state is called the high impedance or state o In the high impedance state the gate output effectively appears to be from the rest of the circuit a Threestate devices have an extra input typically called the OE for enabling data to flow through the device when asserted or placing the output in the high impedance state when negated Little Bits of Digital Wisdom 200607 Edition by D G Meyer Static and Dwiamic Behavior of Digital Circuits Lecture Workbook 7 Page 151 CMOS ThreeState Buffer my in EN c a w m EN 2 Irxr a mom w wmz w wmz m w L w m H Ixrr rrII m r n rxrr 0 ON The most common use of these devices is to create data buses collection of signal lines over which computational subsystems can bidirectionally send and receive data OpenDrain Outputs 0 Definition A CMOS output structure that does not include a pchannel transistor is called an 0 An opendrain output is in one of two states LOW or open ie disconnected 0 An is used to indicate that an output is open drain 0 An opendrain output requires an external pullup resistor to pull it high in the open state since the output structure does NOT include a pchannel Little Bits ofDigital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook 7 Page 152 OpenDrain CMOS NAND Gate nl A Q 2 Z 0quot 0quot open on on open an of open on on L H 02 A 8 z 3 11 N Symbol that denotes an opendrain output OpenDrain Gate Driving a Load 5 39 t u rvun39m puttup a Wm H asst e 2 Ram Note RIse tIme gt of an open drain output is A Q Z 0 much slower B jO 39 than that of a standard gate upmmm m rput E Vunr nv t t t t u in z 5 Run time 7 W Little Bits ofDigital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook 7 Page 153 Driving LEDs 0 One application for opendrain outputs is driving lightemitting diodes LEDs B u Q i This is Driving LEDs 0 Standard CMOS gate outputs can also be used to drive LEDs either by sinking current LOW or sourcing current HIGH n Question Which method is preferred Little Bits ofDigital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook Page 154 Example Based on the data provided in Table 33 on page 98 of the course text calculate the value of the LED current limiting resistor for the worst case current sinking configuration Also calculate the amount of power dissipated by the current limiting resistor Assume VLED is 19 volts r r DC ugcrmmt cumsrmsms oven nammwc rumor m mum Lunrlmnns apply MIN utlienvnr Wm Cunmiemldl 7lt1l c lu xm M eaovlm Mmury 5457an uzw menuv um Sym Parameter Test CondlLr39nnW Min Typrll Mu Unll v mm mm rm cumm lug man Mai 15 v l lnpm Lowml cumm luuu mme w v I mm mm rurrrm I l M 1 mm LOW um nl v a M lg camp amat volume 3 mA 417 a g V A Sheri mm Lurrum xx W l39u mm 735 mA V I 72 4 4 I 499 V ifquot mum HlGH mm quot W I 194 M r a 4 3 v I 2n m n I v V OulpulLDWvullnge K Lquot A I I AmA u n 4133 i came mw v xx 2 m M supply um run v e an or v 1U 41 swm l unc mmxcrmsncs ware mammals RANGE r all Dr SW Parameter 15 Conditions Mln 7w Mu mm a Propagation LlpLry Aanl rnY e 19 n5 5 Inpul mymcnance vmzuv 3 m a c pnwmsapammpmmm page Nu m 22 a m WWquot Wu WarW tamm mm n 25 amt W W mm lquot m an a mm W m a um Hidw y M Little Bits of Digital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook 7 Page 155 SOLUTION VR 50 VLED 50 19 quot V 40 mA NOTE Here use value indicated for of V I 033 VDC R VRIIOL a PR R x IOL2 x 00042 milliwatts NOTE Can also calculate power dissipation of resistor using VR x IOL LED or VR1lR any th dam Example Based on the data provided in Table 33 on page 98 of the course text calculate the value of the LED current limiting resistor for the worst case current sourcing configuration Also calculate the amount of power dissipated by the current limiting resistor Assume VED is 19 volts l n Little Bits ofDigital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook 7 Page 156 SOLUTION VR VED 19V NOTE Here use value 40 mA indicated for of V R an39ou 9 384 VDC PR R x Itquot2 x 00042 milliwatts NOTE Can also calculate power dissipation of resistor using VR x 0H or VR1lR A 4 Wired Logic 0 Definition Wired logic is performed if the outputs of several opendrain gates are tied together with a single pullup resistor Va T u l 91 53 Q Z T NOT an 3W actual 4 gate Caution Little Bits ofDigital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook 7 Page 157 Illustration of Fighting HlGH E r mm in pull men F4 91 7 z m LOWHA 1 a u hr 2 Illustration of what happens if two ordinary CMOS gate outputs are tied together don t try 9 W W this at home mer w well 4 w wmqmpullLOW Pullup Resistors o In opendrain applications two calculations bracket the allowable values of the pullup resistor R LOW The sum of the current through R plus the LOW state input currents of the gate inputs driven the IOLmax of the active device HIGH The voltage drop across R in the HIGH state the output voltage below the VIHmin of the driven gate inputs Little Bits of Digital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook 7 Page 158 Pullup Resistor Calculation High State Here the pullup resistor must be no more than the value Rmax such that the voltage drop across it does not exceed 50 24 26 V when 60 uA of current is flowing through it Applying Ohm s Law we find that Rmax is 26000006 43333 ohms Pullup Resistor Calculation LOW State Here the constraint is that the pullup resistor must be chosen such that the voltage drop across it must be at least 50 04 46 then 32 mA is flowing through it Hm Luv a law 7 lOW 7 a mw 7 9 luv 7 Applying Ohm s Law we find that Rmin is 4600032 153113 1438 ohms 1438 s R 5 43333 VI Little Bits ofDigital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook Page 159 Example Given the following circuit with all of its inputs connected to a LOW logic level We L E 2 74m OD If the offstate leakage current of each of the 74x03 opendrain NAND gate outputs is 5 M and the lIH required by the 74x04 inverter is 90 uA determine the value of the pullup resistor R to obtain a VIH of 49 V at the 74x04 input 50 VDC Solution 100 A Current through R R Voltage drop across R VR R VRlR Q Little Bits of Digital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook Page 160 CMOSTTL Interfacing o A typical system design may contain a mixture of CMOS andor TTL families due to o It is important for a designer to understand the implications of connecting TTL outputs to CMOS inputs and vice versa o Factors to consider CMOSTTL Interfacing o All of the CMOS and TTL devices that we will discuss have part numbers of the form 74FAMnn where FAM is an alphabetic mnemonic and nn is a numeric function designator o Devices in different families with the same nn perform the same function a The prefix 74 has no social significance it was made popular by Texas Instruments o The prefix 54 is used to signify milspec parts wider temperature range Little Bits of Digital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook 7 Page 161 TTLCMOS InputOutput Levels OUTPUTS 5 0 lNPUTS l or hum i ui um 1H lmm MLmM HIGH HC HCT 384 385 HC VHC VHC VHCT 380 i lt7 Highrslaie DC noise margin LS S ALS AS F 27 20 L5 5 ALS AS F HCT VHCT FCT Holdmwmo cnlel ABNORMAL i 1 3 HC VHC 08 LS S ALS AS F FCT 03955 HCT VHCT FCT LS S ALS AS F 05 VHC VHCT 044 7 LOW IaE HC HCT 133 LOW 0 DC noise margin Review Quiz Digital Jeopardy 1 The maximum input current for any value of input voltage The maximum capacitance of an input The maximum voltage that an input is guaranteed to recognize as LOW The minimum voltage that an input is guaranteed to recognize as HIGH Little Bits of Digital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook Page 162 Review Quiz Digital Jeopardy 2 The maximum current that an output can supply in the LOW state while driving a CMOS load The maximum current that an output can supply in the LOW state while driving a TTL load The maximum voltage that a LOW output is guaranteed to produce driving a CMOS load The maximum voltage that a LOW output is guaranteed to produce driving a TTL load Review Quiz Digital Jeopardy 3 The maximum current that an output can supply in the HIGH state while driving a CMOS load The maximum current that an output can supply in the HIGH state while driving a TTL load The minimum voltage that a HIGH output is guaranteed to produce driving a CMOS load The minimum voltage that a HIGH output is guaranteed to produce driving a CMOS load Little Bits of Digital Wisdom 200607 Edition by D G Meyer

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