Class Note for ECE 372 at UA
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This 5 page Class Notes was uploaded by an elite notetaker on Friday February 6, 2015. The Class Notes belongs to a course at University of Arizona taught by a professor in Fall. Since its upload, it has received 15 views.
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Date Created: 02/06/15
SPI serial peripheral interface Motorola speci c Valvano Chapter 77 synchronous interface upto 1 MbiUsecond 8 bit transfer at once Can use more than one device With 7 Daisy chain or 7 Chip select Micro controller 6811 Peripheral r enable E MSB LSB 35 39 CS MSB LSB 8 Bit SPDR MISO lt MISOlt 8 Bit SPDR 5 MOSI gt MOSI i SCK gt SCK 5 GND GND 76543210 76543210 SCK T R T R v b 7 A 397 I t l 1 I i I Data Avail B 7 BH 6 X l u I 39 I Control Baud Mode 0 Primary or Secondary Controller 0 Clock Polarity 0 Clock Phase Arm Interrupt transmission complete Ability to make output open drain multiple devices or standard logic SPIF transmission complete WCOL write collision MODF mode fault If device is secondary controler SCK is input Primary Controller Out Secondary Controller In MOSI is input MISO is output SPCR1 Bit 7 SPIE enable SPI interrupt Bit 6 SPE eable SPI Bit 5 DWOM CMOS or open drain Bit 4 SPTIE enables Transmit interrupt if HC12 is the slave Bit 3 CPOL polarity Bit 2 CPHA phase Bit 1 SSOE slave select output enable Bit 0 LSBFE send LSBit rst SPCRZ New in HC12 SPIBR Selects Baud rate CPOL CPHA Illustration of polarity and phase va clock cycle it 1 2 3 4 5 6 7 8 Trans Complete sex if CPOL 0 scK if 39 39 quot Clock CPDLI sample p l I ll g i xmsaX5X5X4X l J J valid I l szlxm l l l 3 mm l l l l Available 25va XMSBX6X5X4X3X2 IXLSE valid usually CPOL 0 CPHA l or CPOL l CPHAl SPISR Status register Bit 7 SPIF transfer complete Bit 6 0 Bit 5 SP TEF transmit empty intenupt ag Bit 4 MODF mode fault error With Primary Secondary controller selection Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 SPDR Data register 8 bit Example 4 channel 12 bit AD Converter 12 bit gt needs 2 transfers 4 channel gt needs channel select MSB rst AD converter is peripheral samplessends data at rising edge of clock therefore SP1 needs to send data at falling edge of clock CPOL0 CPHA0 or CPOL1 CPHA1 Input 025V 2MHZ max gt 83 ksamplessecond max 6811 SS CLK iT i MOS MISC i v lt 5v 01 MFJrr VDD MAX1247 W A man ADC E 25 w C5 C30 analog SCLK CH my C Q Do CH3 DGND AGND COM J r J 4 Channel 12 bit AD Converter Software void ADinitilizeVoid DDRD 1 0X38 0011 1000 makes CS CLK MOSI output MISO input PORTD 1 0X20 0010 0000 pulls CS high no activity requested SPCR 0X50 0101 0000 SPIE0 SPE1 DWOM0 MSTR1 CPOL0 CPHA0 CPR10 CPRO0 is 1 MHz speed unsigned int ADreadunsigned char channel returns 16 bit integer requests 8 bit channel unsigned int data PORTD amp 0X20 CS0 indicates master logical and with inverted 0X20 SPDR channel request channel whileSPSRampSPIF0 wait until SPIF is set DataSPDR clear SPIF ag SPDR0 start ADC whileSPSRampSPIF0 wait until SPIF is set DataSPDRltlt8 read MS byte SPDR0 second transfer whileSPSRampSPIF0 wait until SPIF is set DataSPDR read LS byte PORTD 1 0X20 CS1 end transfer Return datagtgt3 right justify
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