Class Note for C SC 252 with Professor Homer at UA
Class Note for C SC 252 with Professor Homer at UA
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Date Created: 02/06/15
P1 elinm Read Chapter 4 Sections 45 to 48 4th edition Chapter 6 Sections 61 to 65 3rd edition 0 Laundry example washing 30 minutes drying 30 minutes folding 30 minutes stashing 30 minutes 0 If only one person s wash it takes 2 hours to complete 0 If several folks need to do laundry can do in 2 hours each sequential solution I 0 But the washer dryer folder and stasher are independent units CSc 252 7 Computer Organization 1 8 7 Pipelinng Pipeline basics 0 Pipelined laundry takes 35 hours for four loads I I I I I I O 0 Pipelining 0 Does not help the latency of a single tasks still takes 2 hours to do one person s laundry 0 Does help the throughput of the entire work load 35 hours vs 8 hours 0 Multiple tasks operating simultaneously each using different resources 0 Potential speedup number of pipe stages 0 Rate limited by slowest pipeline stage 0 Unbalanced lengths of pipe stages reduces speedup 0 Time to ll pipeline and time to drain it reduces speedup CSc 252 7 Computer Organization 2 8 7 Pipelinng Pipeline basics continued 0 Consider the load word instruction 1w 50 0t0 Cyclel iCycleZ gCycle3 iCycle4 gCycleS lFetch RegDec Exec Mem Write 0 IFetch Instruction Fetch get the instruction from memory 0 RegDec Fetch values from Registers and Decode the instruction 0 Exec Execute calculate the memory address from which to load the word 0 Mem Read the word from Memory 0 Write Write the word to the Register CSc 252 7 Computer Organization 3 8 7 Pipelinng Pipeline basics continued 0 A more realistic picture Not all cycles take the same amount of time 0 Memory access is slower 0 ALU computation is slower 0 Register access is faster 0 Figure 426 page 333 4th edition There is a similar Figure 62 page 439 in the 3rd edition Instruction Register ALU Data Register Total Instruction class fetch read operation access write t1me Load word 1w 200 ps 100 ps 200 ps 200 ps 100 ps 800 ps Store word sw 200 ps 100 ps 200 ps 200 ps 700 ps R format add sub and or slt 200 ps 100 ps 200 ps 100 ps 600 ps Branch beq 200 ps 100 ps 200 ps 500 ps CSc 252 7 Computer Organization 4 8 7 Pipelinng Pipeline basics continued 0 Can improve performance by increasing the instruction throughput 0 3 load word ops 24 nanoseconds I 20 4O 600 800 100 120 1400 160 1890 20O 1W 81100t0 Instruction Reg ALU Data Reg fetch access A 800 Instruction Data lw s2200t0 PS fetch Reg ALU access Reg A Instruction 800 ps Re ALU 1w s3300t0 fetch g 0 Becomes 3 load word ops 13 nanoseconds I 20 40 60 80 100 120 1400 I I I I I I I 1w s1100t0 IHSftructlon Reg ALU Data Reg etch access 4 D I tI39u U D t W 52 200t0 200 ps nsfetcch on Reg ALU accaegs Reg ZUUp s lnSF39lth lOn Reg ALU Data Reg lw 53300t0 e C access 200 ps 200 ps 200 ps 200 ps 200 ps 0 Clock cycle time dependent on the slowest phases 200 picoseconds in this case CSc 252 7 Computer Organization 5 8 7 Pipelinng Building a Pipelined datapath 0 Need to re arrange some items from single clock cycle im plementation to split the data path into stages x IF 5 ID 3 EX 5 MEM 3 WE Instructlon fetch Instructlon decode E Execute or 3 Memory 5 erte 0 reglster flle read 5 address calculatlon 5 access 3 back M 5 5 u s 2 s 3 f E E E 5 k I I K t t t t E t i gt K x S l t um t i Read E dd E E I E register 1 Read E g E Read data 1 i l Read 5 I register 2 E E 5 Address I k x 13C E Ems Re glsters E E glster t Read Instructro R d ea data 3170 I Write d t 2 Address gt 1 I data a a E i M lnstructlon E t u memorV 5 S E Data X 1 n W 39t s 16 wind 32 dag memory a o E I gt 5 3 I CSc 252 7 Computer Organization 8 7 Pipelinng Building a Pipelined datapath continued 0 Add pipeline registers in between each pipeline stage IF ID EX MEM WB Instruction fetch Instruction decode Execute or Memory Write register file read l address calculation access back Read register 1 Read d I Read ata 1 Read I register 2 Address gt PC Wm Registers R d re 1s er ea Instruction Wat Read I Address data 1 3170 n 6 data 2 data M Instruction u memorV S Data X 1gn Write memor 16 extend 32 data y 0 CSc 252 7 Computer Organization 7 8 7 Pipelinng Building a Pipelined datapath continued 0 How big is each pipeline register How many bits are in each We ll need more bits before we are done IF Instruction fetch Read gt Address Instruction 3 170 Instruction memorV CSc 252 7 Computer Organization ID Instruction decode register file read Execute or address calculation Read register 1 Read Read data I register 2 Wlite Registers register Read wnte data 2 data Sign extend 32 MEM WB Memory Write access back Read Address data 1 M 11 Data X W te memor data y 0 8 7 Pipelinng Building a Pipelined datapath continued 0 Problem CSc 252 7 Computer Organization ID Instruction decode register file read Read register register Write data 1 Registers Read data 2 We know the number of the register to write on the 2nd clock cycle But we do not have the data to write until the 5th clock cycle We need to remember the number of the register until the 5th clock cycle 8 7 Pipelinng Building a Pipelined datapath continued 0 The write register value is stored in the IDEX register on cycle 2 then in EXMEM on cycle 3 then in MEM WB on cycle 4 The value is nally used on cycle 5 now larger by how many bits iggterl R d ea Read datal I Read registerZ Address Wme Registers Instruction regISter R d Read 3170 gt Write dagaz gt 2 Address data data Instruction memory I S Data 191 Write 1g extend 32 data memory CSc 252 7 Computer Organization 10 8 7 Pipelinng Building a Pipelined datapath continued 0 What makes pipelining easy 0 All instructions are the same length 0 Only a few instruction formats R type l type etc 0 Memory operands appear m in loads and stores 0 What makes it hard 0 Structural hazards suppose we have only one memory 0 Data hazards an instruction depends on a preVious instruction 0 Control hazards need to worry about branch instructions 0 We ll build a simple pipeline and look at some of these issues 0 Time permitting We ll talk about modern processors and What really makes it hard 0 Exception handling 0 Trying to improve performance with out of order execution etc CSc 252 7 Computer Organization 11 8 7 Pipelinng Representing Pipelines 0 Simpli ed drawing to enable us to talk about multiple instructions executing in sequence 0 Example the add command IF ID xIEIV WB 0 Full shading indicates combinational unit that is active on that stage 0 The shading on the right side indicates the unit is being READ on that clock cycle 0 Reads occur at the w of the clock cycle 0 The shading on the left side indicates the unit is being WRITTEN on that clock cycle 0 Writes occur at the beginning of the clock cycle ID 0 No shading indicates the unit is not being used on that clock cycle I xIEIV CSc 252 7 Computer Organization 12 WB 8 7 Pipelinng Representing Pipelines continued 0 Can help with answering questions such as 0 How many clock cycles does it take to execute this code 0 What is the ALU doing during clock cycle 4 What else is happening during clock cycle 4 0 Can use this representation to help understand datapaths through the CPU time flows down program execution d r lw 10 201 IF ID 1131 sub1123 IF ID ME1V WB X sw 12284 IF I ID xIElV WB CSc 252 7 Computer Organization 13 8 7 Pipelinng Pipeline Control 0 Control Wires are more or less the same ones we used before as per the single clock cycle implementation lnsiructi on Instrucu39 on Branch MemRead MemtoRe g 094 31726 Instruction memory The w instruction uses bits 20 16 The arithmetic add sub and or I V 0111103 slt instructions use bits 15 11 CSc 252 7 Computer Organization ALUOD MemWrite ALUSrc Re gWrite I Re ad register 1 Re ad register 2 Write register Write data Re ad data 1 Registers Re ad data 2 14 lnsiructi on 50 animal 9N paa d39uraw Data W te memory data 8 7 Pipelinng Pipeline Control continued 0 A speci c example the number of the register to which the result is written 0 The 1w instruction uses bits 20 16 0 The arithmetic add sub and or slt instructions use bits 15 11 0 We do not know which set of bits to use until the end of the second clock cycle 0 Therefore the control Wire cannot be turned on or off until the third clock cycle 0 The multiplexor has to be in the third clock cycle portion of the CPU Read register 1 Read Read data 1 Read register 2 Address quot pC Wnte Registers register Read Instruction Read Addr data 3170 Wnte data 2 egg data Instruction memorV Data Write memor data y CSc 252 7 Computer Organization 15 8 7 Pipelinng
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