Class Note for ECE 372 at UA
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Date Created: 02/06/15
Freescale Semiconductor AN2287D Application Note Rev 1 82004 HCS12 External Bus Design By Jim Williams 8I16 Bit Products Division Applications Engineering Introduction This application note presents a design guide for interfacing external devices to HCS12 Family microcontrollers MCUs Due to the high performance of this MCU family interfaces operating at maximum bus speed are difficult to design and may be expensive Experience in highspeed buses transmission lines and analog design along with an indepth knowledge of the system performance requirements is necessary for understanding and creating a successful system While the HCS12 devices carry over the external bus capabilities oftheir HC12 predecessors the increase in speed presents new challenges to system designers With the introduction of today s fast gate array and interface logic designing systems with a multitude of different interfaces is possible This application note explains the signals necessary to implement an expanded device system The companion application note AN2408D presents example design ideas HCS12 Family Overview The HCS12 Family of MCUs covers a broad range of applications the design focus is for singlechip systems with high integration of peripherals to cover all customer needs Sometimes however a single chip solution is impractical To offer greater flexibility to system designers the multiplexed external bus interface has been included It supports users that need functionality not included in the MCU The bus may be used to interface with external devices This product incorporates SuperFlashW technology licensed from SST Freescale Semiconductor Inc 2004 All rights reserved 397 o freescale semiconductor Modes of Operation The MCU is a 16bit device composed of standard onchip peripheral modules connected by an intermodule bus The multiplexed expansion bus interface MEBI interfaces the intermodule bus to the external bus Memory emulation is facilitated with only an external demultiplexing latch In order to interface with multiple other devices additional decoding is required Most pins with like functionality are combined into groups called ports For example the eight pins named PTB7O comprise a port named PORTB which can be software programmed to act as the low byte of the address bus ADDR 70 in expanded modes or as generalpurpose inputoutput IO lines in singlechip modes The onchip resources modules and pin groupings are shown in Figure 1 Modes of Operation The HCS12 Family operates in one ofeight possible modes These modes fit into three basic types Emulation Special Normal Emulation Modes The emulation modes include Emulation expanded wide Emulation expanded narrow The emulation modes are provided for the development of systems that emulate some of the internal operations of the MCU externally In emulation modes the external bus is configured out of resetwith the bus control signals enabled clock stretch and a chip select m providing immediate fast access for the MCU Port E initialization eg PTE4 is the ECLK output out of reset and the write ability ofthis register is significantly changed In these modes several registers eg PTA DDRA reduced drive for A B are not in the memory map so that an external port replacement unit can replace them because the actual ports are lost to the expanded bus interface Actually the emulation modes are NOT special modes in the sense that additional access rights are available Their purpose is to emulate the single chip expanded wide and expanded narrow operating modes Emulation modes are intended for use in development systems or emulation systems to match the performance capabilities of the singlechip MCU HCS12 External Bus Design Rev 1 2 Freescale Semiconductor Modes of Operation V H VRH V 4 256K BYTE FLASH EEPROM Mm RI 4 ATD1 RL 4 VRL 12K BYTE RAM V332 VD VD SSA lt VSSA AN0 4 PADOO AN0 lt PADos 4 BYTE EEPROM ANI lt PADOI ANI lt PAD09 V AN2 lt PADOZ AN2 PAD010 DDP AN3 0 lt PAD03 AN3 lt PAD011 SSR AN4 2 lt PAD04 AN4 4 lt PAD012 VREGEN VOLTAGE REGULATOR ANs lt PAD05 ANs lt PAD013 VDmz AN6 4 PADoe ANe PAD014 VSSVZ ANT 4 PADOT Am lt PAD015 SINGLEVWIRE PKo rxAWuf BKGDQ BACKGROUND PK1 XADDR15 DEBUG MODULE CPUI 2 M I XADDR16 I XFC4 b PK3 XADDR17 VDDPLL b CLOCK PK4 XADDR18 VSSPV gt PLL AND RESET PEggDVEA g 2PT PK5 mom EXTAL gt GENERATION PK7 Ecs CLOCK MONITOR L J XTAL4 MODULE RESET BREAKPOINTS m PE0 gt m0 PT2 PEI gt IRQ SYSTEM ENHANCED PT3 PE2lt gt A RIW INTEGRATION CAPTURE TIMER p14 PE34 p 4 LSTRB MODULE PT5 E o 4 ECLK PT6 pE44 p EL Q pg 4 4 MODA PT pa 4 4 MODE P90 4 NOACCMCLKS MISO PINM0 KWPO ltgt PP0 MOSI PINMI KWPI ltgt PPi TEST b 3g gt PWMZ KWPZ 7 4 PPZ I II I SPli SSlt2PWM34LLKWP3 0PP3 y y MISO 4 E PWM4 4 E KWP4 g E 4 PP4 MOSI A PWMs A KWP5 4 PP5 MULTIPLEXEDADDRESSIDATA BUS 5 A PVVMG A KWP6 we I SPI2 SS 4 PWM7 A KWP7 PP7 i i i i i PSO DDRA DDRB PSI PTA PTB P52 PS3 I I I IIII P55 22222222 massage P55 oooooooo oooooooo ps7 EMEEREE 99999999 99999999 BDLCUWW PMO 00000000 00000000 44444444 44444444 PV1 r um Now 39I CANO MULTIPLEXED 22222244 222222223 PW I Beeeeeee CCCCCCCCI CAM FW39DEBUS 33333333 33333333J PMS j I PM4 IMULTIPLEXED g g g g g g S gl CANz PMS NARROWBUS 33333333 PM CAN3 PM IIO DRIVER 5 V m INTERNAL LOGIC 25V xnnx gt P J1 VDD iIZ lt 55X VSS iIZ L i PJ6 AID CONVERTER 5 V AND PH VOLTAGE REGULATOR REFERENCE VDDA gt V PLLZ39SV VSSA L KWHO r 4 PHO VDDPLL KWH 4 PH SSPLL T KWHZ 4 PHZ VOLTAGE REGULATOR5VANDIIO P39N 39NTERRUPT KWH3 lt E E 0 PH3 V LOGIC KWH4 g o PH4 KWH5 PH5 KWH6 ltgt PH6 KWH7 7 4 PH Note Thls blockdlagram Is for the 1121quot Version Pms m be are not available In the 801quot Versoquot Figure 1 9812DP256 112Pin Block Diagram HCS12 External Bus Design Rev 1 Freescale Semiconductor 3 Modes of Operation Special Modes The special modes include Special peripheral Special test Special singlechip Special peripheral and special test modes are used for factory testing Operation in these modes is not recommended and therefore will not be elaborated further Special singlechip mode is predominantly for development support and is the main operating mode for all development environments Special singlechip mode is used to bring the MCU under control of a BDM debugger Special singlechip mode differs from the normal singlechip mode in that some registers are granted extra write privileges and the BDM ROM is brought online so that debugging can commence from reset Normal Modes The normal modes include Normal singlechip Normal expanded wide Normal expanded narrow Each normal mode has a default bus configuration and privilege level as discussed here In all these cases any port not used for address data and bus control can be used for generalpurpose inputoutput GPIO HCS12 Family devices must be configured in one of the two normal expanded modes for communication with external memories since these are the only modes where an external address data and control bus exists Normal Single Chip Mode This mode has no external address or data buses The MCU operates as a standalone device having all program and data resources on chip The preferred method is devices are configured to start in normal singlechip mode out of reset if no debugger is attached and software will configure the expanded mode desired Most debuggers will pull MODC low causing entrance in to special signalchip mode Normal Expanded Wide Modes These modes have an external 16bit address data and bus control interface which is made up of ports A B E and K In normal expanded mode the device starts up with clock stretching enabled so that the system may be tailored to the systems requirements The BDM ROM is NOTbrought online so debugging becomes an issue See Mode Selection and Development Environment Consideration for details H0812 External Bus Design Rev 1 4 Freescale Semiconductor Normal Expanded Narrow Modes Memory Map These modes have an external 16bit address 8bit data and bus control interface which is made up of ports A B E and K In this case the external data bus does two consecutive 8bit accesses to handle 16bit data Other than the data bus size narrow and wide modes have the same functionality The BDM ROM is NOT brought online so debugging becomes an issue Memory Map Each ofthe modes described in Modes of Operation also have a default memory map A memory map is a pictorial representation of the total MCU system space and is a convenient way to keep track of the many memory locations Figure 2 illustrates the 9812DP256 memory maps for singlechip and expanded modes of operation immediately after reset 0000 0400 1000 4000 8000 C000 FF00 FFFF 7FFF 8000 EXTERN BFFF C000 FFFF FF00 urn VEQORS VEcmRs EXPANDEDm NORMAL SPECML aNcLEcmP SWGLECHW REGISTERS MAPPABLE TO ANY 2K BYTES WITHIN THE FIRST 32K BYTES 4K BYTES EEPROM MAPPABLE TO ANY 4K BYTES 12K BYTES RAM MAPPABLE TO ANY 16K BYTES AND ALIGNABLE TO TOP OR BOTTOM 16K BYTES FIXED FLASH PPAGE 3E 62 THIS IS DEPENDENT ON THE STATE OF THE ROMHM BIT 16K BYTES PPAGE WINDOW 16 x16K BYTES FLASH EEP PAGES 16K BYTES FIXED FLASH PPAGE 3F 63 BDM IF ACTIVE 1 Assuming that a 0 was driven 0n10 p0r1 K bi17 during reset See ROMON description Figure 2 9812DP256 Memory Map HCS12 External Bus Design Rev 1 Freescale Semiconductor Physical Memory Interface Physical Memory Interface One of the first and most important system design issues to be investigated should be the interface logic levels Be aware that many data sheets give the appearance that devices are faster than they really are It is a common practice to specify speed values at reduced O levels in order to present the best possible numbers in the specification Care must be taken to understand exactly how the devices to be interfaced operate In highspeed designs dealing with nanoseconds and possible subnanoseconds it is imperative to understand exactly how all devices in a system operate Careful study of the part specifications may show that devices specified as 5volt CMOS are not tested at 5volt CMOS logic levels for production timing testing As an example a SRAM memory manufacturer specifies their device output high voltage level VOH to be 24 volt minimum This is well below the 38volt input high voltage of the 5volt HSC12 MCUs To complicate matters careful review ofthe AC timing specification shows that the tAVQV access time is measured at 1 5volt levels Therefore in orderto interface to the 5volt HCS12 devices a data bus buffer is required to match the 24volt output of the SRAM to the 38volt input high VIH requirement ofthe MCU In addition the access time ofthe RAM should be derated or verified by test to account for 25volt VOH levels in lieu of the 15volt levels at which testing is done Careful characterization of the SRAM device may reveal that by derating the memory and adding additional time to the SRAM s tAVQV specification the SRAM may achieve 38volt levels In this case data buffers may not be necessary This decision is left to the system designer Currently all HCS12 Family devices operate at 5volt CMOS logic levels 38volt VIH However due to the increased signal noise immunity that 5volt CMOS levels offer over lower voltage interface levels the designer must decide whether the 5volt noise tolerances are a system requirement Most highspeed devices are trending toward lower CMOS interface levels Future HCS12 Family devices will follow this trend The 21volt VIH levels ofthese 33volt MCUs will eliminate the need for a data bus buffer for level matching NOTE I t is left to the system designer to determine whether logic level matching is required in the application system The following subsections provide a description of each pin needed for a functional system that is interfaced to external memories These are only a few recommendations in an area that has a multitude of solutions In general a designer should consider all possible functions of each pin when designing an HCS12 Family MCU into an application system Power VDD and V55 Power is supplied to the HCS12 devices by using 5volt powerground pin pairs The VDDRVSSR pair is used to provide power to the internal voltage regulator circuitry The VDDXVSSX pair is used to provide power to the external O drivers including the external bus interface The VDDANSSA pair is a separate power source for the analog systems of the device analogto digital converter ADC digitaltoanalog converter DAC and voltage regulator Vreg H0812 External Bus Design Rev 1 6 Freescale Semiconductor Physical Memory Interface On all current HCS12 devices all these power pins operate from a single 5volt power supply with bypass filter capacitors to the supplies Future devices may operate at lower supply voltages and the discussion below should be adjusted accordingly The internal voltage regulator generates a 25volt power supply for the core and module operation Bypass pins are available on the VDD1Vss1 and VDDZNSSZ pairs Also the phaselocked loop PLL has additional bypass pins available on the VDDPLLVSSPLL pair These pins are provided to bypass the internal supplies On some HCS12 Family members the 25volt power can be supplied to the device externally and on these derivatives these VDD and V55 pins will be connected to the external supply In all other cases these pins will not be connected to each other Bypass filter capacitors are required for each pin pair No power can be supplied from the device to external circuitry Very fast signal transitions are present on many of the pins These short rise and fall times are present even when the MCU is operating at slow clock rates Depending on the load on these fast signals significant short duration current demands can be placed on the MCU power supply NOTE Special care must be taken to provide good power supply bypassing at the MCU Use bypass capacitors with highfrequenc y characteristics and place them as close to the MCU as possible For all capacitors it is essential to use a type with low equivalent series resistance E SR Wide body surface mount technology SM T devices tend to have lower E SR l t is often useful to add two capacitors in parallel to achieve good highfrequenc y response while still having acceptable bulk capacitance All recommendations are load and printed circuit board routing dependent Power Supply Decoupling Power supply decoupling is discussed here for each of the powerground pin pairs The overall system affects the final design of the power system VDDXNSSX This is highly dependent on the type of load and switching frequency since VDDX supplies the 5volt drivers in ports J K T P M and 8 Start with 47 nF 220 nF and add 10 uF if large loads are switched or the supply track is long highly inductive A fastswitching peripherals pulsewidth modulator PWM timer controller area network CAN etc are located on this bus VDDAN SSA Good noise decoupling is key here The internal load is almost static 22 nF 100 nF is suggested VDD1NSS1 and VowV552 These are the outputs of the internal voltage regulator 47 nF 220 nF is suggested VDDRNSSR These pins supply the internal regulator as well as the HO ports A B E and H High peak currents may be present through ports A B and E external bus 100 nF 10 uF is suggested H0812 External Bus Design Rev 1 Freescale Semiconductor 7 Physical Memory Interface VDDPLLVSSPLL The most important point here is decoupling of the highfrequency noise generated by the oscillator and PLL switching 22 nF 100 nF is suggested VRH I VRL This is the analogtodigital converter reference so it must be a clean supply High frequency of 1 O nF is suggested NOTE All capacitors should be physically and electrically as close as possible to the pin pairs The capacitors should also have good highfrequency characteristics These are only general recommendations for simple systems such as the examples provided in this application note Start Up RESET RESET is an active low control signal used to initialize the MCU to a known startup state Lowvoltage inhibit LVI and debouncing circuitry may be required on this input This input requires a 41 kg pullup resistor to VDD NOTE Internal LVI is not available on all members of the HCS 12 Family RESET must be guaranteed to be clean from noise monotonic and activated during low power conditions Clocking XTAL EXTAL ECLK and XCLKS Upon reset all the MCU clocks are derived from the EXTAL input frequency The frequency applied to this pin is two times higher than the desired bus frequency ECLK with PLL disabled An external oscillator or crystal may be implemented with crystal inputs Extreme care must be used in this area of the printed wiring board to avoid excess stray capacitance Power and ground planes should be removed from underthe crystal components and short direct connections should be made to the XTALEXTAL pin pair Vias should be avoided The XCLKS pin may be pulled high or low depending on the device to enable the input of an external clock source or select the type of internal oscillator The active level of the XCLKS pin is defined on a device level and should be verified as it varies from device to device Refer to the data sheet NOTE External clock sources must be limited to the 2 5volt VDDPLL supply voltage The ECLK is the bus frequency clock output which is used as a basic timing reference signal The output of the ECLK signal is affected by The ESTR bit in the EBICTL register enabledisable clock stretching The IVIS bit in the MODE register clock on internal accesses The NECLK bit in the PEAR register turn offon ECLK output of PE4 The EXSTRX bits in the MISC register adjust amount of stretching H0812 External Bus Design Rev 1 8 Freescale Semiconductor Physical Memory Interface For additional information refer to the application note entitled Transmission Line Effectin PCB Applications Freescale Semiconductor document order number AN1051D Bus Control Signals RIW and LSTRB In any exp ided mode system the RW and LSTRB signals found at PORTE may be used f bus control RW is used for external writes and indicates the direction of data on the data bus RW typically connects to the external memory s write enable pin and to the data bus buffer direction pin NOTE It is important to note that W will not return to the deasserted state between successive write cycles Lowbyte strobe LSTRB is also used during external writes and indicates ifthe size of the data access is 8 or 16 bits When used with wordwide SRAMs LSTRB connects to the SRAM pin that controls the lowbyte writes typically a pin named something like E When there are two external bytewide SRAMs glue logic is required for byte writes This logic includes LSTRB ADDRO and the chip selects LSTRB is not needed at all when a single external bytewide memory is used It is also not necessary to connect the LSTRB signal to external readonly memory because external reads can occur in wordwide lengths If all 16 data bits are driven when the MCU only needs 8 bits of data the unnecessary 8 bits of data are ignored by the MCU This is why LSTRB is not used in any ofthe schematic examples where the MCU is connected to FLASH memory The RW signal output is affected by the RDWE bit in the PEAR register while the output of the LSTRB signal is affected by the LSTRE bit in the PEAR register In addition to the ADDRO signal RW and LSTRB are used to determine the type of bus access that is taking place Table 1 details all possible access types Table 1 LSTRB ADDR0 and RIW Decode LSTRB ADDR0 RIW Type of Access Mnemonic 1 0 1 8bit read of an even address R8H 0 1 1 8bit read of an odd address R8L 1 0 0 8bit write of an even address W8H 0 1 0 8bit write of an odd address W8L 0 0 1 16bit read of an even address R16 16bit read of an odd address 1 1 1 lowhigh data swapped RLH 0 0 0 16bit write to an even address W16 16bit write to an odd address 1 1 0 lowhigh data swapped WLH Emulation ChipSelect Signal ECS When the EMK bit in the MODE register is set PORTK bit 7 is available as an activelow emulation chip select signal ECS ECS is useful for systems that require an external chipselect signal for memory H0812 External Bus Design Rev 1 Freescale Semiconductor 9 Physical Memory Interface emulation This signal is intended for systems where internal FLASH memory is emulated with external RAM and it cannot be used as a generalpurpose chip select While this pin is used as a chip select the external pin will return to its deasserted state VDD for approximately 14 cycle just after the negative edge of ECLK unless the external access is stretched and ECLK is freerunning ESTR bit in EBICTL is equal to O ECS is only available in expanded mode and only active when internal FLASH memory would have been selected by the bus access if emulation were not enabled When the EMK bit is clear this pin can be used for generalpurpose O Forfurther information referto the module mapping control MMC specification External ChipSelect Signal XCS When the EMK bit in the MODE register is set PORTK bit 6 is available as an activelow external chip select signal XCS This signal is active only when the ECS signal described in Emulation ChipSelect Signal ECS is not active and when the system is addressing the external address space Accesses to unimplemented locations within the register space orto locations that are removed from the map ie ports A and B in expanded modes will not cause this signal to become active While this pin is used as a chip select the external pin will return to its deasserted state VDD for approximately 14 cycle just after the negative edge of ECLK unless the external access is stretched and ECLK is freerunning ESTR bit in EBICTL is equal to 0 When the EMK bit is clear this pin is used for generalpurpose O NOTE This signal is not available on all HCS 12 Family derivatives For further information refer to the module mapping control MMC speci cation and to the Device User Guide Mode Selection Signals MODA MODB MODC The operating mode is determined during reset by the states of the PE5 MODA PE6 MODB and BKGD MODC pins as shown in Table 2 Each of these pins should be connected to VDD or VSS through a 47kQ pullup or pulldown resistor Table 2 Modes of Operation Input BKGD Input Input and and and Mode Description Bit MODC Bit MODB Bit MODA Special single chip BDM allowed and active BDM is allowed in all 0 0 0 other modes but serial commands are required to enable BDM and make it active 0 0 1 Emulation expanded narrow BDM allowed 0 1 0 Special test expanded wide BDM allowed 0 1 1 Emulation expanded wide BDM allowed 1 0 0 Normal single chip BDM allowed 1 0 1 Normal expanded narrow BDM allowed 1 1 0 Peripheral BDM allowed but bus operations would cause bus conflicts must not be used primarily used for Freescale testing 1 1 1 Normal expanded wide BDM allowed HCSIZ External Bus Design Rev 1 10 Freescale Semiconductor Physical Memory Interface NOTE These pins should not be directly connected to VDDVss This is because after reset in expanded modes they may be driven from the M CU In this case if the resistor was not in place powertoground shorts may occur For development support it is especially important to use pullup devices on the BKGD MODC pin as it is used for debugging This may also be important fortestability of the final assembly Mode Selection and Development Environment Consideration When choosing the operating mode the system designer should also take into account the development environment ofthe system lfthe system is to be used in an emulator or emulation environment booting directly into external memory this is easily accomplished by moding the device into emulation or normal expanded modes If the system is to be developed using the background debug functions of the device additional points must be considered The difficulty of using BDM in expanded systems usually occurs immediately after reset Unlike the special singlechip mode the processor doesn t enter a halted state but instead starts executing instructions This can be troublesome because before BDM tools can command the processorto halt the processor registers may have been altered by fixed or random code that may be executing Even if something is programmed into memory the device will be running for some amount of time after reset This is a drawback to BDM in the expanded mode ofoperation The reason special singlechip mode starts in a halted state is to allow devices with blank FLASH to always be bootable The advisable solution is to combine modes to account for both the development and service environments Additional jumpers may be added to the mode control lines or some form of multiplexing used to allow the part to boot in special singlechip mode for developmentwhile using normal expanded mode for service This is accomplished by pulling MODA and MODB low with 47kQ resistors and pulling up MODC with a 47kQ resistor allowing the BDM tool to pull MODC low for development lfthe expanded system is to be developed using the background debug functions it is suggested that the system designer Configure the system for normal singlechip mode and allow the debugger to boot into special signalchip mode during development Write the MODE register to select the expanded mode desired CAUTION Other registers may not be set up properly for the expanded mode and may require additional startup code to initialize correctly Also the write protection of some registers will be different between modes Finally be aware that if the internal FLASH is to be disabled via the ROMON bit in the MISC register it is not advisable to do so while executing from the internal FLA SH memory The program execution will most likely crash If device code changes are undesirable between environments be aware that most debugging tools provide the ability to self configure the device in the debugging environment if the part is booted into special signalchip mode If the MCU is to be configured for expanded operation in secure mode the MCU must exit reset in the expanded mode No writes to the MOD bits are allowed while operating in a secure mode However to release security special singlechip mode must be possible H0812 External Bus Design Rev 1 Freescale Semiconductor 11 Physical Memory Interface Internal FLASH Enable ROMON In addition to the selection ofthe bus modes determined earlier the ROMON pin can be used in expanded modes to enable and disable the internal FLASH or ROM memory in the memory map of the device This function can be used to Totally disable internal FLASH or ROM memory when external emulation memory is used or Enable the internal FLASH or ROM memory so that the device can be booted from the internal memory while still having external memory available after reset The active level and function of the ROMON signal may vary from emulation to normal mode operation Please consult the specific device data sheet for complete functionality and active levels MCU Free Cycle Detection No Access NOACC The NOACC signal is provided to signal external devices that the current external bus operation is invalid This is important because the MCU internal operation cycles might otherwise be interpreted by external devices as a valid read cycle and cause possible bus contention issues This is not an issue if External devices are read only FLASH The internal visibility function IVIS is not used The external chip selects are used The NOACC signal is also used during debugging so that external tools can be signaled to ignore cycles which are not meaningful MCU accesses The NOACC bit in the PEAR register affects the output of the NOACC signal When in expanded modes all program fetch addresses are signaled on the external address bus whether internal or external The MS bit ofthe MODE register only controls whether the data is driven onto the bus If the MS bit is set during internal MCU cycles free cycles the date driven onto the bus may hold from one cycle to the next Hence data from one bus transaction may be interpreted as the address of the next For example ifthe BSET opr8a msk8 instruction which uses an er0 bus cycle access sequence is executed with the MS bit set and the P cycle was a program fetch to an even address then the O cycle will be executed as an MCU free cycle The MCU does not drive the bus during this internal cycle and data from the write cycle will be held from the w cycle to the O cycle This may cause external logic to interpret this hold over data as a valid address on the O MCU cycle The NOACC single will be active in this instance Multiplexed Address Bus PORTA and PORTB Connecting the MCU ADDR15O to an external memory depends on the MCU mode of operation and the type of external memory configuration bytewide or wordwide used The two eight bit ports A and B provide a 16bit multiplexed external address bus ADDR15O H0812 External Bus Design Rev 1 12 Freescale Semiconductor Conceptual Memory Interface In expanded wide modes The MCU s ADDR151 should connect to the memory s ADDR14O lines In expanded narrow modes The MCU s ADDR15O should connect to the memory s ADDR15O lines Multiplexed Data Bus PORTA and PORTB Internally HCS12 Family devices have full 16bit data paths But depending upon the operating mode the external data bus may be 8 or 16 bits In external wide modes the 16bit data bus is made up of ports A and B Bidirectional PORTB70 shares functionality with the low byte ofthe data bus DATA7O and low byte of the address bus Bidirectional PORTA70 shares functionality with the high byte of the data bus DATA158 and high byte of the address bus In external narrow modes the 8bit data bus is made up of port A only Bidirectional PORTA70 shares functionality with the low byte ofthe data bus DATA70 and high byte of the address bus Data accesses are split into two consecutive 8bit accesses so only portA is used as the data bus In this case the external data bus does two consecutive 8bit accesses to handle 16bit data requests from the MCU NOTE Backtoback writes will not negate the RW signal Conceptual Memory Interface MCU in Narrow Mode Connected to One External ByteWide Memory HCS12 Family devices permits the access of individual bytes of memory Memory can conceptually be thought of as a column or linear list of 64K bytes of space from 0000 through FFFF An external memory in a bytewide configuration such as a 64K x 8 SRAM can also be thought of as a column In this case it is also a column of 64K bytes of memory With the MCU in an expanded narrow mode the connections between the MCU address bus and the external memory address bus are straightforward Each ofthe MCU address lines connects to its corresponding memory address pin For example MCU ADDRO connects with the memory address 0 pin MCU ADDR1 connects with the memory address 1 pin MCU ADDR15 connects with the memory address 15 pin Figure 3 is an example of this type of connection HCSIZ External Bus Design Rev 1 Freescale Semiconductor 13 Conceptual Memory Interface 0000 BYTE 0000 0001 BYTE 0001 0002 BYTE 0002 0003 BYTE 0003 0004 BYTE A0 A0 0004 0005 BYTE A1 A1 0005 0006 BYTE A2 A2 0006 0007 BYTE 0007 A15 A15 EEEc BYTE EEEc EEED BYTE EEED EEEE BYTE FFFE EEEE BYTE EEEE MCU IN NARROW MODE 64KXSSRAM Figure 3 Address Connection for MCU in Narrow Mode to One ByteWide Memory MCU in Wide Mode Connected to One External WordWide Memory When the MCU is in wide mode and the external memory is in wordwide configuration the connections are different An external memory such as a 32Kx 16 SRAM can be thought of as two 8bit columns from 0000 through FFFF 32K addressable words where the left column is considered the high byte and the right column is the low byte The MCU being byte addressable continues to be thought of as a single 8bit column that is 64K bytes long The 32K words of the SRAM are equivalent in quantity to the 64K bytes the MCU can access In this situation each of the MCU address lines connects to a memory address pin offset by one For example MCU ADDR1 connects with the memory address 0 pin MCU ADDR2 connects with the memory address 1 pin Continuing on to MCU ADDR15 which connects to the memory address 14 pin The external memory requires only 15 pins ADDR151 to access all 32K words MCU ADDRO is used to selectthe even or high side of the external memory word and the MCU LSTRB signal is used to select the odd or low side of the external memory word This connection is shown in Figure 4 HC812 External Bus Design Rev 1 14 Freescale Semiconductor Paging Memory Interface HIGHEVEN LOWODD BYTE W BYTE E 0000 BYTE 0000 0001 0001 BYTE 0002 0003 0002 BYTE 0004 0005 0003 BYTE A1 A0 0006 0007 0004 BYTE A2 A1 0005 BYTE A3 A2 0000 BYTE 0007 BYTE A15 A14 A0 W EEEC BYTE LSTRB E EEED BYTE EEEE BYTE EEEc EEED EEEE BYTE EEEE EEEE MCUINWIDE MODE 32KX16RAM Figure 4 Address Connection for MCU in Wide Mode to One WordWide Memory NOTE This is only necessary to signal byte access from word accesses for write operations In read operations the M CU will automatically determine which of the bytes is required Paging Memory Interface The multiplexed external bus interface block of circuitry MEBI module supports memory expansion via the six memory expansion lines This section discusses expanding memory beyond the 64K direct addressing limit Paging Paging in a simple sense can be implemented by using port pins as additional address lines This simple method allows the system to periodically select new memory by modifying the output value of a given port However this simplicity induces several issues into the system design The most noticeable issue is how to run from one bank while switching to another This can be overcome by allocating a section of common memory that can be used while the bank flip takes place For example code could execute from internal RAM during this banktransition The HCS12 Family has been designed to overcome this potential problem HCS12 Family design defines a paging window at 8000 BFFF This window has an associated page select register that selects external memory pages to be accessed via the window For example on the 9812DP256 the PPAGE register determines which of 64 possible 16K byte pages is active in the program window Only one page at a time can occupy the window and the value in the associated register must be changed to access a different page of memory Each page is the same size as the windowThe memory expansion function overrides two ofthe standard 16 address lines When an internal address falls into one ofthe overlay windows it is translated for the correct address See Figure 5 HCS12 External Bus Design Rev 1 Freescale Semiconductor 15 Paging Memory Interface If the EMK bit in the MODE register is set PPAGE values will be output on XADDR19 XADDR14 respectively PORTK bits 50 when The system is addressing within the physical program page window address space 8000 BFFF The system is in an expanded mode When addressing anywhere else within the physical address space outside of the paging window the XADDR19 XADDR14 signals will be assigned a constant value based upon the physical address space selected For additional information refer to the HC12 and HCS12 CPU Reference Manual Freescale Semiconductor document order number CPU12RMAD In addition the activelow emulation chipselect signal ECS will likewise function based upon the assigned memory allocation In the cases of 48K byte and 64K byte allocated physical FLASHROM space the operation of the ECS signal will depend additionally upon the state of the ROMHM bit in the MISC register Again this signal is only available externally when the EMK bit is set and the system is in an expanded mode 0000 PAGED FLASH UNPAGED FLASH IIO REGISTERS PPAGE 4000 I EEPROM VALUE El RAM 3E BLOCKS BLOCKZ BLOCKI BLOCKO l39 T T 00 2F 30 31 32 33 34 35 30 37 38 39 3A 33 30 30 3E 3F L J L Paged memory between 3F 8000 and BFFF is selected 5 within the H0812 physical memory map by the value in the PPAGE register FFFF Figure 5 9812DP256 Paging Example Paging is accomplished by using the lower address lines from the MCU and appending the PPAGE bank select lines XADDR19 XADDR13 This creates a linear address as shown H0812 External Bus Design Rev 1 16 Freescale Semiconductor Assessing External Memories Compatibility Bank Window A15 AO Bank A13 A0 0 8000 BFFF 0000 3FFF 00000 03FFF 8000 BFFF 4000 7FFF 04000 07FFF 8000 BFFF 8000 BFFF 08000 OBFFF 8000 BFFF COOO FFFF OCOOO OFFFF 8000 BFFF 0000 3FFF 10000 13FFF LWMA 3B 8000 B FFF COOO FFFF ECOOO E FF FF 3C 8000 B FFF 0000 3FFF F0000 F3FFF 3D 8000 B FFF 4000 7FFF F4000 F7 FFF 3E 8000 BFFF 8000 BFFF F8000 FBFFF 3F 8000 BFFF COOO FFFF FCOOO FFFFF Address lines A13AO select 16K pages By dropping the unused address lines A14 and A15 they will not change in the banked window and appending the PPAGE address XDADDR19XADDR14 linear addresses mapping to the external device can be formed In other words don t use or connect A14 or A15 to external banked memory To reverse back from linear addresses divide the linear address by 4000 ie ECOOO 4000 38 Hence ECOOO is physically bank 3B Assessing External Memories Compatibility This section examines the relationship among the signals of the HCS12 Family device involved in communicating with external memories These signals allow read and write transactions between an MCU and its external environment Understanding these is useful for finding compatible memories Both protocol flowcharts and timing diagrams are used to explain the read and write cycles of devices in the HCS12 Family Read Cycle The protocol flowchart shown in Figure 6 shows the sequence of events that occurs when an HCS12 Family MCU performs a read from an external memory The items on the lefthand side are the events carried out by the MCU and those on the right are the actions taken by thegternal memory The read sequence begins when the HCS12 device sets up an address driving the RW signal high and the LSTRB signal low if the address is odd When these signals are valid The MCU drives the appropriate ECS or XCS signals low to indicate to the external memory that all the values currently presented to the external memory are valid The external memory detects the ECS or XCS signal and starts to access the data The external memory then takes control ofthe data bus by placing the requested data on the bus HC812 External Bus Design Rev 1 Freescale Semiconductor 17 Assessing External Memories Compatibility A There is no acknowledgement from the external memory to the MCU indicating that valid data is available Instead at a specific time with respect to the time that the address became valid the MCU terminates the cycle by latching the data forcing LSTRB high if it was asserted and forcing m or m high A The external memory again detects the state of ECS or XCS and terminates its activity by removing data from the data bus and releasing it to a highimpedance hiZ state so that there is no bus contention with the MCU I ADDRESS THE MEMORY I SET Riv v TO READ PLACE ADDRESS 0N BUS ASSERT RB IF RESS IS ODD ASSERT ECS AND XCS IF IN RANGE I I I I OUTPUT THE DATA A DECODE THE ADDRESS A PLACE DATA ON BUS ACQUIRE THE DATA A NEGATE RB IE ASSERTED A NEGATE ECS AND XCS IE ASSERTED TERMINATE THE CYCLE I A REMOVE DATA FROM THE DATA BUS I AND RELEASE TO leZ LATCH THE DATA I START THE NEXT CYCLE I L i Figure 6 Protocol Flowchart for an HCS12 Family MCU Read Cycle It is up to the systems designer to confirm that the external memory can place valid data on the data bus between the time when the MCU places a valid address on the address bus and when the MCU latches the data from the data bus Write Cycle The protocol flowchart shown in Figure 7 for a HCS12 device write cycle is very similar to the read cycle Here though instead of the external memory providing data the MCU provides the data At the start of the cycle RW is forced low an address is placed on the address bus and LSTRB is forced low ifthe address is odd or if a word is being transmitted HC812 External Bus Design Rev 1 18 Freescale Semiconductor Assessing External Memories Compatibility When these three signals are valid The MCU drives the appropriate ECS or XCS signal low to indicate to the external memory that all the values currently presented are valid and that the MCU is about to send it some data The external memory detects the ECS or XCS signal and makes preparations to receive the data The MCU then takes control of the data bus by placing the data to be written to memory on the bus at a specific time during the write cycle There is no acknowledgement from the external memory to the MCU indicating that the write transaction was successfully completed The MCU terminates the cycle forcing ECS and XCS high and removing data from the data bus and driving it to a hiZ state The external memory again detects the state ofthe ECS or XCS signal and terminates its activity EXTERNAL MEMORY I ADDRESS THE MEMORY SET RNTI TO WRITE PLACE ADDRESS ON BUS ASSERT LSTRB IF ADDRESS S ODD ASSERTmAND m IF IN RANGE PLACE DATA ON DATABUS I I INPUT THE DATA DECODE THE ADDRESS STORE DATA FROM DATA BUS l I TERMINATE WRITE DATA I I NEGATE W I I I NEGATE mAND W REMOVE DATA FROM DATA BUS I TERMINATE THE CYCLE I RELEASE DATA TO leZ I I START THE NEXT CYCLE Figure 7 Protocol Flowchart for an HCS12 Family MCU Write Cycle It is up to the system designer to confirm that the external memory can latch valid data from the data bus between the time when the MCU drives ECS or XCS low and the time when the MCU presents data on the data bus H0812 External Bus Design Rev 1 Freescale Semiconductor 19 Assessing External Memories Compatibility NOTE The MCU may not negate the RW signal Backtoback write cycles will cause RW to stay low for both cycles Timing Diagram There are certain timing values not shown in Figure 6 and Figure 7 that the system designer must know in order to find compatible memories to work with the HCS12 Family The timing diagram shown in Figure 8 shows more precise timing relationships between the signals involved so that read and write calculations can be made to select appropriate external memories It shows the bus timing for the 9812DP256 in wide and narrow modes For actual values refer to the appropriate device data sheet H0812 External Bus Design Rev 1 20 Freescale Semiconductor Assessing External Memories Compatibility lt 5 7 15 lt 10 r 9 H lt 6 gtllt 16 gt gtl 1 11 ADDRESSDATA 39 I I I READ DATA I 9 ADDRESS I DATA PA PE I 1 7 gt1 I s lt gt 13 I 12 I s 14 7 ADDRESSDATA I WRITE DATA X ADDRESS X DATA X PA PE I lt 17 gtlt 18 gtl 19 l NONVMULTIPLEXED I I ADDRESSES I X I PK50 I 22 1 m PK7 RIW PEZ I lt m 39 PE3 394 I NOACC PE7 lt 33 gtlt 34 gtllt 35 gtlt 36 gtl IPIPOO L 5 lPlPOi I X l g PE65 I I Figure 8 General External Bus Timing Example of the 9812DP256 gtlt Before continuing the timing diagram discussion some basics are covered here Timing parameters are shown as tX and are used to show a minimum time for which MCU input data must be stable or a maximum time in which MCU output becomes valid Inputs may be represented by two parallel lines at logical levels 0 and 1 when concern is only with the points at which changes occur and not the actual value of the input The shaded areas between parallel lines indicate that data is invalid Midlevel lines parallel to the O and 1 levels are used to show times when the data is in a highimpedance state also known as hiZ state floating state or threestate H0812 External Bus Design Rev 1 Freescale Semiconductor 21 Assessing External Memories Compatibility The expanded bus timings are highly dependent on the load conditions The timing parameters shown assume a balanced load across all outputs In the systemtiming example Figure 9 each read or write cycle consists of one ECLK cycle The cycle starts in state 80 with ECLK falling edge and ends in state 83 with ECLK falling edge In state 80 A new address is placed on ADDR15O at no more than tAD seconds from the start of ECLK O m changes to a low if the address is odd or if a word is being transmitted The RNV signal changes to a high for reads or changes to a low for writes The timing specifications of the m and RW signals are the same as ADDR15O W m remain high In state 81 ADDR15O LSTRB and RW all remain valid ECS XCS go low indicating to the external memory that If RW is high all the signals currently presented are valid and that the MCU is readyto receive data If RW is low that the MCU is about to send it some data ECS XCS go low no less than tCSD after the address has stabilized ln state 82 The address is removed from the bus If RW O signaling a write cycle the MCU starts to drive data onto the bus If RW 1 signaling a read cycle the bus is left in a hiZ state This is in anticipation ofthe external memory driving data onto the bus NOTE The end of state 82 can be extended by introducing M CU stretch cycles Each stretch cycle will add one MCU E CLK tcyc ns to the 82 state At 25 MHz this would stretch the 82 state from 10 ns to 50 ns adding an additional 40 ns to the access time of external devices Up to three additional stretch cycles may be introduced to increase total access time by up to 120 ns at 25 MHz H0812 External Bus Design Rev 1 22 Freescale Semiconductor 25ns ernal Read Cycle 1 150ns 175ns 75ns l100ns I I al WnIe Cycle ernal WnIe Cycle 2 lnIernal Cycle SYSC LK m 9 EC LK lm 1AD 12 12 IDDW IDDW IDHW AddrlDaIa RAM DaIa Addr MCU DaIa MCU DaIa RNTI RAMiRNV LaIchediAddr 1E LQV IGLQV IAVQV RAM daIa 12 MCU Data 12 MCU DaIa IGHQZ RamiDaIa Figure 9 System Timing Example for ECLK 25 MHz Assessing External Memories Compatibility In state 83 ECSXCS LSTRB and RW continue to remain valid throughout state 83 keeping the lines of communication to the external memory open During a write cycle the MCU continues to drive data to the external memory For a read cycle the external memory must have valid data presented to the MCU at least tDSR ns before the end of 83 NOTE At the end of the nal state 83 all the signals are completing the cycle and are getting prepared for the next cycle RVV remains or changes to a high mXCS change to a high bringing the transaction between the M CU and the external memory to an end The bus and LSTRB signals become invalid General Guidelines This subsection provides general guidelines for read and write cycle calculations Read Cycle Calculations After studying the MCU timing diagram the next step in finding a suitable external memory is to determine whether the MCU and memory combination violate any of the read and write timing parameters The nomenclature for the external device timing conforms to JEDEC standards Please check carefully the corresponding parameters for the external device Use the following list as a guide when checking the principal timing parameters between the MCU and the memory 1 Is the device address access time tAVQV sufficient for a read by the MCU tAVQv lt N tCYC tcvc tAD tDSR Where N is the number of MCU clock stretch cycles For N O the external device must have an address access time of less than tCYC tAD tDSR to function correctly with the MCU at a frequency of 1 Item Additional delays of any required level translation logic must also be accounted for either by adding to the device access time tAVQV or subtracting from the bus cycle time tCYC tAD tDSR Does the read data hold for the time tDHR that is required by the MCU to latch the data For HCS12 Family MCUs the required hold time is 0 ns Are the read data bus drivers turned off and floated before the next MCU access begins To avoid any bus contention the memory data bus drivers must float the bus before the next MCU access tries to drive the next address onto the bus tAD ns All current access activity must cease before this new activity begins Although bus contention is not desirable in any system it does not mean the design will notfunction Bus contention will cause increased power consumption increased heat and a reduction in access timing HC812 External Bus Design Rev 1 24 Freescale Semiconductor Assessing External Memories Compatibility The bus must have reached a stable noncontentious state before the above calculations can be applied This does not mean the system will not function Write Cycle Calculations The next step in determining if an external device is compatible with the MCU is checking the write cycle timing 1 Is the memory setup time sufficient for the MCU to place data on the data bus The MCU must haV valid address presented to the memory at least tWLAX ns before the write enable WE pin or CE pins negate The MCU must maintain a valid address forthe entire write cycle access time tWLAX lt N tCYC tcvc tAD Where N is the number of MCU clock stretch cycles The address is valid tAD ns after ECLK fall the address will be valid for tCYC tAD ns This must be greater than the time the memory requires the address to be ve tVLAX 2 Does the MCU address remain valid for at least tEHAX ns afterthe memory s CE or WE pin go high The MCU must hold a valid address forthe memory at least tEHAX ns after the memory s Eor W pin negates The MCU holds the address at least tAH ns after ECLK fall Since the memory sE pin may be affected by the MCU sm m m and LSTRB pins all three play a factor in determining whetherthe memory s tEHAX parameter is met The MCU also holds the RW pin for a minimum of tRWH ns after ECLK fall 3 Is data from the MCU valid at least tDVEH ns before the rising edge ofthe memory s E orm pin The MCU must have a valid address for the memory at least tDVEH ns before the rising edge ofthe memory sEorm pin negates The MCU guarantees that afterthe data has been held for tDSW ns the m pin won t go high until tCSH ns later the A0 pin won t change until tAH ns later the LSTRB pin won t change until tLSH ns later and finally that the RW pin won t change until tRWH ns later 4 Does data from the MCU remain valid at least tEHDX ns after the rising edge ofthe memory s E or WE pin The MCU must keep data valid at least tEHDX ns after the rising edge of the memory s E or W pin goes high The MCU holds the data at least tDHW ns after ECLK fall Since the memory sm pin may be affected by the MCU s m m A0 and LSTRB pins all three play a factor in determining whether the memory s tEHDX parameter is met The MCU also guarantees to hold the RW pin for a minimum of tRWH ns after ECLK fall If the read access timing of most external devices to the MCU can be met the write access timing is usually guaranteed It is important to study the timing when the external device is selected E W active to see that a valid address is stable and that when the device is deselected data has met the devices tWLAX and tWHDH specifications HC812 External Bus Design Rev 1 Freescale Semiconductor 25 Conclusion Conclusion Freescale Semiconductor s HCS12 external bus enables a designer to create an expanded device system for situations where a singlechip solution is impractical because of cost or availability of peripherals Using the HCS12 external bus to create an expanded device system means the designer is not limited by the functions available on a single MCU This application note described considerations and benefits of setting up a system using the HCS12 external bus t presented the signals required to implement the external bus and discussed the modes of operation in which the external bus is available AN2408D details examples which support the methods described here This document can serve to guide a designer to understanding and creating a successful system that takes advantage of the flexibility of the HCS12 external bus H0812 External Bus Design Rev 1 26 Freescale Semiconductor Conclusion This page is intentionally blank H0812 External Bus Design Rev 1 Freescale Semiconductor 27 How to Reach Us USAEuropeLocations not listed Freescale Semiconductor Literature Distribution PO Box 5405 Denver Colorado 80217 18005216274 or 4807682130 Japan Freescale Semiconductor Japan Ltd SPS Technical Information Center 3201 MinamiAzabu Minatoku Tokyo 1068573 Japan 81334403569 AsiaPaci c Freescale Semiconductor HK Ltd 2 Dai King Street Tai Po Industrial Estate Tai Po NT Hong Kong 85226668334 Learn More For more information about Freescale Semiconductor products please visit httpwvafreescaleLom AN2287D Rev 1 82004 Informa ion in this document is provided solely to enable system and soltware implementers to use Freescale Semiconductor products There are no express or implied copyright licenses granted hereunderto design or fabricate any integrated circuits or integrated circuits based on the information in this document Freescale Semiconductor reserves the right to make changes without further notice to any products herein Freescale Semiconductor makes no warranty representation or guarantee regarding the suitability ofits products for any particular purpose nor does Freescale Semiconductor assume any liability arising out ofthe application or use of any product or circuit and speci cally disclaims any and all liability including with out limitation consequential or incidental damages Typical parameters which may be provided in Freescale Semiconductor data sheets andor speci cations can and do vary in different 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