Class Note for ECE 372 at UA
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Date Created: 02/06/15
68HCS12 UofA System Setup U of A System Schematics Orcad U ofA System DragonFly 5 T i s N PS 0 1T 3 9 XTALIAD 17 lleDCfTAGHIUBlQGD 23 EXTAL39 22 I m 1s BUZZERQ l 21 PAUtHDDRo RXLANJPMU 16 i m7 PE4IADDR4 TXCANJPNH Te 13 MIQPW 38 t Eli PE JIXCLKS 53mm 7 4D MOBIJPMi 37 Eli PPSJPWS screws AD 13 PSDJRXD u XI o FEWTXD w t 12 D IR 33 VRH 5 ESET 51 PTUJF V JUII 0c UF HEHZlDH tl l m1 g 6 PthPWtIIOMPAD mm 7 7 F39TEJPV39JZIIOC2PADI r4112 8 8 3x yanocaPAD ANUB 9 9 F T4F 4t lC39CAF39HEll mum 0 1D maxim5 FAD ANLL e ra 11 PTmoca PAooammns 727D F39TTJIDC39I39 PADWIAND39 19 DANHU D714 PEMECLK mum 720 D Mud 1 Li MODULE U ofA System Power Supply Typical Applications Fixed Output Regulator INPUT OUTPUT Gilli CH 4 M F 2 TT 0077mm Required if the regulator is located far from the power supply filter Although no output capacitor is needed for stability it does help transient response If needed use 01 pF ceramic disc LMTBUSITO Input Power 1 VIN g VOUT o W U2 SW1 4 c1 022uF a 5 Volt Regulator 1A POWER LED U ofA System Led Display Reset Aln Dln DOut gt Output EnableV 5N54174L5244 pm 45 e 26 M 2M 1V2 2A3 W3 2A2 1w 2A1 5V R12 RESET LED ADC 7 PT R3 R18 g J b 5 j X R4 RESISTOR VAR 10k FTZ m FT R5 16 1M 2 WA 2V3 1A3 2Y2 1M 2V1 END 7 470 7w 7W TrIState BUffer what Is each Circuit used for PTA R5 r m E n 7 Open Collector Output D39P DIP mom 15 7 20mA 39 R7 39339 H P am E amp T4 7 7 V 11 3 7 gtPT7 BUZZER m R8 5 2 5 Boats cs a k 470 v5 A5 3 A d r u 1 A l 1 YE A6 5m BUZZER a x l 7 I W l w M l 2 l g lquot g a 33 F 7 if m m 41 8 3 A H U Mm t m w m 39l gt A1 2 NW aw c 7 ca I I i 1 MP what Is this buffer for Lab 1 Introduction H09812032 GOTO Website Setup Goal IS to configure all pins to create a functional circuit The DragonFly module already pre configures your microcontroller l U L L VSSR gt PORT E Expansion VDDR b VDDX gt VSSX gt Voltage Regulator D Iag ra m DD2gt 16K 32K 64K 96K 128K Byte Flash vssz gt 21 1K 2K 4K Byte RAM BKGD0 MODC Background Debug12 Module XFcltgt VDDPLL gt Clock and Power VSSPLL gt PLL Reset EXTAL p Generalloquot COP Watchdog RO M XTALlt M d 395 RESETo Periodic interrupt PEG h XIRQ PE1 gt W De bug PE2ltgt m RW PE3ltgt LU n iLSTRBTAGLO OscHlator DEM E g 5cm PE5ltgt MODAIPIPED Interru pts p55 MODBIPIF39E1 M 0d 6 p570 NOACCXCLKS Timer Module PWM Module RXD TXD SCI MSCAN is not available on the 981260 Family Members Analog 2D Timer Input Timer Output Pulse Width M Serial RS232 Serial CAN Serial SPI Reduced 68HCS1ZC 48 Pin Assignment Serial Port AD DIO Analog n quot0 x 3 ND E1 1 53 g E5 keypad amp a g a a g e Ref H H H H H H H C V 3 tr 8 g 3 R B port T PJ39IDJOCOPTO I I 3 RH PWH IOClI PT I I 2 1 VDDA Input Capture I I YIIZIIOLZ PTZ I 3 I momma OUtpLIt compar P J r39SIIOCGI PTS 4 l PADOGIANDE PWM 25V J39DD39I E 5 j momswas V851 I 6 lVlC aSlzCFamily I PADWANM PW4I39Ioc4IPT4 I 7 quot CE SQGC FWW I RADCGiANUTS OC JPT5 I B mom an IocsIPTe I 9 I I PADDlIANDi Ioc7IPTI E 10 l RADooIANIIn Debug MODcIBKsD I H I PAD PBAE Zm V m a t m m o N m v2 339 XIROIPEU VOVWWWNNNNN POFIB lllllllll L I J e 5 5E 2 4 39 PLL B IRQ CLK Con g V Filter CLK 0 Reset Osc read electrical speci cations for details on voltage levels RXCAN MSCAN TXCAN MlSO hme NFO hwmvm r i EEEEEEEEE EEEEEEEE SPI Mg Ei zimw hmmwm vo SCK MMCCZMEQDC MMCCIXKCCMIZ annnnnng nanonnon DDDDOQQD DDDQDDDD ltltltltltltzltlt ltltltltltltltlt 39A39I39T 1323 2335quot 31 u 39 39 utipexeltltltltltltltlt 4 lt Wide BUS EEEEEEEE g 5 SignalsshownInBoldarenotavailableonthe520r48PInPackage Signals shown in Bold Italicare available in the 52 but not the 48 Pin i It 42 3 sheI Single chip mode Mode of Operation Executing on external memory 48 pin does not have bus expansion routed to physical external pins Debug Mode Mode Selection MODA MODB MODC XCLKS ROMCTL MODAB relevant for external bus not accessible in DragonFly MODC affects debugging ROMCTL allows disabling of internal flash memory BKGD e pa e 1255 e we e ROMON Mom MODE MODA ROMCTL Eit M me escr39lm m SDecIal smge Chip sum allnwed em ACTIVE EDM 1s a a a x 1 asiowea in all other modes bu a serial command 1 Equll ed 10 make EIDM acme a 1 u x a SDecIal Test Expanded Nidel BDM allowed u 1 1 1 emuvamn panuea wee Hum allowed 1 a u x 1 Normal Single cm BDM a 1 o 1 f S Normal Expanded Narrow EDM allowed Peripheral aw alien13921 um bus operations would cause 1 1 u x 1 bus con vc s lmust r1111 he used 1 1 1 1 Normal Emanned wee em allowed Power Power Supply Fast signal transitions on pins demand high instantaneous currents peaks Use two decoupling capacitors 1 uF and 001 uF as close as possible to VCC and Vdd pins for most integrated circuits Heavily loaded expanded mode systems may require more elaborate bypassing Bypassing supply high dynamic Line noise currents 8 limit ground filtering bouncing boald l every IC Line noise is due to parasitic of the interconnections on the power distribution network HC12 Power Supply VDDR 5V and VSSR external supply ground to internal voltage regulator VDD1 25V and V881 OV bypass internal voltage regulator output VDDA 5V and VSSA supply ground for AD VRH 5V and VRL reference voltage for AD ground VDDX 5V and VSSX supply ground for lO pins VDDFLL 25V and VsspLL bypass supply for PLL clock ground capacitor output Internal Voltage Regulator mom R552 Supply 22 D 12 mm AD quiet FOR mm vss 12 V88 4 CTRL LVl VREGEN RESET What would you want to do if any of those resets are triggered Dragon Fly Supply Implementation 1 were Dragon Fly Supply Implementation 2 Power Saving Modes Shutdown Mode Requires POR VDD1 VSS1 not available Stop Reduced Power Mode STOP instruction chip in full static mode requires external reset or interrupts to restart VDD1 VSS1 lower but available Pseudo Stop STOP instruction COP and RTI still running consumes more power than full stop faster restart Wait WAI instruction data and address bus static clocks running faster recovery requires reset or interrupts to restart Run Full Performance Mode Clocks Oscillators why do we need a clock in a microcontroller Clock Operation Run Mode Wait Mode allows to disable clocks Stop Mode Full all clocks disabled Pseudo oscillator runs but system clock stopped COP and RTI still running Self Clock Mode If input clock not sufficient quality External Oscillator XCLKS pin determines oscillator type 1 512CORE Flasli RAM TIM vssPtL ATD PM me a the nature m 2 rammed grim Cclpll39s US law a EXl39AL DC voltage has is apalea In the quta 7 sci Pleasemnsctnzmsz 39vamfncuerfnlnrysalDC SPl a I k E ERG Flgufe 25 colpius Osclllator Connectlons lPE71l oscillator clock SCAN lioi mi 951ch VREG TPM Winnquot llezemi shme i nnen lsth wignmeuusacmsials Reler nls39lufadulel 5 data Figure 27 External Clack connectlons FE7m Figure 26 Plerce Oscillator Connections PE7ol Dragon Fly Clock Implementation F Et 955 ExTAL J r39 393 airm I ll Hm I U Hyp 4 I a J2 vDDii 35 VEDA What will happen r NE 35 iRH ifyoucheckEXTAL wi h oscilloscope while in run mode Alternative PLL Clock Voltage Regulator PLLCLK 2KOSCCLKX Dower on Reset Law vaiiae Resei ijS i i wR 1 i i REF 1 System Rese l f CRG E thEl Rese Cluck mail ZxcLKs Monito a O GSCCLK Clg koaliiy EEXTAL scl an er XML later RTI XFC PLLCLK VDDPLL PLL Clock and Reset Mat Control Ens Clock 7 Core Clock cscillaror Clack Real Time iniemi 3i LL Luck inierrup Se lClnck Mme ii Refer lo Iewce specincmiou ior avariahiiiiy oi the law valmue resei feature inreimpi PLL Clock Registers amp Nquot is39i lriiRi PLLLLK LEOJLLLKXIREFD IJV1quot 164 Address urrser xnu Unininlenisi led m Reserved Figure 32 one Relerence Divider Register REFDV PLL Clock Filter Passive external loop filter second order low pass required Determines stability of PLL See Device Users Guide to calculate component values XFC pulled high if PLL not needed how do you pull high Figure 2V1 PLL Loop Filler Connections DragonFly PLL Clock Filter VUDPLL 1 C5 C6 IUF 4339205 7 C7 ATBFF 19 R3 1K what PLL clock speed was this designed for email me answer and you will get bonus points for first lab T ch 39 MCEmZCszrcs V mucus Ali stepFm Fm gt Rfemhe 5ch 42 w 1 came PLL versus External Oscillator my ms mm l 55 cm mu mar em up It takes 4 080 4 PLL clock cycles to transition between clocks L where is external clock and PLL clock Figure 42 System Clocks Generator Clock Summary Clock provides time base for microcontroller execution speed synchronization Oscillator clock is 8MHz DragonFly and derived from an external oscillator The core clock is either the oscillator clock or derived from a PLL PLL clock provides an alternative clock speed PLL clock is derived from oscillator clock Clock Summary Bus clock is 2 times slower than the core clock A stable clock is essential for proper MC operation Clock monitor circuit detects clock failures Do not measure EXTAL amp XTAL with oscilloscope why We can stop the clock stopwait how do we start it again lt gt 1 core clock cycle Address Data 1 bus clock cycle Reset Reset amp Interrupts A reset is required to restart your microcontroller There are several type of resets Power on is detected CREG External by pressing the reset button Low voltage is detected VREG COP watchdog times out CREG Clock monitor failure detected CREG A reset brings you microcontroller into a prede ned state Reset Clock and Voltage Regulator are connected how Clock amp Reset Generator nweron Reset Voltage Regulator Law Voltae Reset 7 39 RESET 1 m Reset System Reset Clack CM l ll Generator xcus Monim E cvsch a Clock Qualin EXTAL Oscil Checker E E c x XML Iator 5 3 E Rn ColeCluEK Oscillator Clark ch E DDPLL Clock and Reset Real rims intellqu IX VSSPLL Control PLL Luck lntemlm Sencloclwlude 39 1 Refer to devlce speclllcaliwn lor availability or me low voltage reset lealure lnterruDl Internal Voltage Regul R332 Supply 3312 mm REG ator voom vsSFLL vDD VDD1 AD quiet k gt Lva of m pea WE J 12m v551 LVl what program is executed after POR Power On Reset Detection of VDD transition Assert reset until clocks are stable External Reset Restart of your hardware and application Afterthe reset is completed the microcontroller executes your main program Reset recovery time depends on clock speed RESET DRGdrlvesiRESETplllow 1mm 1 I rsleassd 1 l posslbly W l quot 9W possibly mm minalga ed RESET Cy es 596 mg dwell9W an lrllemal synchranlzatlorl many delay Ml mnrllng Low Voltage Reset If VDD is below desired state we need to reset system to prevent undesirable behavior protect unintentional corruption of internal registers and flash memory what program do you want to run if low voltage reset occurs Watchdog COP Protection against software failures User application will need to write code sequence to register periodically lf software fails to write to register COP occurs Based on OSCILLATOR clock Occurs at user defined intervals 10 Clock Monitor If clock outside of specifications too slow interrupt occurs what program do you want to run if CM reset occurs Real Time Interrupt RTI based on OSCILLATOR clock high priority interrupt which occurs at user defined intervals what is a real time requirement do we have a need for that at this time External Hardware Interrupt in addition to RESET Interrupt Pins Interrupts handle asynchronous requests XIRQ PEO and IRQ PE1 are active low External hardware can be attached eg keypad XIRQ nonmaskable interrupt can always interrupt CPU for serious system problems eg battery problems IRQ software maskable interrupt used for general requests 11 Interrupt Pins Can be used with multiple interrupt sources Each source must be an open drain type driver to avoid contention between multiple devices wired OR network Interrupt service routine will need to determine device that caused interrupt Single pullup resistor close to interrupt pin disables interrupt do we have external devices requiring interrupts currently 68H CS I 2C SPI PIn ASSIgnment m 59 email 5 QAN 232 HO ET 3 a x ke ad a Igsg g ND 11 a m 7 v 3 a VP eggs Eiia gs Ref l7 l7 l1 l7 l Fl l Fl 4 t m c Port T PWOAOCDPTC39Et S Q g Q g Q g 6quot 3 35 l RH PWllOClI PTI E 2 35 l DDA Inpm capture WWWPT E3 34 l 2400mm OUtPUt Compar PWSIlOCEFTS E4 33 l PADosrAan PVVM 25V VDDI 5 32 3 mowan Port AD VSSI E6 MCSSlZOFamIly at I PADWAW DIO PWMlOmPTA E7 Mcgmcwam w 3n 3 PADOSIANKB locaws EB 29 91002 an Analog In lOCEiPTB E9 28 l PADO IiANDt lamPT l 390 27 l PADODtANUU Debug momma l M 26 l PAD Port A pBAElZE 3 E w I m g a a Q 25 3mm POI IB uuuuuuuuuuuu e v m c o u Q E E as gt gt EB X PLL B read electrical CLK Config V Filter specifications CLK Reg for details on O 39 Resa 08 voltage levels lO Ports Po h ega thodme if a port or pin is not available what does this physically mean Port Integration Module llDATAt BKGDMODCTAGH x R R m ItlDATAll 12 13 14 15 12 IO PAB70 core logic and multiplexed bus PAO PB4 minimal functionality available in 48pin package AD70 analogdigital module 8 channels PT70 timer module PWM module routed to this port PS30 SCI module one RX one TX PM50 MSCAN SPI TXCAN RXCAN MISO MOSI SCK SS PP70 PWM module PJ76 interrupt sources PE70 general contol BKGDB XIRQ RQECLK if a port inputoutput is not connected to an external pin what is happening to that resource IO For every port you can select lO direction inread outwrite Drive strength full power reduced power Enable pull updown resistors Every port 5V digital inputoutput or analog in Input with selectable pullup or pulldown resistors 47k Ohm pull up or down to 5V 1 or ground 0 why do we use a resistor for pull updown Example PORT T PT Writing to port output Reading from port input OutputInput has different hardware Can connect General purpose digital lO 5V level Timer Input Capture Output Compare PWM Pulse Width Modulation Example PT Address Offset 240 O register holds value driven out or read in Address Offset UU Eu 7 e 5 4 3 2 I El 0 Read P lf PTTG PTTS FTT4 PTTC PTTZ PTT1 PTTG Write 1 TM lOC7 lOCG i955 iocg lOCS lOCZ lOC1 lOCG PWM PW4 PWME PWMZ PWM PWMU Reset D o u U u U u 0 l Reserved umm merited digital lO Timer inputoutpu PWM on how many pins can we have PWM can we have Timer functions and PWM on different pins simultaneously 13 Example PT Address Offset 241 Read Status of Pins regardless of connected hardware Address Offset so1 EH7 f5 5 4 3 2 l Bno Read l FTlT I l FTlTG l PTIT5 l FTIT4 l PTITS l PTIT2 l PTIT1 l PTlTU l WVquot l l l l l Reset A r t t Reserved orunmtplemented Address Offset 242 Data Direction input or out ut Address Offset 802 Elt7 6 5 4 3 2 l Bit 3 DDR39W DDRTS DDRTE DDRT4 DDRTS DDRT2 DDRTT DDRTD Reset D O U 0 U U D D Reserved or unimplemenled can you read from output port Example PT Address Offset 243 Reduced Drive 113 Address Offset 35 03 Bit 7 6 5 4 3 Z i BRO Read Wme RDRW RDRTG RDRTS RDRT4 l RDRTC l l RDRTZ l RDRTl l RDRTO 1 Reset D 0 0 0 0 U D Reserved or unimplemenied Address Offset 244 Pull updown enable Address Offset s04 Bit 7 6 5 4 3 2 l Bit D Read Wme PERT PERTG PERU FERT3 PERTZ PERT PERTO I Reset D 0 U U D 0 0 D l Reserved or ummplemented PERTS are resistors built in Example PT Address Offset 245 Polarity selector 1 p u lld own Address Offset 05 Bit 7 5 5 A 3 2 l Bit 0 55 RDRW RDRTG RDRTE RDRT4 l RDRT3 l RDRTZ l RDRT l l RDRTO Reset I D 0 0 D 0 I O Reseryed or unimplemenled Address Offset 247 Module routing 1PWM OTM Address Offset 04 Ext 7 6 5 4 3 2 l Bit D 3 PERT7 PERTFS PERTS l PER39W FERT3 PERTZ PERTl l PERTO Reset D 0 U 0 D D U 0 Reserved or unimpleniented Port MS Pins Six bidirectional pins PM5 PMO General purpose port Serial Port SCI and SPl Asynchronous SCI serial communications interface PSO becomes RxD and PS1 becomes TxD Synchronous SPl serial peripheral interface PM2 PM3 PM4 PM5 become SPl functions CAN controlled area network PMO PM1 for Rx and Tx data 14 Serial IO SPI synchronous serial peripheral interface rMOSI COntrOl outi receiver In PM2 rMISO COntrOl In receiver Out PM 7804 CIOCK PM4 r 55 receiver select PM5 rWlth 25 MHZ bus rate maxlmal l2 MHZ serial transferapprox l Mbytesecond emmnge all one between mmmllev and vecelvevln me tremendan Serial IO SCI asynchronous serial communication interface 7 RX data P80 7 TX data PSI 725 MHZ bus speed 38400 baud sends mm M bits per byte l baud l bitsecond Serial Communication Will need additional external electronics R8232 Maxim Driver Signal levels on tne R8232 cable are lov wnen tne rnicrocontroller sends data on TX it Will navetO reacn Rx on your COM port OfyOur desktop computer Pin 3 on COM port is Rx Pin 2 on COM port is TX Pin 5 is ground goes on cable snield RS232 connectors Pin lnsenionl side oltne DEaF izaoa 5789 39Pin lnsenionl sldE oltne DEaM 387 15 MSCAN 0 Motorola Scalable Area Network 12 CAN20 NB 0 BOSCH 1991 standard 0 Can attach multiple devices RX PMO TX PM1 0 08 bytes data length in a frame 0 1 Mbps 0 requires additional transceiver electronics In Circuit Debugging Background Debug Module BKGD pin Single wire serial interface On chip hardwarefirmware Hardware commands to readwrite memory Software commands to readwrite CPU resources registers TRACE execute one instruction from program than return to debug TAG instruction execute until tagged instruction in execution queue once CPU status is sent to host computer microcontroller already has started executing the instruction gt need to tag Backgrnd Debug Module HOST SYSTEM BKGD IEVBlT SHlWREGlSTER I w ADDRESS ENTAG BUS lNTERFACE lNSTRUCTlON DECODE gt EDMACT AND EXECUTION ltgt com ioeic DATA TRACE lt CLOCKS SDV STANDARD BDM ENEDM FlRMlA ARE WSW LOOKUP TABLE 16
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