Class Note for CHEM 112 at UMass(44)
Class Note for CHEM 112 at UMass(44)
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This 17 page Class Notes was uploaded by an elite notetaker on Friday February 6, 2015. The Class Notes belongs to a course at University of Massachusetts taught by a professor in Fall. Since its upload, it has received 17 views.
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Date Created: 02/06/15
ENGIN 112 Intro to Electrical and Computer Engineering Lecture 37 Register Transfer Level quot ELECTRICAL 9 quot COMPUTER ENGINEERING umvsnswv or MASSACHUSETTS AMHERST ENGIN11Z L37 Register Transler Level Decemh2r32 3 Overview System design must be modular Easier to represent designs with systemlevel blocks Register transfer level represents transfers between clocked system registers Shifts arithmetic logic etc Algorithmic state machine Alternate approach to representing state machines Status signals from datapath used for control path Algorithmic state machine chart shows flow of computation ENGN112 L37 Register Transfer Level December 3 2003 Systemlevel Design Difficult to represent a design with just one state machine A series of control and data paths used to build computer systems Helps simplify design and allow for design changes ENGN112 L37 Register Transfer Level December 3 2003 Registers and Data Operations Activity and performance in computers defined on reglstertoregIster paths Digital system at register transfer level specified by three components The set of registers in the system Operations to be performed on registers Control that is applied to registers and sequence of operations Function ENGN112 L37 Register Transfer Level December 3 2003 Representation of Register Transfer Flow Arrow indicates transfer from one register to another R2 2 R1 Conditional statements can help in selection lfT1 1then R2 R1 Clock si nal is not generally included in register transfer evel statement Sequential behavior is implied Multiple choices also possible lfT1 1then R2 2 R1 R2 2 R2 How could these statements be implemented in hardware ENGN112 L37 Register Transfer Level December 3 2003 Other representative RTL operations Addition R1 R1 R2 Increment R3 R3 1 Shift right R4 R4 Clear R5 0 Transfer doesn39t change value of data begin moved How could these statements be implemented in hardware ENGN112 L37 Register Transfer Level December 3 2003 Algorithmic State Machines gASMz Flowchart specifies a sequence of procedural steps and decision steps for a state machine Translates word description into a series of operations with conditions for execution Allows for detailed description of control and datapath Status conditions Commands gt Control Datapath loglc External Input Output gt gt gt inputs data data Fig 8 2 Control and Datapath Interaction ENGN112 L37 Register Transfer Level December 3 2003 Algorithmic State Machines State Box ASM describes o eration of a sequential curcuu ASM contains three basic N l Bingry T i on elements we CO 6 Re istero eration R 0 State box gorouggut STXRT Decision box Condition box l l M a General description b Specific example state Box also indicates operation to be performed Fig 8 3 State BOX Binary code and state name also included ENGN112 L37 Register Transfer Level December 3 2003 Decision Box Describes the impact of input on control system Contains two exit paths which indicate result of condition More complicated conditions possible Implemented in hardware with a magnitude comparator Exit path Exit path Fig 8 4 Decision Box ENGN112 L37 Register Transfer Level December 3 2003 Conditional Box 0 Indicates assignments following a decision box 0 Generally indicates data transfer T1 001 START From exit path of decision box l ED Register operation or output a General description b Example With conditional box T2 V v 010 FEE Fig 8 5 Conditional BOX ENGN112 L37 Register Transfer Level December 3 2003 ASM Block O Paths exist between state boxes 0 Each state box equivalent to one state T2 Fig 8 6 ASM Block ENGIN112 L37 Register Transfer Level December 3 2003 ASM Block 0 Equivalent to State Diagram Fig 8 7 State Diagram Equivalent to the ASM Chart of Fig 8 6 Fig 8 6 ASM Block ENGN112 L37 Register Transfer Level December 3 2003 Concept of the State Machine Example Odd Parity Checker Assert output whenever input bit stream has odd of 139s Reset Present State Input I Next State Output E Even 0 Even 0 0 Even 1 Odd 0 Odd 0 Odd 1 Odd 1 Even 1 1 1 Symbolic State Transition Table Present State Input I Next State Output 0 Q o o o o 0 1 1 0 1 0 1 1 State 1 1 o 1 Diagram Encoded State Transition Table Note Present state and output are the same value Moore machine ENGN112 L37 Register Transfer Level December 3 2003 ASM for Odd Parity Checker Example Odd Parity Checker Assert output whenever input bit stream has odd of 139s gset 0 1 State Diagram 1 ENGN112 L37 Register Transfer Level December 3 2003 Verilog Representation for RTL O Conditional assignment statements assign Y S 10 0 Statement evaluation always l1 or l2 or S if S Y l1 else Y l0 Perform evaluation only when an input changes always posedge clk q d Verilog description of a flip flop ENGN112 L37 Register Transfer Level December 3 2003 Typical Design Flow o I I I I It all starts WIth Verllog description V gt HDL description Valld gt Synthesis Nethst gt Of design design tools it v Simulate Simulate 4 Test bench RTL deagn gate level design V V Result Result Good Good Needs Needs correction correction V V Compare Fabricate No match Match 1C Fig 8 1 Process of HDL Simulation and Synthesis Summary Register transfer level provides a simple way to descrIbe deSIgns A series of operations take place between registers Algorithmic state machine another way to represent a state machine Direct correspondence between state diagram and algorithmic state machine Possible to implement state machines in Verilog Also in VHDL Next time programmable array logic ENGN112 L37 Register Transfer Level December 3 2003
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