Class Note for CHEM 112 at UMass(45)
Class Note for CHEM 112 at UMass(45)
Popular in Course
Popular in Department
This 16 page Class Notes was uploaded by an elite notetaker on Friday February 6, 2015. The Class Notes belongs to a course at University of Massachusetts taught by a professor in Fall. Since its upload, it has received 15 views.
Reviews for Class Note for CHEM 112 at UMass(45)
Report this Material
What is Karma?
Karma is the currency of StudySoup.
You can buy or earn more Karma at anytime and redeem it for class notes, study guides, flashcards, and more!
Date Created: 02/06/15
ENGIN 112 Intro to Electrical and Computer Engineering Lectu re 1 9 Sequential Circuits Latches quot ELECTRICAL 9 quot COMPUTER ENGINEERING umvsnswv or MASSACHUSETTS AMHERST ENGIN11Z L19 Sequential 0dnher172 3 Overview Circuits require memory to store intermediate data Sequential circuits use a periodic signal to determine when to store values A clock signal can determine storage times Clock signals are periodic Single bit storage element is a flip flop A basic type of flip flop is a latch Latches are made from logic gates NAND NOR AND OR Inverter ENGN112 L19 Sequential Circuits Latches October 17 2003 The story so far Logical operations which respond to combinations of inputs to produce an output Call these combinational logic circuits For example can add two numbers But No way of adding two numbers then adding a third a sequential operation No way of remembering or storing information after inputs have been removed To handle this we need sequential logic capable of storing intermediate and final results ENGN112 L19 Sequential Circuits Latches October 17 2003 Seguential Circuits Inpms Combinational OUtPUtS circuit Next State Present state Timing signal clock Clock synchronizes when current state changes happen keeps system wellbehaved makes it easier to design and build large systems ENGN112 L19 Sequential Circuits Latches October 17 2003 Crosscoupled Inverters O A stable value can be stored at inverter outputs State 1 State 2 ENGN112 L19 Sequential Circuits Latches October 17 2003 SR Latch with NORs R reset Q S R Q Q l l 0 0 Unde ned l O 1 0 Set a 0 1 0 1 Reset s set 0 0 2 5 Stable SR latch made from crosscoupled NORs If Q 1 set state If Q 0 reset state Usually S0 and R0 S1 and R1 generates unpredictable results ENGN112 L19 Sequential Circuits Latches October 17 2003 SR Latch With NANDs S Q Disallowed Set Q1 Reset R Store Latch made from crosscoupled NANDs Sometimes called S R latch Usually S1 and R1 0 S0 and R0 generates unpredictable results ENGIN11Z L19 Sequential Circulls Latches 0dnher172 3 SR Latches R Reset Q gt 3 Logic diagram 3 Set DTQ gtlt R Reset O 1 a Logic diagram ENGN112 L19 Sequential circuits Latches s R Q 6 1 0 1 0 Selstate 0 0 1 0 O 1 0 1 O O 0 1 Reselstate 1 1 0 0 Undefined b Function table s R Q 6 0 1 1 0 Setstate 1 1 1 0 1 0 0 1 1 1 0 1 Resetstate 0 0 1 1 Undefined b Function table October 17 2003 SR Latch with control inlgut No change No change Q 0 Reset state Q 1 set state Indeterminate C o l l kHl OQ i HOOXM i OHOX it S Q Next state of Q a Logic diagram b Function table Fig 5 5 SR Latch With Control Input Occasionally desirable to avoid latch changes C 0 disables all latch state changes Control signal enables data change when C 1 Right side of circuit same as ordinary SR latch ENGN112 L19 Sequential Circuits Latches 06t0b6r17 2003 NOR SR Latch with Control Input Latch is levelsensitive in regards to C Only stores data if C R ENGN112 L19 Sequential Circuits Latches Q utpu ts Chang 3 Mb in C i RE Q il h 39wi wi HOLD October 17 2003 D Latch Q0 indicates the previous state the previously stored value D Store Reset Set Disallowed 0dnher172 3 ENGIN11Z L19 Sequential Circuils Latches Input value D is passed to output Q when C is high Input value D is ignored when C is low ENGIN11Z L19 Sequential Circuils Latches 0dnher172 3 D Latch Latches on following edge of clock E X D Q X Z E e Z Z only changes when E is high If E is high Z will follow X ENGN112 L19 Sequential Circuits Latches October 17 2003 D Latch Latches on following edge of clock E X D Q X Z E e Z The D latch stores data indefinitely regardless of input D values if C 0 0 Forms basic storage element in computers ENGN112 L19 Sequential Circuits Latches October 17 2003 Symbols for Latches SR m D Fig 57 Graphic Symbols for Latches SR latch is based on NOR gates S R latch based on NAND gates D latch can be based on either D latch sometimes called transparent latch ENGN112 L19 Sequential Circuits Latches October 17 2003 Summary l aotghes are based on combinational gates eg NAND Latches store data even after data input has been removed SR latches operate like crosscoupled inverters with control inputs S set R reset With additional gates an SR latch can be converted to a D latch D stands for data D latch is simple to understand conceptually When C 1 data input D stored in latch and output as Q When C 0 data input D ignored and previous latch value output at Q Next time more storage elements ENGN112 L19 Sequential Circuits Latches October 17 2003
Are you sure you want to buy this material for
You're already Subscribed!
Looks like you've already subscribed to StudySoup, you won't need to purchase another subscription to get this material. To access this material simply click 'View Full Document'