Class Note for CMPSCI 377 at UMass(60)
Class Note for CMPSCI 377 at UMass(60)
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This 3 page Class Notes was uploaded by an elite notetaker on Friday February 6, 2015. The Class Notes belongs to a course at University of Massachusetts taught by a professor in Fall. Since its upload, it has received 19 views.
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Date Created: 02/06/15
CMPSCI 377 Operating Systems Fall 2007 Lecture 2 September 10 Lecturer Emery Berger Scribes Andrew Syriala Ellth Prakash 21 Intro 0 Registers o Caches AssociatiVity o Cache Misses 211 Memory Hierarchy In the memory heirarchy the higher you are the lower latency you have and the more expensive you are From Ferrari to Bicycle 0 Register 1 cycle latency o Cache L1 2 cycle latency L2 7 cycle latency L3 less latency than RAM more than L2 0 RAM 100 cycle latency o DISK 40000000 cycle latency 0 Network 200000000 cycle latency 212 Registers Rather than accessing a single location of memory a dedicated name for a word of memory is managed by a CPU 0 General Purpose Registers AX BX CX on x86 0 Special Purpose Registers 77 hold program state they usually include the program counter aka instruction pointer stack pointer and status register aka processor status word 1777 SPStack Pointer Points to top of stack FPFrame Pointer Points to Where you are PCProgram Counter Where you are in the codeWhat address youlre at Context Switch When you change from one process to another you have to save current registers and load saved registers 21 22 Lecture 2 September 10 213 Caches Cache Since access to main memory is expensive we have caches which is small fast but expensive memory Caches hold recently accessed dataD or instructionl There are 3 different types of caches with different sizes and physical locations that corresponds to their speed 0 L1 ls fast because it is On chip also it is the smallest 0 L2 Slower than Ll because it is on or next to chip also it is larger than L1 0 L3 Slower than L1 and L2 because it is on the bus larger than L2 and L1 Approximate access times for common memory types 214 Terminology cold This is the term for when the cache is initially empty 0 hit This is the term for when you are accessing data that is found in the cache 0 miss This occurs when you are trying to access data that is not in the cache 0 fetch When a miss occurs we need to retrieve the information so the data is retrieved from a lower level in the hierarchy This is slower than a hit 0 populating the cache This is the term for the lling of the cache caused by misses o warmed up This is the term for when the cache holds the most frequently used data note A context switch changes processes so now the data in the cache is not going to be the most frequently accessed data so the cache is once again cold 0 ideal cache fully associative77 based on LRU queue 77 past behavior is a good predictor of the future The thing you just used is in front the thing you havenlt used in a while is in the back Emery Berger 0 ways Since a fully associative cache is too expensive we partition memory addresses and put into bins which are divided into ways l way or direct mapped 2way or 2 entries per bin 4 way or 4 entries per bin etc 215 Miss Clari cation o Compulsory Miss This occurs the rst you access data Never avoidable 0 Con ict Miss This happens when too many items are mapped to the same address ie too many items in a way This is avoidable with higher associativity 0 Capacity Miss This occurs when there is no more space in the cache Avoidable if cache were larger 0 Coherence Miss Occurs when you have more than one processor sharing the cache and both try to modify resulting in invalidation Avoidable if cache were unshared Lecture 2 September 10 216 Quotes of the Day 0 howdoigetmyGerbilOutoftheToileticorn o esperanto yiddish dictionary 0 Dealing With bad things 1 Stop them 2 Fix them 23
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