Class Note for ENGIN 112 at UMass(19)
Class Note for ENGIN 112 at UMass(19)
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Date Created: 02/06/15
College of Engineering University of Massachusetts Amherst ENGIN 112 Introduction to Electrical and Computer Engineering Fall 2008 Discussion A 12 Registers and Counters I Registers An nbit register is just a set of n flipflops that are connected to a common clock and are used to store n bits A register may also include other circuitry to control the values that are stored Example 4bit D A0 A 1 A2 A3 flipflop register 0 1 J l2 3 J lo l3 data bits D D D D input A0 A3 gtC gtC gtC gtC stored bits R R R R clear T T E r clock I L When Clear 0 all flipflops are reset to 0 When Clear1 the inputs are transferred to the flipflop outputs at the next positive clock edge This is called parallel loading all the data are transferred at the same time One problem with the simple register design is that the inputs are transferred to the register that is stored at the flipflop outputs on each clock cycle If we want to maintain the stored values we must either make sure that the inputs don t change or have some circuitry that prevents the transfer One way to control the loading of new data into the register is to use a 2 x 1 multiplexer for each flipflop that connects either the new data input or the currently stored bit to the flipflop input depending on the value of a load control bit When Load 0 the input to the 2X 1 D AK flipflop is set to the current Ik MUX gtC output AK when Load 1 the R flipflop input is the new data input Ik Load T o A shift register is a connection of flipflops that shift data from one register to the next on a clock edge Serial Input 8 D D D D Serial Output 80 gt C gtC gt C gt C R R R R clear T T E i O O I At a clock edge A new bit of data 8 is transferred into the leftmost flipflop Each flipflop except for the rightmost transfers its current stored bit to the next flipflop to the right The current output bit 80 is replaced by the value currently at the rightmost flipflop s input Note we can also add load control to each flipflop s input if we want to prevent data transfer on some clock cycles Example Suppose the four flipflops in the shift register diagram are all loaded with 0 s initially Asequence of input bits 101010 synchronized with the clock enters the shift register at 8 Let the clock transition times be denoted T0 initial time T7 etc What values are stored in the flipflops during the clock cycles Time Input Values Stored in First Output SI Three FlipFlops SO After To 1 0 0 0 0 After T1 0 1 0 0 0 After T2 1 0 1 0 0 After T3 0 1 0 1 0 After T4 1 0 1 0 1 After T5 0 1 0 1 0 When bits are transferred one at a time from a source register to a destination register we say we have serial data transfer as opposed to the parallel transfer in the first register that we saw Serial data transfer makes use of shift registers Typical system for serial data transfer using two 4bit shift registers Feedback loop keeps data Shift Register Circulating in gt A RegisterA SA clock Shift Register B SOB Shift control J CLK Shift control selects four clock pulses to perform data transfer Example Suppose we want to transfer four bits 1 0 1 0 stored in RegisterA to Register B which initially stores bits 0 1 0 1 Clock T1 T2 Ts T4 Shift Control CLK Time Register A Register B Initial 1010 0101 AfterT1 0101 0010 AfterT2 1010 1001 AfterT3 0101 0100 AfterT4 1010 1010 Many operations can be done with either parallel or serial data transfers parallel operations are faster but serial designs are often simpler that is require fewer components to implement One example is an adder circuit Recall the 4bit adder circuit that we saw previously A2 82 A1 B1 A0 Bo A3B if H ll ll c c c c4 lt A lt 3 FA FA lt 7 FA lt Co l l l l s3 s2 31 so This circuit works essentially in parallel it requires a separate Full Adder block for each bit position Note that this is a combinational circuit Now suppose that we want to construct a serial adder Serial operation implies that we must consider time as a parameter so we must design this adder as a sequential circuit Let s use a D flipflop to store the current carry bit let the circuit output be the current sum bit and let input bits X y denote the current two bits to be summed along with the current carry bit Current Current Inputs Output Next State StateQ x y S Qt1 O O O O 0 State Table 0 O 1 1 O O 1 O 1 O O 1 1 O 1 1 O O 1 O 1 O 1 O 1 1 1 O O 1 1 1 1 1 1 Notice that we can take advantage of the Full Adder block to generate the sum and carry bits while the inputs can be stored in shift registers In fact to add two fourbit numbers we can use the following circuit Serial input Shift Register B gt Shift Register Sum bit A i Output carry FA Not shown but included in circuit Common clock and shift control for registers and flip op and Clear input for flipflop gt CLK Input carry Example Go through steps for serial addition of 4bit numbers A0111 and B 1010 Assume that the serial inputs to the B register are all US Note that the addition starts with the flipflop cleared so QT00 39 Time Register Register Q FAlnputs FAOutputs A B ABQ SumCarry To 0111 1010 0 100 1 0 T1 1011 0101 0 110 0 1 T2 0101 0010 1 101 0 1 T3 0010 0001 1 011 0 1 T4 0001 0000 1 end 80 After 4 clock cycles stored sum isl 0001 Carry out bit stored in flip op Sum bits stored in RegisterA Note that data entered serially into a shift register can be taken out in parallel just by tapping into the flipflop outputs Also parallel loading capability can be added then data entrydata removal can be any choice from serialserial serialparallel parallelserial or parallelparallel Also the register can be constructed so it can shift either left or right A register with all these capabilities is called a universal shift register Circuit Parallel outputs AA A A A0 Cl C C C C CLK Control Mode Control Register 31 I 80 Operation 51 4 X1 4 x 1 4 X1 4 X1 0 O No change 50 MUX MUX MUX MUX 0 1Shiftright 3210 321i 3210 3210 1 O Shift left I I I I I I 1 1 Parallel load Serial SeriaI input for in 39 I putfor Bluff Em shiftleft r3 3 n In Parallel inputs II Counters A counter is a register that goes through a specified set of states as transition pulses from a clock or some other source are applied If an n bit register cycles through the binary numbers from 0 000 to 2 1 111 it is called a binary counter If the counter cycles through BCD representations for 01 it is called a BCD counter If all counter transitions are governed by a common clock we have a synchronous counter If instead the pulses governing transitions in some flipflops are generated by the outputs of other flipflops we have a ripple counter Let s design a 3bit binary ripple counter Assume that there are input pulses called Count into one flipflop that trigger the transition of the least significant bit LSB We have 3 flipflops call their outputs A B C and 8 states 000 001 111 Say that we want to initiate a count state transition on the negative edge of the Count pulse The state table is Current State Next State ABC ABC 000 001 001 010 010 011 011 100 100 101 101 110 111 Note that on every state transition the least significant bit C is complemented Bit B changes when C changes from 1 to 0 Bit A changes when B changes from 1 to 0 Consider circuit D Count 0 gtC R 0 Note that the pulse edges for transitions from 1 to 0 in each flipflop output are used to initiate data D transfer from input to gtC output in the succeeding R 0 flipflop T Reset O D 4 j Note that it takes some very small but not zero time for the flipflop output to respond to transitions on the clock input So we can think of the state changes as rippling through the flipflops A negative puse edge in Count causes a change in C a very short time later if that change in C is from 1 to 0 it creates a negative puse edge that in turn triggers a transition in B a very short time later etc Example Say we are in state 010 Consider timing of transitions to succeeding states Count 0 1 o c 1 1 o B 1 A Example How could we design a BCD ripple counter Note that a BCD counter should have state table using 4 flipflops Current State Next State ABCD ABCD 0000 0001 0001 0010 0010 0011 0011 0100 0100 0101 0101 0110 0110 0111 0111 1000 1000 1001 1001 0000 Note that the pattern is the same as the binary ripple counter a transition from 1 to 0 in a bit triggers a change in the next most significant bit except for state 1001 in that state the next transition must set all registers to 0 That is it must clear all the registers So we can use a 4bit binary ripple counter with a Reset line that 0 when A1 D1 and Count0 D Count A When transition is made to state 1001 the next Count transition to zero sets the Reset to 0 this clears all flipflops and gets us back to state 0000 Reset Ripple counters are examples of asynchronous systems the timing of transitions between state is not controlled by a clock but instead by the possibly irregular timing of the Count pulses Now suppose we want to build a synchronous counter whose transitions are controlled by a clock Let s go through the design procedure for a 3bit synchronous binary counter start with the state table Current State Next State ABC ABC 000 001 001 010 010 011 011 100 100 101 101 110 110 111 111 000 Note that Cz 1 C Bz 1 BC BC Az 1 ABC ABC Circuit Clock o gtC
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