Class Note for ENGIN 112 at UMass(22)
Class Note for ENGIN 112 at UMass(22)
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Date Created: 02/06/15
ENGIN 112 Intro to Electrical and Computer Engineering Lecture 27 Counters quot ELECTRICAL 9 quot COMPUTER ENGINEERING umvsnswv or MASSACHUSETTS AMHERST ENGIN11Z L27 Cnunlers Nnvemher J Overview Counters are important components in computers The increment or decrement by one in response to input Two main types of counters Ripple asynchronous counters Synchronous counters Ripple counters Flip flop output serves as a source for triggering other flip flops Synchronous counters All flip flops triggered by a clock signal Synchronous counters are more widely used in Industry ENGN112 L27 Counters November 5 2003 Counters Counter A register that goes through a prescribed series of states Binary counter Counter that follows a binary sequence N bit binary counter counts in binary from n to 2quot1 Ripple counters triggered by initial Count signal Applications Watches Clocks Alarms Web browser refresh ENGN112 L27 Counters November 5 2003 Binag Ripple Counter T A0 Count c CR Count c CR 0 f T o Reset Signal sets all outputs T to 0 T A1 D Count signal tog les output a CR a CR of of loworder fle op i T Loworder fli flop provides T A2 D trIgger for a jacent fle flop o c C 4c C Not all flops change value R R e f 3 simultaneously Lowerorder flops change first T A3 D Focus on D flip flop C C Implementation i 7 I Logic 1 Reset Reset a With T ip ops b With D flip flops Fig 6 8 4 Bit Binary Ripple Counter ENGN112 L27 Counters November 5 2003 Another Asynchronous RiEple Counter D J C J B J A J C39 CLK OJ CLK O l CLK OJ CLK 0 IL 7D K 70 K 78 K 7A K O39 39AII J and K inputs assumed to be I D DCBA 3 3 5 3 3 5 3 mum ooouimm3001050011301003010150110301111 10103101151100311015111051111300003000120010 L Recycle to 0000 Similar to T flop example on previous slide 0 ENGN1 12 L27 Counters NovemberS 2003 Asynchronous Counters lglgch FF output drives the CLK input of the next FFs do not change states in exact synchronism with the applied clock pulses 0 There is dela between the responses of successwe Fs Ripple counter due to the wa the FFs respond one after another In a kind 0 rIppIIng effect 99gt gt gt lg 2 1 p r OOOOOO OOOOHHO lr Or Or Or O ENGN112 L27 Counters November 5 2003 Synchronous counters I An C Synchronousparalel counters Count enable All of the FFs are triggered simultaneously by the clock input pulses All FFs change at same time Remember If JK0 flop maintains value If JK1 flop toggles Most counters are synchronous in computer systems Can also be made from D ops Value increments on pOSltlve edge To next stage CLK Fig 6 12 4 Bit Synchronous Binary Counter ENGN112 L27 Counters November 5 2003 S ChI39OI39IOUS counters O Synchronous counters Same counter as previous slide except Count enable replaced by JK1 Note that clock signal is a square wave Clock fans out to all clock inputs g An Air 3quot H RE I A l 39x ti 3 C 1 D J L J E I g 139 I 39 I Livia ELKif CLM D Il ELKCO D r L F I F 39A r i JI l L 1 I mm a ENGN112 L27 Counters November 5 2003 Circuit operation ESHril D 39C39 39 El if Cl C CII I2 I 1 rquot 1 CI 1 2 IT I39J 1 f2quot 3 I CI 1 I I III I D D 5 I 1 I39TI I E El I I III 7 CI 1 1 1 3 1 i U 339 l 9 39l D I 39l 10 1 a 1 l 1 1 39I I3 1 39I 12 1 1 I I 1393 1 1 CI 1 14 I 39I 1 1quot IE I 1 1 1 i r E l I39J EaztI E I1 Count value Increments on each negative edge 0 Note that loworder bit A toggles on each clock cyc e ENGN112 L27 Counters November 5 2003 S nchronous UPDown counters Up 39 gt T UplDown Counter can either DOW C count up or down on each clock cycle Up counter counts from 0000 U to 1111 and then changes j T back to 0000 C Down counter counts from 1111 to 0000 and then back j to 1111 L 39 gt T Counter counts up or down c each clock cycle Output changes occur on clock rising edge T C ENGIN112 L27 Counters CLK Fig 613 4Bit Up Down Binary Counter November 5 2003 Counters with Parallel Load Counters with parallel load can have a preset value Load signal indicates that data I lo should be loade into the counter Clear resets counter to all zeros Carry output could be used for higherorder bits ENGN112 L27 Counters Count Load 10 Clear CLK Carryoutput Fig 6 14 4 Bit Binary Counter with Parallel Load November 5 2003 Counters with Parallel Load Count Clear Clk Load Count Function 0 X X Clear toO Load Load inputs lo 1 Count 0 No Change gtltgtlt 1 1 A0 1 O 1 O 11 Function Table If Clear is asserted 0 the 12 counter is cleared If Load is asserted data inputs are loaded If Countasserted counter value IS Incremented Clear CLK Carryoutput Fig 6 14 4 Bit Binary Counter with Parallel Load ENGN112 L27 Counters November 5 2003 Binary Counter with Parallel Load and Preset rese a epara e 00quotquot er WI P1 asynchronous preset Parallel data inputs p2 l l O PHE J O PHE J on PRE J CLK CLK CLK O CLFl K cm K CLFl K quot I I CLOCK mm Parallel load iPL U lgtcgt If PL 0 load P into flops Binary Counter with Parallel Load and Preset Commercial version of binary counter PL P3 P2 P1 P0 Pin Description i i w T CPU Countup clock Input 7 active rising edge CPU TCU 74ALs193 0 CPD Countdown clock input M0016 u down 7 active rising edge CPD f TCD CCUquot er 0 MR Asynchronous master reset input active HlGH FTL Asynchronous parallel load input V v V actlve LOW MFl C23 Q2 Q Q0 8 PurP5 Parallel data inputs QDQ3 Flipflop outputs Mode Select 7 i TCD Terminal countdown borrow output MR PL CPU CPD Mode active LOW H X X X Asynchr reset 7 L L X X Asynch prEse TCU Terminal countup carry output L H H H No change Mel LOW L H T H Count up 0 L H H 1 Count down H HIGH L LOW X Don t care T PGT c ENGIN112 L27 Counters November 5 2003 Summary Binary counters can be ripple or synchronous Ripple counters use flip flop outputs as flop triggers Some delay before all flops settle on a final value Do no require a clock signal Synchronous counters are controlled by a clock All flip flops change at the same time UpDown counters can either increment or decrement a stored binary value Control signal determines if counter counts up or down Counters with parallel load can be set to a known value before counting begins ENGN112 L27 Counters November 5 2003