Class Note for ENGIN 112 at UMass(31)
Class Note for ENGIN 112 at UMass(31)
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This 15 page Class Notes was uploaded by an elite notetaker on Friday February 6, 2015. The Class Notes belongs to a course at University of Massachusetts taught by a professor in Fall. Since its upload, it has received 13 views.
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Date Created: 02/06/15
ENGIN 112 Intro to Electrical and Computer Engineering Lecture 28 Timing Analysis quot ELECTRICAL 9 quot COMPUTER ENGINEERING umvsnswv or MASSACHUSETTS AMHERST ENGIN11Z LG Timing Analysis unvemher7znn3 Overview Circuits do not respond instantaneously to input changes Predictable delay in transferring inputs to outputs Propagation delay Sequential circuits require a periodic clock Goal analyze clock circuit to determine maximum clock frequency Requires analysis of paths from flipflop outputs to flipflop inputs Even after inputs change output si nal of circuit maintains orIginal output for short Ime Contamination delay ENGN112 L28 Timing Analysis November 7 2003 Sequential Circuits Sequential circuits can contain both combinational logic and edgetriggered flip flops t clock signal determines when data is stored in flip ops Goal How fast can the circuit operate Minimum clock period Tmin Maximum clock frequency fmalx Maximum clock frequency is the inverse of the minimum clock period 1lein fmax CIOCk Penod I l I I I I Clock ENGN112 L28 Timing Analysis November 7 2003 Combinational Logic Timing Inverter A A lgto Y Y XX tcd l l tpd H H Combinational logic is made from electronic circuits An input change takes time to propagate to the output The output remains unchanged for a time period equal to the contamination delay tccl The new output value is guaranteed to valid after a time period equal to the propagation delay tmI ENGN112 L28 Timing Analysis November 7 2003 Combinational Logic Timing XNOR Gate A BDOC B H II C XX XX tcd l lH tpdw e l l The output is guaranteed to be stable with old value until the contamination delay Unknown values shown in waveforms as Xs The output is guaranteed to be stable with the new value after the propagation delay ENGN112 L28 Timing Analysis November 7 2003 Combinational Logic Timing complex circuits 1m f 12 Circuit X d n8 T 3ns Tpd1ns A 39 cd c A B C T d 5ns B T 1ns Propagation delays are additive Locate the longest combination of tpd Contamination delays may not be additive Locate the shortest path of tcd Find propagation and contamination delay of new combined circuit ENGN112 L28 Timing Analysis November 7 2003 Clocked Device Contamination and Propagation Delay D Q D Clk fgt Q ted 6 1ClkQ Timing parameters for clocked devices are specified in relation to the clock input rising edge Output unchanged for a time period equal to the contamination delay tccl after the rising clock edge New output guaranteed valid after time equal to the propagation delay tckQ Follows rising clock edge ENGN112 L28 Timing Analysis November 7 2003 Clocked Devices Setup and Hold Times 1s 1h D Q 7 lt gtlt gt D Clk fgt Q Timing parameters for clocked devices are specified in relation to the clock input rising edge D input must be valid at least ts setup time before the rising clock edge D input must be held steady th hold time after rising clock edge Setup and hold are input restrictions Failure to meet restrictions causes circuit to operate incorrectly ENGN112 L28 Timing Analysis November 7 2003 EdgeTriggered Flip Flop Timing D X X CLK th hold time tS setup time The logic driving the flip flop must ensure that setup and hold are met Timing values tccl tpd tkQ tS th ENGN112 L28 Timing Analysis November 7 2003 Analyzing Sequential Circuits T 5ns T 5ns TCIk Q 5 5 C39kQ pd T8 2 ns D D Q D Q z FFA FFB gt G gt CLK F What is the minimum time between rising clock edges 0 Tmin TCIKQ FFA Tpd G T5 FFB Trace propagation delays from FFA to FFB Draw the waveforms F max ENGN112 L28 Timing Analysis November 7 2003 Analyzing Sequential Circuits Tpd 4ns Comb Logic F X Y Comb D Q Logic H D Q 2 FFA FFB gt Tpd 5ns gt CLK F TCIk Q 5ns TClkQ 4 5 T5 2 ns What is the minimum clock period Tmin of this circuit Hint evaluate all FF to FF paths Maximum clock frequency is 1Tmin ENGN112 L28 Timing Analysis November 7 2003 Analyzing Sequential Circuits Tpd 4ns Comb max Logic F D Q 2 FFA CLK Fgt Tpd 5ns Fgt Tc39k39Q 5ns TCIkQ 4 ns T5 2 ns 0 Path FFA t0 FFB 39 TCIkQFFA TpdH TsFFB 5ns 5ns 2ns 12ns Path FFB to FFB TCLKQFFB TpdF TpdH TSFFB 4ns 4ns 5ns 2ns ENGN112 L28 Timing Analysis November 7 2003 Analyzing Sequential Circuits Hold Time Violation Tcol 1ns Tcol 2ns Th 2 S D D Q D Q z FFA FFB gt G gt CLK F One more issue make sure Y remains stable for hold time Th after rising clock edge Remember contamination delay ensures signal doesn t change How long before first change arrives at Y TcdFFA Tc G gt Th 1ns 2ns gt ns ENGN112 L28 Timing Analysis November 7 2003 Analyzing Sequential Circuits Hold Time Violations Tcol 1ns All aths must satisf re uirements P y CI Comb Logic F D Q D Q 2 FFA FFB gt Tcol 2ns gt CLK F TC39D mg TCID 1 ns Th 2 ns Path FFA to FFB TCDFFA TCDH gt ThFFB 1 ns 2ns gt 2ns 0 Path FFB t0 FFB 39 TcpFFB TcpF TCdH gt ThFFB 1ns 1ns 2ns gt 2ns ENGN112 L28 Timing Analysis November 7 2003 Summary Maximum clock frequency is a fundamental parameter In sequential computer systems Possible to determined clock frequency from propagation delays and setup time The longest path determines the clock frequenct All flipflop to flipflop paths must be checked Hold time are satisfied by examining contamination delays The shortest contamination delay path determines if hold times are met Check handout for more details and examples ENGN112 L28 Timing Analysis November 7 2003
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