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# Class Note for ENGIN 112 at UMass(33)

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Date Created: 02/06/15

ENGIN 112 Intro to Electrical and Computer Engineering Lecture 33 Arithmetic Logic Unit ALU quot ELECTRICAL 9 quot COMPUTER ENGINEERING UNIVERSITY or MASSACHUSETTS AMHERST ENGIN11Z L33 Arilhmelic Lngic Llnils NnvemherZLZ Overview Main computation unit in most computer systems ALUs perform a vaiety of different functions Add subtract OR AND Example ALU chip 74LS382 Has data and control inputs KildliJvidual chips can be chained together to make larger s ALUs are important parts of datapaths ROMs often are usd in the control path Build a data and control path ENGN112 L33 Arithmetic Logic Units November 21 2003 ROMbased Moore Machine Timing What is the maximum clock frequency of this circuit Does this circuit satisfy hold time constraints ENGN112 L33 Arithmetic Logic Units November 21 2003 Arithmetic Lo ic Unit Arithmetic logic unit functions Two multibit data inputs Function indicates action eg add subtract OR DataOut is same bit width as multibit inputs DataA and DataB ALU is combinational Conditions indicate special conditions of arithmetic activity eg overflow ENGN112 L33 Arithmetic Logic Units DataA DataB Function gt Conditions DataOut Think of ALU as a number of other arithmetic and logic blocks in a single box Function selects the block November 21 2003 ALU Integrated Circuit Integrated circuit offtheshelf components Examine the functionality of this ALU chip Inputs A3 A A A Outputs A0 F3 F2 53 F F B 52 74L8332 F B 74H0352 0 Bo cN Cw OVR A 4bit input number B 4bit input number CN carry into LSB position S 3bit operation select i1puts F 4 bit output number ON carry out of MSB position OVH overflow indicator 3 EN Function Table 32 S 30 Operation Comments 0 o 0 CLEAR F3F2F1Fo 0000 O 0 1 B minus A O 1 0 A minus B N55ds 0 1 o 1 1 A plus 5 Needs cN o 1 0 0 A a B EXCIUSlVE39OH 1 0 1 A B OR 1 1 0 AB AND 1 1 1 PRESEF F3F2F1Fo 1111 Notes S inputs select operation OVR 1 for signednumber overflow b Performs 8 functions Example Determine the 74HC382 ALU out uts for the following in uts SZS So010 A3 2A1A00100 B3BZB1B00 01 and cN1 Function code indicates subtract o1oo 0001 0011 Change the select code to 101 and repeat Function code indicates OR 0100 OR 0001 0101 Synchronize ALU DataA DataB With a clock Function gt Conditions DataOut ENGN112 L33 Arithmetic Logic Units November 21 2003 Eannding the ALU Multibit ALU created by connecting carry output of loworder chip to carry In of high order B7 56 B5 B4 B3 52 B1 50 52 S180 0 Ba 82 8 Bo A3 A2 A AU 32 3150 CN Eaa 52 B180 74H0382 74H0332 CNM OVR F3 F2 F1 F0 CNM OVR F3 F2 F1 F0 27 Es 25 EA is 22 31 En Notes 21 adds Iawer order bus gzazddfgigne der blts EIght blt ALU formed from 2 fourbit ALUs 7 o ENGIN OVR at 22 Is 8bit over ow Indicator Datapath components Tristate buffer n Out If Enable asserted Out In Otherwise Out openCircuit Enable Loadable register C Ik Load Data stored on rising edge if Load is asserted eg Load 1 ENGN112 L33 Arithmetic Logic Units November 21 2003 Computation in a Typical Computer Control logic often imglemented as a finite state machine Including R Ms Datapath contains blocks such as ALUs registers tri state buffers and RAMs In a processor chip often a 5 to 1 ratio of datapath to control logic mm Cthlllullx iimniimk Conlml Datapath logic Ixlciimi lilplll lulluil gt gt mpim Lllllil uiiiii Fig 372 Control and Dalzipalli Interaction ENGIN11Z L33 Arilhmelic Lngic Llnils NnvemherZLZ Using a Datapath 0 Consider the following computation steps 1 ADD A B and put result in A 2 Subtract A B and put result in B 3 OR A B put result in A Determine va39ues for Function LoadA LoadB Repeat starting from step 1 l i LoadA LoadB V Function gt ALU ENGN112 L33 Arithmetic Logic Units November 21 2003 Modeling Control as a State Machine 0 Consider the following computation steps 1 ADD A B and put result in A 2 Subtract A B and put result in B 3 OR A B put result in A Determine va39ues for Function LoadA LoadB Repeat starting from step 1 Model control as a state machine Determine control outputs for each state ENGN112 L33 Arithmetic Logic Units November 21 2003 Modeling Control as a State Machine 0 Consider the following computation steps 1 ADD A B and put result in A 2 Subtract A B and put result in B Eatzego 3 OR A B put result in A 31 01 Repeat starting from step 1 82 10 Present State Next State Function LoadA LoadB OO O1 011 1 0 O1 10 010 O 1 10 00 101 1 0 We know how to implement this using an SOP Can we use a ROM ENGN112 L33 Arithmetic Logic Units November 21 2003 ROM Implementation of State Machine Present State Next State 00 O1 O1 10 10 CD ROM 0101110 1001001 gt 0010110 PS NS ENGN112 L33 Arithmetic Logic Units Function LoadA LoadB 011 1 O 010 O 1 101 1 0 States SO 00 S1 01 OO 82 10 O1 10 Note No minimization One line in ROM for each state i Function LoadA LoadB November 21 2003 Putting the Control and Datapath Together RCMM 0101110 00 1001001 01 gt 0010110 10 PS NS LoadA 3 Func on ENGN112 L33 Arithmetic Logic Units V ILLJ LoadB November 21 2003 What if we replaced the ROM with RAM RAM 0101110 00 Looks like software 1001001 01 gt 0010110 10 PS LoadB NS LoadA 3 V Function ALU Possible to implement different functions Program the RAM to perform different sequences ENGN112 L33 Arithmetic Logic Units November 21 2003 Summary ALU circuit can perform many functions Combinational circuit ALU chips can be combined together to form larger ALU chips Remember to connect carry out to carry in ALUs form the basis of datapaths ROMS can form the basis of control paths Combine the two together to build a computing circuit Next time more data and control paths ENGN112 L33 Arithmetic Logic Units November 21 2003

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