Class Note for ENGIN 112 at UMass(36)
Class Note for ENGIN 112 at UMass(36)
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This 16 page Class Notes was uploaded by an elite notetaker on Friday February 6, 2015. The Class Notes belongs to a course at University of Massachusetts taught by a professor in Fall. Since its upload, it has received 17 views.
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Date Created: 02/06/15
ENGIN 112 Intro to Electrical and Computer Engineering Lecture 38 Programmable Logic ELECTRICALw quot COMPUTER ENGINEERING UNIVERSITY or MASSACHUSETTS AMHERST ENGIN11Z L33 Prngrzmmzhle Lngic Decemh2r52 3 Overview Programmable logic offers designers opportunity to cus omIze chIps Programmable logic devices have a fixed logic structure Programmable array logic contain ANDOR circuits First introduced in early 1980 s Field programmable gate arrays FPGAs contain small blocks that implement truth tables First introduced in 1985 Xilinx Corporation Software used to convert user designs to programming information ENGN112 L38 Programmable Logic December 5 2003 Design Implementation Chip creation is a long and difficult process Millions of dollars required to create custom silicon Simulation synthesis fabrication lots ofjobs for eng I nee rs V gt HDL description Valld Synthesis Nethst gt Of desrgn des1gn tools it v Simulate Simulate Test bench gt RTL de gn gate level design V V Result Result Good Good Needs Needs correction correction v v Compare Fabricate No match Match 1C Fig 8 1 Process of HDL Simulation and Synthesis ENGN112 L38 Programmable Logic December 5 2003 Programmable Logic Design Generic chip created and then customized by deSIgner Programming information used Like a ROM Analogy sign making Custom sign more expensive customized by manufacturer difficult to change Sign built by consumer from individual letters less expensive not quite as nice easier to change remix letters ENGN112 L38 Programmable Logic December 5 2003 Programmable Array Logic AND gates inputs Implements sumofproducts ex Pg gct 12345678910 p 7 D1 Four external Inputs and 2 D F1 complements a x Dy Feedback path from output F1 M 39 39 J 4 Product term connections glm F2 made VIa SWltcheS 6 Df 12 7 9 D FI 13 10 11 F4 12 DJ L 14 12345678910 Fig 7 16 PAL with Four Inputs Four Outputs and Three Wide AND OR Structure ENGIN112 L38 Programmable Logic December 5 2003 Programmable Array Logic AND gates inputs Consider implementing the following expression P ijn i n1 1 2 3 4 5 6 7 8 910 1I2I339I39I2 l3 l4 14F1 1 Dy 1 7 g Note that only functions of up 6 W to three product terms can be 12 g2 implements 7 DLN Larger functions need to 8 BW F3 be chained together via the 9 feedback path 1H2 113 VF F4 14 12345678910 Fig 7 16 PAL with Four Inputs Four Outputs and Three Wide AND OR Structure ENGN112 L38 Programmable Logic December 5 2003 Reconfigurable Hardware Logic Element 4 Out UCWgt ABCD out Each logic element operates on four onebit inputs Output is one data bit Can perform y Boolean function of four inputs 224 64K functions ENGN112 L38 Programmable Logic December 5 2003 Logic Element T7 LE Each logic element outputs one data bit Interconnect programmable between elements Interconnect tracks grouped into channels ENGN112 L38 Programmable Logic December 5 2003 FPGA Architecture Issues X X X X Logic x Element X X X X Need to explore architectural issues How much functionality should go in a logic element How many routing tracks per channel Switch population ENGN112 L38 Programmable Logic December 5 2003 Translating a Design to an FPGA C program Circuit Array p A C gt B CAB CAD to translate circuit from text description to physical implementation well understood CAD to translate from C program to circuit not well understood Very difficult for application designers to successfully write high performance applications Need for design automation ENGN112 L38 Programmable Logic December 5 2003 Circuit Compilation 1 Technology Mapping fgb gt LUT quot 2 Placement LUT 7 Assign a logical LUT to a 39 physical location 3 ROUting Select wire segments And switches for l Interconnection December 5 2003 Two Bit Adder Made of Full Adders quoti I AB D Co FTA Ci S Logic synthesis tool reduces circuit to SOP form S ABCi A39B39Ci AB Ci A BCi i i Ci LUT Co Ci LUT Co ABCi A BCi AB Ci ABCi ENGN112 L38 Programmable Logic December 5 2003 Dynamic Reconfiguration gt5D ii What if I want to exchange part of the design in the device with another piece Need to create architectures and software to incrementally change designs Effectively a configuration cache ENGN112 L38 Programmable Logic December 5 2003 Xilinx XC4000 Cell W w 1 5 a S a W 1 s w E E 7 quoti F g Fquot 7 Sm 7 Bus 8 5 a in HM quot ED Fem T Mmummmw Figural Simplified Block Diagram nfxCAooo Series CLB RAM and Carry Logic functions nouhuwn EMGIMHZ m Prnummrmhle Law 24 Decenter 5 2m xawoo um xawoox 5m mu ngnmnhh am Arry XXIIJNX39 km Xilinx XC4000 Routing Small boxes represent switches T as 9 xxx qu96 aka 5amp0 ENGIMHZ us Prnurzmmzhle Lnulc Decenter 5 2m Summary Programmable logic allows for designers to easily create custom deSIgns Programmable array logic contains ANDOR structures to implement SOP equations FPGAs contain small memories and numerous wires for routing Designers create designs in Verilog Design translated to the chip via software Hands on experience in ECE353 ECE354 ENGN112 L38 Programmable Logic December 5 2003
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