Class Note for ENGIN 112 at UMass(39)
Class Note for ENGIN 112 at UMass(39)
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This 19 page Class Notes was uploaded by an elite notetaker on Friday February 6, 2015. The Class Notes belongs to a course at University of Massachusetts taught by a professor in Fall. Since its upload, it has received 17 views.
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Date Created: 02/06/15
University of Massachusetts Amherst Engin112 Lectures 3637 Programmable Logic l Maciej Ciesielski Department of Electrical and Computer Engineering 12032008 Recap from last lecture Memories 0 RAM 0 ROM 0 Programmable ROM Today s lecture PLA PAL 0 PLDS gtgt Combinational gtgt Sequential FPGAS gtgt LUTbased 12032008 Engin 112 Intro to ECE 2 Combinational PLDs Combinational Programmable Logic Device PLD 0 Convenient method for implementing combinatorial logic 0 Regular structure of AN DOR array Three possible implementations Programmable ROM PROM Fixed bl Inputs AND array r pragmmnm e gt Outputs OR array decoder Programmable Array Logic PAL programmable E Fixed Inpms AND array OR array oumS o Programmable Logic Array PLA programmable programmable AND array OR array Inputs r Outputs V 12032008 Engin 112 Intro to ECE 3 Programmable Logic Array PLA Programmable AND and OR A arrays B AND array c E generates products H 3 x w A OR array generates quot quot 2 quot x C sum of products x 3 x ac Output XOR allows H A BC inversion c on B A Av Je l What is the function of this PLA F1AB ACA BC ii F2 AC BC Programmable L inverters 12032008 Engin 112 Intro to ECE 4 Programmable Logic Array PLA Z O O O O 3 I O I 5 39 39 39 Programmable inverters 6 I O I Implement 4 F1Xyz H0356 X y z X yz xy z xyz F2Xyz 20124 7 2356 1 F2 X yz X y z X yz xy z xyz 12032008 Engin 112 Intro to ECE 5 F1 Programmable Array Logic PAL Programmable AND array and fixed OR array Section of PLA 0 Threewide AN DOR array 0 AND generates product term 0 OR generates sum Additional feedback 0 First output is fed back Limitations 0 Only three wide ANDOR 0 Not all functions can be implemented 12032008 Engin 112 Product AA39BB C C39BD39WW I V term D Lm 3 i x quot quot x A g 39 H 31rm E x J a 35 B 39 Alll fuses intact L always ll 7 H 31 9 x x C gt 10 DR 11 1 12 D L 2 x Fuse inlact Fuse blown AA39B39B39CC39DD WW Intro to ECE 6 Programmable Array Logic Implement F1Xyz 20 3 5 6 XIyIzI Xy z xyz F2Xyz 20 124 7 23 5 6 I I I xyz X y z XT X yz xy z xyz 12032008 YM 2 H Engin 112 Intro to ECE ww m3 H w2356 H 3 3 I I m6 I a W I m0 Z0356 W Y G L Z356 Sequential Programmable Devices PLDs convenient for combinatorial circuits 0 Can we design something similar for sequential circuits Inpms gt Combinational ompms circuit BaSIc sequential cnrcunt i What can we use for 0 combinatorial portion mm AND 0M Outputs PAL or FLA Flip ops 0 memory 39 Sequential programmable devices 0 Sequential programmable logic device SPLD 0 Complex programmable logic device CPLD 0 Field programmable gate array FPGA 12032008 Engin 112 Intro to ECE 8 Sequential Programmable Logic Device SPLDs are mode from macrocells 0 Contains sumof product combinatorial logic PAL 0 Contains flipflop Dtype CM OE Tristate output Macrocell Sum ofj 0 Typically products 810 per ltE DK i IC package k h V j Flipflop feedback 12032008 Engin 112 Intro to ECE 9 Complex Programmable Logic Device CPLDs for larger circuits 0 Combine multiple SPLDs 0 Switch matrix connects SPLDs m m m m lO block with tristate lO no I re Programmable switch matrix Details are hm vendorspecific Pm m 0 Altera CPLD 239 PAL or PLA structures 12032008 Engin 112 Intro to ECE 10 Field Programmable Gate Arrays Gate Array 0 An array of programmable logic function blocks 0 Gate array is manufactured ahead of time prefabricated 0 Customer programs configures the gate array gtgt provides logic functions and interconnections Field Programmable Gate Array FPGA 0 An array of identical programmable logic function blocks gtgt Each block has a fixed number of inputs k gtgt Each block is able to implement an arbitram logic function 0 Customer programs FPGA after manufacturing in field gtgt Reprogrammable Easier to debug and cheaper in smaller quantity than ASIC An alternative to ASIC 0 High production cost amortized over large quantity of chips gtgt ASIC Application Specific Integrated Circuit high volume of custom design chip gtgt FPGAs high volume of programmable flexible chips 12032008 Engin 112 Intro to ECE 11 Lookup Table based FPGA Lookup Table 0 Truth table implemented in hardware 0 Can implement arbitram function with fixed number of inputs typically 45 by programming the storage bits customizing the truth table P Read or Write Data Example F X1X2 X1X2 1 Programming bit P 2lnput LUT X1 X2 F F 01 01 01 01 V V gt X1 X2 12032008 Engin 112 Intro to ECE 12 LUT Programming Implement the following function using 3input LUT F ab ac be a b c F Programming bit LUT 12032008 Engin 112 Intro to ECE 13 Logic Element I Logic Element the basic programmable element of FPGA 0 Contains LUT lookup table Inputs CIOCk gt State Enable 12032008 Engin 112 Intro to ECE 14 FPGA Architecture Logic Element Tracks Each programmable logic element outputs one data bit 0 Interconnects are programmable between elements 0 Interconnect tracks grouped into channels 12032008 Engin 112 Intro to ECE 15 FPGA Routing I L C L C L 533 E9 Basil Logic Element Programmable routing 0 SwitchboxesS 0 IO connectors C o 1 2 o 1 2 a 5 block b c block 12032008 Engin 112 Intro to ECE 16 m e V S A G D F Engin 112 Intro to ECE Multi 12 032008 Target Architectures 39 Microprocessor Reconfigurable ASIC SW hardware HVV ASIC gives high performance at cost of inflexibility Processor is very flexible but not tuned to the appHca on Reconfigurable hardware is a nice compromise gtgt Uses CPLDs and FPGAs 12032008 Engin 112 Intro to ECE 18 Reading Assignment Read Mano 81 85 RTL 12032008 Engin 112 Intro to ECE 19
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