Class Note for ENGIN 112 at UMass(4)
Class Note for ENGIN 112 at UMass(4)
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Date Created: 02/06/15
College of Engineering University of Massachusetts Amherst ENGIN 112 Introduction to Electrical and Computer Engineering Fall 2008 Discussion A 13 Timing and Random Access Memory I Timing In circuits data are transferred from input to output via electrical currents that cause changes in voltage levels It takes some small but not zero time for currents to propagate through the devices that make up the circuits which causes some delay between the time a voltage change is applied at the input indicating new input data and the resulting change starts and is completed at the output That delay determines how rapidly the circuit is able to process data In combinational circuits with no clock two types of delay are important contamination delay denoted ted and propagation delay denoted tpd Contamination delay is the time it takes from the a change in the input to sz i39tto cause a change in the output so a change in the output does not start until ted seconds after the input change Propagation delay is the time it takes from a change in the input to the completion of the change in the output so after tpd seconds the output will not further change in response to the input change Example Suppose that we have AND gates with contamination delays 5 nsec 5 nanoseconds 5 x 10399 sec and propagation delays 10 nsec and OR gates with contamination delays 3 nsec and propagation delays 8 nsec Find the overall contamination and propagation delays for the circuit shown below X output y O 2 1 ted 3 nsec 3 nsec 6 nsec z p ted path d 10 nsec 8nsec 18 nsec Propagation delays and setup times determine the minimum required clock period that is the time from one triggering clock edge to the next the period must be long enough to allow the desired input to propagate through all circuits leading to the output flipflop plus allow for enough setup time at the output The clock frequency is defined to be 1period this is a measure of how fast the overall system is able to operate Frequency is expressed in units of Hertz Hz sec391 So for example a clock having a period of 100 nsec 1 x 10397 sec has a frequency of 11 x 107 1 x 107 Hz 10 x 106 Hz 10 megahertz 10 MHz Note that the maximum allowed clock frequency is 1minimum allowed clock period In circuits with multiple paths from input to output it is the path with the largest sum of propagation delays and output setup time that determines the maximum clock frequency Example In the circuit shown below each flipflop has propagation delay tckQ 10 nsec and setup time 2 s 2 nsec Combinational circuit 1 has a propagation delay tpm 5 nsec combinational circuit 2 has propagation delay tpd2 8 nsec and the AND gate has propagation delay tpd3 1 nsec What is the maximum possible clock frequency for the circuit D1 Q1 Input gtC Comb Circuit 1 Comb Circuit 2 3 D2 gtC Q2 Clock Output After the initial triggering clock pulse edge 1 It takes tckQ 10 nsec for the input to propagate from D1 to Q1 2 It takes tpm 5 nsec for the value at Q1 to propagate through Combinational Circuit 1 and tpd2 8 nsec for it to propagate through Combinational Circuit 2 so the inputs to the AND gate will be correct 8 nsec after Q1 is set 3 It takes tpd3 1 nsec for the AND gate inputs to propagate to D2 4 The value at D2 must be set for t8 2 nsec before the next triggering clock pulse edge So the minimum required time between clock pulse edges is 10812 21 nsec and the maximum possible clock frequency is 121 x 109 476 x 107 476 MHz One last issue in timing We must insure that there are no hold time violations at flipflop inputs that is we must make sure that the input into a flipflop does not change for at least 2 7 seconds after a triggering clock pulse edge Recall that contamination delays determine when a change will m appear at a circuit s output So we must make sure that contamination delays are such that no change will start to appear in a flipflop input for at least th seconds that is the smallest sum of contamination delays along paths into a flipflop must be 2 th Example In our previous example suppose that each flipflop has contamination delay ted 2 nsec and hold time 2 7 5 nsec Combinational circuit 1 has ted 3 nsec combinational circuit 2 has ted 4 nsec and the AND gate has ted 05 nsec Does the circuit satisfy the hold time requirements The time from when a transfer is initiated at the first flipflop on a clock pulse edge until the effects begin to appear at DZ is 2305 55 nsec path through combinational circuit 1 This is gt th 5 nsec so hold time requirements are satisfied II Memory A memory unit is a collection of cells registers that are used to store binary data During processing selected data are transferred from the memory unit where they are stored to registers in the particular processor The processing results are then transferred back into the memory unit The transfer of data out of a memory unit is called a read while the transfer of data in is called a write One type of memory unit called Random Access Memory RAM allows for both read and write operations Another type called Read Only Memory ROM allows data to be written in only once after that only read operations are allowed 80 data in ROM are stored permanently One note on logic symbols In memory operations it is common for a logic gate to have many inputs For graphical simplicity instead of drawing many lines going into the gate we usually draw a single line in with the actual input lines drawn perpendicular to that ingoing line ID I IUJIJgt For example D c B A isdrawnas I l l l gt First let s consider RAM The key requirements for RAM are that we need to be able to specify whether we want to write or read data and to specify where that is the specific memory cells the data are to be written to or read from Inside the memory data are stored as groups of bits called words An 8bit word is called a byte Typically each word consists of some fixed number of bytes for example a word may consist of 4 bytes 32 bits The memory unit stores 2quot words where k is some integer The capacity of the memory unit is usually given as the total number of bytes it can store for example a RAM that stores 228 4byte words has a capacity of 228 0 22 230 10737 x 109 bytes this is usually written as 1 GB 1 gigabyte When a write or read operation is performed One entire word is transferred into or out of RAM So A RAM that stores 2quot m byte words needs to have 1 n 8m data input lines so that a new word can be written into memory 2 n 8m data output lines so that a word can be read from memory 3 A readwrite line to specify which operation is to be performed 4 k address lines to specify which of the 2quot words is to be writtenread 5 Usually a memory enable line that enablesdisables operations on the memory unit Block symbol k address nes n data input lines l l RAM 2quot words n bitsword lt ReadWrite MemOIy enable Hl n data output lines Note Word locations are indexed by kbit binary numbers 0000 to 1111 so the bits on the address lines tell which word location is to be accessed Steps for a Write operation 1 Put the binary code for the desired word location on the address lines 2 Put the bits to be written in on the data input lines 3 Activate Write and Memory Enable inputs The bits from the data input lines will then be transferred into the register that is word location specified by the address bits Steps for a Read operation 1 Put the binary code for the desired word location on the address lines 2 Activate Read and Memory Enable inputs The bits stored in the register word location specified by the address bits are then transferred to the data output lines Action of ReadWrite and Memory Enable inputs Memory Enable ReadNVrite Operation 0 X no operation 1 0 Write 1 1 Read Timinq requirements The memory unit requires time to perform read and write operations The time required to select and read a word is called the memory access time The time required to write to a selected location is called the memory cycle time For a write operation The input lines containing the address of the selected word the data to be written Memory Enable 1 and Read Write 0 must all be held stable for a number of clock cycles that at least cover the cycle time T1 T2 T3 T1 Clock Memory address Address valid Memory enable Read Write Data input Data valid X X J X X For a read operation the address lines Memory Enable 1 and ReadWrite 1 must all be held stable for a period of time at least equal to the access time mack T1 T2 T3 T1 Mammy address MEII JIDIT 39t enable ReadlIr Write Data XData valid gtlt utput gtlt Address 1valid X One type of RAM is called static RAM SRAM it uses latches to store the data one latch per bit The basic binary cell BC for storing one bit can be represented using a D latch as follows Output Select ReadWrite ldea When Select 1 and ReadWrite0 the input bit is written into the latch the output bit is fixed at 0 When Select1 and ReadWrite1 The latch is disabled so the stored bit is unchanged the output bit the stored bit Q When Select0 the latch is disabled and the output bit is fixed at 0 Block symbol for Binary Cell Select A real SRAM binary cell is l typically constructed in CMOS with a total of six InpUt BC gt output transistors T ReadWrite o In a typical RAM there are thousands of words each consisting of some number of bytes so there are many thousands or millions of binary cells Input data i i l BC gtBC gt r gtBC gt wag gt1 Example of RAM m i i u 39 39 3 i555 f storing four 4bit mpu a y L i l 39 PgtlBClgt 1ch gtBC ner L d efcodvery i i T 39 f t d l r W T I BC gt BC ac w as gt Memory EN quot r i I F f enable 39 L g 7 Wo rd39S c A T r l L ac H L ac L BC BC J ReadWrite i J J WWW Output dam
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