Class Note for ENGIN 112 at UMass(5)
Class Note for ENGIN 112 at UMass(5)
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Date Created: 02/06/15
College of Engineering University of Massachusetts Amherst ENGIN 112 Introduction to Electrical and Computer Engineering Fall 2008 Discussion A 9 Synchronous Sequential Circuits I Enable for Combinational Circuits 1 Combinational circuits are often provided with an enable input to further control circuit operations For example consider the 3 X 8 line decoder shown last week DI X39y z39 Du X39y39 Suppose we add an enable variable w as input to each of the AND gates Then when w1 the decoder is enabled and the output is as shown in the figure But when w0 all outputs are zero L14 2 1sz D 5 xyquot DE t39yz Example application using two 3 x 8 line decoders to make a 4 x 16 line decoder output is 1 on the line that corresponds to the minterm for the values of WXyz 3x8 Decoder 1 m0 1m1 1m2 1m3 enable 3x8 Decoder enable 0m0 0m1 0m2 0m3 0m4 0m5 0 m6 0m7 A II Synchronous Sequential Circuits Sequential circuits are those in which part of the circuit s output is fed back to form part of the circuit s input The feedback path necessarily includes some delay so the same signal is not simultaneously at the input and output and data storage registers memory elements Data gt Combinational gt Data 39npUt circuit output gt Memory element E Synchronous sequential circuits have an associated clock that allows for data transfer into or out of the memory elements only at discrete points in time So the circuit performs computations on the data at times that are determined by the clock As in any circuit the output of a sequential circuit is a function of the inputs but the introduction of timing and feedback into the circuit operation both expands the types of operations the circuit can perform and complicates the circuit description and analysis In particular in describing the action of a sequential circuit that is the output that is generated at any given time we need to consider both the data input to the circuit and the state that is the binary information being stored of the memory elements Example As an example consider the circuit shown below X gt gt y Output at timei Input at FXy time i One cycle period yM lt gt Clock sngnal 1cycle delay lt memory State at time i T 1 T time output at time i1 time i1 time i time i1 As a function of the input and state y FX y7 simple expression If we try to write the output as a function ofjust the inputs Using yk FXk ym for every time k we have y FXi Yi1 F09 F094 Yi2 F09 F094 FX2 Yi3 very complicated First We will look at the memory elements that can store 1 bit 1 Latches A latch is a storage element whose operation is controlled by the clock level that is either high voltage 1 or low voltage 0 0 gt Latches are simple circuits consisting of coupled NAND or NOR gates We ll look at a few different examples i SR Latch First note that for a twoinput NOR gate if one input is set at 1 then the output is 0 no matter what the other input is For a NAND gate if one input is set at 0 then the output is 1 no matter what the other input is 1 O 0 1 X X Consider this circuit R Q T 01Q The bit stored by this latch is the value Q When the latch is acting as a storage element the inputs R and S are both 0 The stored value of Q is set by S temporarily changing either R or S but not both to 1 Say that we set S1 R0 Then and Q 1 and Q 0 This is called the set state Note that after the set state is established and we revert back to the standard inputs S0 R0 the outputs remain in the set state That is In the set state the value Q 1 is stored as long as S0 R0 Now say that we set S0 R1 Then and Q 0 and Q 1 This is called the reset state Note that after the reset state is established and we revert back to the standard inputs S0 R0 the outputs remain in the reset state That is In the reset state the value Q 0 is stored as long as S0 R0 A similar circuit can be built with NAND gates In this circuit S0 R1 sets Q1 Q 0 the set state The inputs then revert to the standard conditions of 81 R1 the circuit remains in the set state as long as we keep S1 R1 S1 R0 sets Q0 Q 1 the reset state The inputs revert to 81 R1 and the circuit remains in the reset state as long as we keep S1 R1 Since this circuit sets and resets with inputs that are the complements of those used in the NOR gate SR latch this NAND circuit latch is usually called an S R Laz ch S C S Bubbles on R inputs indicate c R o latch is S R Symbol for SR latch Symbol for SP latch o A latch can be supplied with an enable input that controls when the state can be set or reset Consider the circuit 8 X w EN enable 3Y When EN0 The inputsXand Yinto the S R latch are both 1 meaning that the state QQ will not change no matter what we set as the values of S and R that is latch operation is disabled When EN1 Note that S1R0 produces X0Y1 which in the S R latch stage generates the set state Q1Q 0 S0R1 produces X1Y0 which in the S R latch stage generates the reset state Q0Q 1 and when S0R0 produces X1Y1 which maintains the latch in whatever state it is So this overall circuit acts like an SR latch when EN1 that is it is an SR latch with enable Note that there is one problem with an SR latch We cannot allow the inputs S1R1 when the latch is enabled Why S1R1EN1 gives X0Y0 which in turn produces Q1Q 1 which can t be true the state is actually indeterminate A simple way to make sure that we never go into this disallowed state is to modify the SR latch with enable into a D latch D x EN 0 y y In this circuit D1 generates the set state Q1 and D0 generates the reset state Q0 when EN1 that is when the latch is enabled it sets QD When EN0 the latch maintains whatever state it is in o Q39 Block symbol for D latch with enable D latch EN 2 Flipflops One problem with a latch is that states are set or reset by the level of the enable input for example in a D latch the circuit is able to be set or reset as long as EN1 This can cause difficulties when a circuit needs multiple bits of memory storage because outputs of some latches become inputs that is D lines of others Then if timing is not properly synchronized intended state changes in some latches can cause unintended changes in others Example Consider the connection of D latches shown below along with their enable pulses IEN D latch O EN2 Say thatA0 and thatX1 initially then EN D latch o Q l EN1 EN1 Q is set to 1 when EN1 becomes 1 We want to store this value But before EN1 goes to zero and saves the bit Q1 EN2 goes to 1 and Xis reset to 0 this in turn causes Q to be reset to 0 EN2 A flipflop is a memory storage device that is designed so that state transitions can only happen at the positive edge or negative edge of a clock pulse rather than during the whole time that the pulse is high This lets us synchronize the timing so that we don t have inadvertent state transitions Positive pulse edge gt Negaz ive pulse edge time gt Flipflops an be constructed from D latches and logic gates The most commonly used is the D flipflop which has the following implementation D latch Y D latch D master D slave Q EN EN 0 Q 3 2 4 CLK CLK clock 1 Circuit operation 1 During time 1 CLK0 the value YYOLD is stored at the master latch output and the slave latch output Q takes the value YYOLD 2 At time 2 the enable input into the slave latch transitions to 0 and the value QYOLD is saved 3 During time 3 CLK1 Ytakes the new value YNEWD while Q maintains the value YOLD 4 At time 4 the enable input into the slave latch transitions to 1 and Q takes the new value QYNEWD So in this flipflop The value of the flipflop output stored bit Q can change only on negative edges of the clock pulses Block symbol for D flipflop Ogt CLK The bubble indicates that the dynamic input acts on negative pulse edges The gt indicates a dynamic input this denotes that the flipflop acts only during clock transitions D flipflop It is also possible to build a D flipflop that whose dynamic input is triggered by positive clock transitions this has block symbol No bubble indicates that dynamic input acts on positive pulse edges D flipflop gt CLK Positive edge triggered D flipflop S o Q39 The action of a flipflop is indicated by its characteristic equation and characteristic table The characteristic equation tells how the flipflop state after the next triggering clock transition denoted Qz 1 depends on the current input For a D flipflop the characteristic equation is Qt1 D This is also represented by the characteristic table D Qt1 O O reset 1 1 set D flipflops are most commonly used in practice because it is relatively simple to construct in CMOS However other types of flipflops can be developed T fiQfOQ Consider the Tflipflop Circuit 333 0 gt CLK D flipflop Characteristicequation Qt1 D T Ql 739Qz Characteristic table T Qt1 Qt Qt JK fliQ og Now consider the JK flipflop circuit D flipflop 3 D K gtO gt CLK Characteristic equation Qz 1 D JQz K Ql JKfIipflop characteristictable J K an o o W o 1 O reset 1 o 1 set 1 1 Qt Next week Analyze circuits that contain flipflops
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