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# Class Note for ENGIN 112 at UMass(7)

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This 11 page Class Notes was uploaded by an elite notetaker on Friday February 6, 2015. The Class Notes belongs to a course at University of Massachusetts taught by a professor in Fall. Since its upload, it has received 17 views.

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Date Created: 02/06/15
College of Engineering University of Massachusetts Amherst ENGIN 112 Introduction to Electrical and Computer Engineering Fall 2008 Discussion A 11 FSM Examples Example 1 Say that a sequence of bits arrives at some node Develop a circuit that outputs a 1 if the number of 1 s that have arrived up to the current time is even and outputs a 0 if the number is odd 1 How many states Set two states 80 to mean number of 1 s is even S7 to mean number of 1 s is odd 2 Draw state table and state diagram as a Mealy model Recall key point In a Mealy model outputs are sampled immediately before clock edge Current Current Next State Current State Input X Output y So 0 So 1 So 1 S1 0 S1 0 S1 0 S1 1 So 1 3 Assign code to represent states and draw Meay model implementation Let 0 represent 80 and 1 represent 8 jD A o D X clock gt CLK O 4 Now draw state table state diagram and implementation as a Moore Model Recall For a Moore model outputs are synchronized with clock edges 80 the input does not change the output until the next clock edge Current Current Next State Current State Input X Output y 80 0 So 1 So 1 S1 1 S1 0 S1 0 S1 1 So 0 State diagram Implementation clock gt CLK O y Example 2 Design a circuit that counts the number of 1 s in arriving bits and resets to O on every fourth 1 Use a Moore model Define states 800 811 822 833 Encode the states with 2 bits A B so SO is encoded by A0 B0 S7 is encoded by A0 B1 etc State table Current Next State Next State Output State x0 x1 OO 00 01 OO 01 O1 10 O1 1O 1O 11 1O 11 11 OO 11 State diagram To design circuit Draw Karnaugh maps for the next states Az 1 and Bz 1 AB x 00 01 11 10 O 1 T 1 1 1 Az 1AB X AXA B DA Map forAt1 AB x 00 01 11 10 O 1 1 1 1 1 Bz 1 X B XB DB Map for Bt1 Example 3 Suppose that we again want to keep a count the number of 1 s that have arrived but now we want to count up to 1023 before resetting to 0 How many states how many ipflops We have 1024 states we index these with flipflop output bits so we need ten flipflops How many rows in the state table 1024 states one current input bit so we have 2048 rows in the state table and enormous Karnaugh maps Can you think of an alternative approach using modular design Consider using full adders recall that a onebit full adder sums two input bits and a carry bit to form a sum bit and an output carry and that we can string together n full adders to make an nbit adder We want the sum bits to represent the current count of 1 s so the sum bits should be stored on flipflops When a new 1 arrives it should be summed with the stored previous sum We have 1024 states denote them 0 1 2 1023 These are encoded by strings of 10 bits state 0 is encoded as 0000000000 state 1 as 0000000001 state 1023 as 1111111111 State diagram implemented as Moore machine 1 1 a Note Outputs are also encoded with ten bits just like the states

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