Class Note for ENGIN 112 at UMass(9)
Class Note for ENGIN 112 at UMass(9)
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Date Created: 02/06/15
ENGIN112 Introduction to Electrical and Computer Engineering Fall 2003 Prof Russell Tessier Understanding Sequential Circuit Timing Perhaps the two most distinguishing characteristics of a computer are its processor clock speed and the size of its main memory While it is relatively easy to understand the concept of main memory size the number of storage bits in the computer the concept of processor clock speed is a little more dif cult to grasp In this document we will explain what is meant by sequential circuit clock speed and more importantly how to calculate it using the timing parameters of combinational and sequential circuit components I 1 lt per gt Clk Figure 1 Periodic Clock Signal As we have discussed this term edgetrigged ip ops such as the D ip op are controlled by a clock signal such as the signal labeled Clk in Figure l A clock signal is a periodic square wave which alternates between logic high 1 and logic low 0 values at predictable times The amount of time between rising clock edges is called the clock period Tim of the clock In modern computers the clock period is usually under 10 nanoseconds 10 us The inverse of the clock period T is the clock frequency 1 Since the clock is used as the control input to edge triggered ip ops the clock frequency measures how often the data is transfered or clocked into edgetriggered ip ops A bigger clock frequency indicates that data is being stored more quickly and the sequential circuit is generating results at a faster rate Typical clock frequencies for modern computer systems range from 1 megaHertz MHZ to around 5 gigaHertz GHZ 1 Timing Parameters for Combinational Logic When implemented physically combinational circuits such as AND and OR gates eXhibit certain timing characteristics When a binary value 0 or 1 is applied at the input to a combinational circuit the change at the circuit output is not instantaneous due to electrical constraints Circuit inputtooutput delay in combinational circuits can be expressed with two parameters tpd and ted de ned as follows 0 Propagation delay tpd This value indicates the amount of time needed for a change in a logic input to result in a permanent change at an output Combinational logic is guaranteed not to show any further output changes in response to an input change after tpd time units have passed Figure 2 Combinational Propagation and Contamination Delay 0 Contamination delay ted This value indicates the amount of time needed for a change in a logic input to result in an initial change at an output 1 Combinational logic is guaranteed not to show any output change in response to an input change before ted time units have passed An example of combinational propagation and contamination delay appears in Figure 2 When in put X changes the change in Y is not instantaneous The inverter output maintains its initial value until time ted has passed After this time the Y output of the inverter may be at an intermediate value for a While indicated by the crosshatched area before the nal output value is created After the propagation delay tpd the inverter output is stable and is guaranteed not to change again until another input change Combinational propagation delays are additive It is possible to determine the propagation delay of a larger combinational circuit by adding the propagation delays of the circuit components along the longest path For example the propagation delay of the combined circuit in Figure 3 is 5 ns since the longest delay from a circuit input w m y to the output 2 is the sum of the component propagation delays through gates A and B 3 ns 2 ns 5 ns The 4 ns propagation delay path through gates C and B can be ignored in determining the overall propagation delay of the circuit since it is shorter than 5 ns In contrast the determination of the contamination delay of the combined circuit requires identifying the shortest path of contamination delays from input to output In Figure 3 the contamination delay of the combined circuit is 2 ns since the shortest sum of contamination delays from an input y to an output 2 is tcdC tcdB 1 ns 1 ns 2ns Note that this value is smaller than the contamination delay path through gates A and B 2 ns lns 3 ns tcd 2ns tpd3n5 W tcd1n5 A t 2ns x W Z y C tcd 1ns tpd 2ns Figure 3 Combined Combinational Circuit Dealy 2 Timing Parameters for Sequential Logic Like combinational circuits when sequential circuits such as edgetriggered ip ops are phys ically implemented they exhibit certain timing characteristics Unlike combinational circuits these characteristics are speci ed in relation to the clock input Since ip ops only change value in response to a change in the clock value timing parameters can be speci ed in relation to the rising for positive edgetriggered or falling for negativeedge triggered clock edge The fol lowing parameters specify sequential circuit behavior Unless otherwise speci ed the following descriptions pertain to positive edgetriggered circuits Similar de nitions can be made for nega tive edgetriggered circuits 0 Propagation delay talkQ This value indicates the amount of time needed for a change in the ip opclock input eg rising edge to result in a permanent change at the ip op output Q When the clock edge arrives the D input value is transfered to output Q Note from Figure 4 that the output of the ip op may be at an intermediate value for a while indicated by the crosshatched area before the nal output value is created After talkQ the output is guaranteed not to change value again until another clock edge trigger eg rising edge arrives o Contamination delay ted This value indicates the amount of time needed for a change in the ip op clock input to result in the initial change at the ip op output Q Note from Figure 4 that the output of the ip op maintains its initial value until time ted has passed The ip op is guaranteed not to show any output change in response to an input change until after ted has passed 0 Setup time 255 This value indicates the amount of time before the clock edge that data input D must be stable As shown in Figure 4 D is stable 255 time units before the rising tcd telk m Figure 4 Setup and Hold Time for Sequential Circuits clock edge 0 Hold time 25 This value indicates the amount of time after the clock edge that data input D must be held stable As shown in Figure 4 the hold time is always measured from the rising clock edge for positive edgetriggered to a point after the edge Setup and hold times are restrictions that a ip op places on combinational or sequential circuitry that drives a ip op D input The circuit must be designed so that the D ip op input signal arrives at least 259 time units before the clock edge and does not change until at least 25 time units after the clock edge If either of these restrictions are violated for any of the ip ops in the circuit the circuit will not operate correctly These restrictions limit the maximum clock frequency at which the circuit can operate If the rising clock edges in Figure l are too close together data will not have enough time to propagate through the circuit to the ip op input and arrive 255 time units before the rising clock edge 3 Determining the Max Clock Frequency for a Sequential Circuit Most digital circuits contain both combinational components gates muxes adders etc and sequential components ip ops These components can be combined to form sequential circuits that perform computation and store results By using combinational and sequential component parameters it is possible to determine the maximum clock frequency at which a circuit will operate and generate correct results This analysis can best be examined through use of an example A sample sequential cicuit is shown in Figure 5 Before starting timing analysis consider the ow of data in this circuit in response to a rising clock tckQ 10 ns t 2ns d tckQ 1Ons t2ns tcd2quots tcd2quots th2ns tpd5ns X Y D D Q E9 D Q Out A B Clk Figure 5 An Example Sequential Circuit edge starting at ip op A 1 Following the rising clock edge on Clk a valid output appears on signal X after th 10 ns 2 A valid output Y appears at the output of inverter F tpd 5 ns after a valid X arrives at the gate 3 Signal Y is clocked into ip op B on the next rising clock edge This signal must arrive at least 259 2ns before the rising clock edge As a result the minimum clock period Tmm of the circuit is Tmm t01k7QAtpdF t5B 10713 5713 2713 17713 1 and the maximum clock frequency of the circuit is 588 MHZ Waveforms that show the determination of the minimum clock period are show in Figure 6 Since the Clk input is attached to both ip ops both will change value at the same time On each clock edge the same three steps starting from ip op A are repeated On the next edge a new value is clocked into ip op B that is a result of the previous clock edge on ip op A In a typical sequential circuit design there are often millions of ip op to ip op paths that need to be considered in calculating the maximum clock frequency This frequency must be determined by locating the longest path among all the ip op paths in the circuit For example consider the circuit shown in Figure 7 In this example there are three ip op to ip op paths op A to op Figure 6 Timing Waveforms for the Circuit in Fig 5 B op A to op C op B to op C Using an approach similar to Equation 1 the delay along all three paths are 0 TAB talkQA t9B 9 ns 2 ns 11 ns 0 TAO t01k7QA tpdZ 7550 9 118 4 118 2ns 15 IIS 0 T30 2501164203 tpdZ 2590 10 ns 4 ns 2 ns 16 ns Since the T30 is the largest of the path delays the minimum clock period for the circuit is Tmm 16 ns and the maXimum clock frequency is 625 MHZ 1 Twin 4 Validating FlipFlop Hold Time Unfortunately simply designing a circuit for a speci c maXimum clock frequency is not enough to ensure that the circuit will work properly As mentioned earlier the hold time 25 must be satis ed for each ip op input indicating that each D input cannot change until 25 time units after the clock edge Fortunately the contamination delays of combinational circuitry and ip ops help prevent ip op inputs from changing instantaneously This observation can be illustrated by reexamining Figure 5 The hold time requirement on ip op B indicates that the Y input to ip op B should not change until at least 2 ns after the rising clock edge of Clk By examining the circuit it can be seen that the earliest the signal can start to change is equal to the sum of the contamination delays of ip op A and inverter X Therefore if 5 Conclusion Sequential circuits rely on a clock signal to control the movement of system data Given a set of combinational and sequential components and their associated timing parameters it is possible to determine the maximum clock frequency that can be used with the circuit This analysis includes the examination of every ip op to ip op path in the circuit The examination includes both the propagation delays along the paths and the data setup time at the destination ip op Following the calculation of the maximum clock frequency each ip op to ip op path can be examined to ensure that ip op hold times are satis ed If the contamination delays along each path are greater than or equal to the destination ip op hold time the circuit will operate as designed References 1 S Ward and R Halstead Computation Structures McGrawHill Boston Ma 1991
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