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Week 4 CMPE 12 Notes

by: Shanee Dinay

Week 4 CMPE 12 Notes CMPE 12

Shanee Dinay
GPA 3.94
Comp Sys/Lang Lab

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About this Document

Week for Notes for Computer Systems and Assembly Languages. Topics include ISA, CPU, LC-3, Instruction Fetch, Memory, Read Write, MDR, MAR, D-Latch, R-S Latch, Control Unit, Opcodes, and Registers.
Comp Sys/Lang Lab
Class Notes
CMPE 12, Computer Language, memory, Registers, LC-3
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This 11 page Class Notes was uploaded by Shanee Dinay on Sunday February 14, 2016. The Class Notes belongs to CMPE 12 at University of California - Santa Cruz taught by Dunne,M.J. in Winter 2016. Since its upload, it has received 42 views. For similar materials see Comp Sys/Lang Lab in Computer Science and Engineering at University of California - Santa Cruz.

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Date Created: 02/14/16
Day 7 1262016 CMPE 12 Midterm Date February 16th Review on Friday the 12th 5PM hopefully Homework base 3 not base 3 turn it in either way fro credit Late Day form on Ecommons please fill out for assignments already turned in Subtraction 100 A 01 Ex 1001010 110110 010100 Ex 1010 Ex 1010 0101 0101 2 s complement 2 3 gt 2 3 no binary subtraction on 2 s complement Sign Magnitude 2 3 gt 3 2 Ex 2 3 in 2 s complement Let s use 4 bits 2 gt 0010 3 gt 0011 gt 1100 1 gt1101 0010 1101 1111 gt 1 Abstraction and Computing Systems Chapter 1 Computing machines are everywhere Distinguishing features speed cost priceperformance ease 1st very Important Idea universal computational devices Turing s Thesis every computation can be performed A Turing Machine also known as the Universal Computational Device accepts both input data and instructions 2nd Very Important Idea Problem Transformation the ultimate objective is to transform a problem expressed in natural language into electrons running around a circuit This is CS and CE Computer Architecture problems algorithms language Instruction Set Architecture Microarchitecture Circuits Devices Computer Science def the study of algorithms and data structures to solve problems abstraction do not care of how something happens work on problems Programming Flow high level language gt compiler gt assembly language gt assembler gt machine language Computer Engineering def the creative application of engineering principles and methods to the design and development of hardware and software systems Instruction Set Architecture ISA def interface between a computer s hardware and software Central Processing Unit CPU Motherboard System CPU Package SoC System on a chip Two recurring themes 1 abstraction a the notion that we can concentrate on one level of the big picture at a time 2 hardware vs software a on the other hand abstraction does not mean being clueless and levels b hardware and software are connected What is Computer Organization electronic devices gt desired behavior Out computer model for now CPU gt Memory LC3 Architecture Chapter 4 CISC vc RISC CISC Complex Instruction Set Computer lots of instruction of variable size very memory optimal typically less registers RISC Reduced Instruction Set Computer less instructions all of fixed size more registers optimized for speed LC3 Architecture very RISC 15 instruction 16bit data and address Instruction Fetch Execute Cycle in addition to input amp output a program also evaluates arithmetic amp logic functions to determine values to assign to variable determines the order of execution of the Arithmetic and Logic instructions evaluate variables and assign new values to variables Control instruction test or compare values of a variable and makes decisions about what instruction is to be next Program Counter PC basically the address at which the current executing instruction exists or the next instruction For Example PC gt ADD A B C CPE fetches instruction Branch like a goto instruction next instruction to be fetched and executed if an instruction other than the next in memory Breaking down an instruction ADD a b c opcode destination register a source registersimmediate b c The Stored Program Computer Von Neumann Model Locality of Reference techniques to reduce instruction size memory is not referenced randomly Memory 2kx m array of stored bits address contents Interface to Memory how does the processing unit get data tofrom memory MAR Memory Address Register MDR Memory Data Register To LOAD a location A To STORE a value X to a location A 1 write the data x to the MDR 2 write the address A to the MAR How this is going on RNV readwrite RNV 01 we are going to build 2 by 2 memory 2 locations and each one is 2 in size 22 t quot339 t1 n U 1 WE WE MA MR 1 393 a U 1 I WE WE MAR This is how we read memory How do we write memory perform essentially the same operation MEIt 41 E a a D i D WE l WE WE MR9 Q bad state never want 0 O to happen 1 O keeps Q Q X 1 O k D WE r V Day 8 1282016 CMPE 12 No Quiz Today RS Latch 44000 AQAQJU XOAXD DLatch is used to store memory 5 1 91 j 39 LJ JD R Di WE o 40400 I OI I E 1 D and WE gt O D and WE gt O RS Latch we want Q and 0 Trying to use DLatches to store memory RNV 01 22 A 01 Q m c u 2057 l H MAR is going to be a zero or a 1 RNV read or write flag we will always have an output if you set RNV flag to one then we would be able to change the contents of the memory 3 MAR WE WE i m Processing Unit PHDEESEIHG LIMIT Functional units ALU could have many function units multiply square root etc LC3 performs AND ADD NOT Registers small temporary storage Operands and results of functional units LC3 has eight registers R0 R7 each 16 bits wide Word Size number of bits normally processed by ALU in one instruction also width of registers Von Neumann Model Input and Output devices for getting data into and out of computer memory each device has its own interface usually a set of registers like memory s MAR and MDR LC3 supports keyboard input and monitor output keyboard data register KBDR and status and register KBSR monitor data register DDR and status register DSR Control Unit CDNT L LJINIIT I controls the execution of the program Instruction Register IR contains the current instruction Program Counter PC contains the address of the next instruction to be executed Control Unit reads an instruction from memory the instruction39s address is in the PC Instructions the instruction is the fundamental unit of work specifies two things opcode operation to be performed operands datalocations to be used for operation add r1 r2 r3 and instruction is encoded as a sequence of bits often but not always instructions have fixed lengths such as 16 or 32 bits control unit interprets instruction operation is either executed completely or not at all A computer s instructions and their formats is know as the Instruction Set Architecture ISA Ex LC3 ADD Instruction LC3 has 16bit instructions each instruction has a fourbit opcode bits 1512 LC3 has 8 registers ROR7 for temp storage sources and destination of ADD are registers Ex LC3 LDR Instruction load instruction reads data from memory base offset mode add offset to base register result is memory address load from memory address into destination register Instruction Processing slide for each setp FETCH load next instruction at address stored in PC from memory into Instruction Register IR copy contents of PC into MAR send read signal to memory copy contents of MDR into IR then increment PC so that it points to the next instruction in sequence PC becomes PC1 DECODE first identify the opcode in LC3 this is the first four bits of instruction a 4to16 decoder asserts a control line corresponding to the desired opcode depending on opcode identify other operands from the remaining bits ex for LDR last six bits is offset for ADD last three bits is source operand 2 EVALUATE ADDRESS for instructions that require memory access compute address used for access ex add offset to base register as in LDR add offset to PC add offset to zero FETCH OPERANDS obtain source operands needed to perform operation ex load data from memory LDR read data from register file EXECUTE perform the operation using the source operands ex send operands to ALU and assert ADD signal do nothing eg load and stores STORE RESULT write results to destination register or memory ex result of ADD is placed in destination register result of memory load is placed in destination register for store instruction data is stored to memory write address ot MAR data to MDR assert WRITE signal to memory Changing the Sequence of Instructions in the FETCH phase we increment the Program Counter by 1 what if we don t want to always execute the instruction that follows this one ex loop ifthen function call we need special instructions that change the contents of the PC these are thos control instructions from before jumps are unconditional they always change the PC branches are conditional they change the PC only if something is true Ex LC3 JMP set the PC to the value contained in a register This becomes the address of the next instruction to fetch Instruction Processing Summary instructions Iookjust like date it s all interpretation Three basic kinds of instructions Size basic phases of instruction processing F gtD gtED gtFO gtE gtSR Instruction Set Architecture all the programmervisible components and operations of the computers memory organization address space how many locations can be addressed addressability how many bits per location register set how many gt 8 what size gt 16 how are they used gt temp storage result of all low storage instruction set opcodes data types addressing modes most complicated Memory vs Registers memory adress space 216 locations 16bit addresses addressability 16bits Registers temp storage accessed in a single machine cycle accessing memory generally takes longer Opcodes 15 opcodes operate ADD ADD NOT data movement LD LDI LDR control BR JSRJSRR JMP Data Types 16bit 2 s complement integer Addressing Modes how is the location of an operand specified nonmemory addresses immediate register memory addresses PCrelative indirect baseoffset Operate Instructions only three operations ADD AND NOT source and destination oeprands are registers do not reference memory ADD and AND can use immediate mode where one operand is hardwired into instruction Will show dataflow diagram with each instruction NOT NOT1001DstSrc111111 ADDAND ADDOOO1DstSrc1OOOSrc2 ANDO101DstSrc1OOOSrc2 ADDOOO1DstSrc11Imm5 ANDO101DstSrc11Imm5 immediate mode if bit 5 has a 1 Using Operate Instructions with only ADD AND NOT how do we subtract R3 R1 R2 R2NOTR2 R2 R21 R3 R1 R2 how do we OR break the line change the sign use DeMorgan s R3 R1 OR R2 R1 NOTR1 R2 NOTR2 R3 R1 AND R2 R3 R3 how do initialize a register to zero R1 R1 AND O how do we copy from register to another R3 R2 R3 R2 O lt zero register called zero Data Movement Instructions Load read data from memory to register LD PCrealtice mode LDR base offset mode LDI indirect mode Addressing Modes LC3 Addressing Modes PCrelative address is a displacement from PC Indirect use PCRelative to get address from memory Base plus Offset use contents of a register as base address and add offset to find address The Solution use the 9 bits as a signed offset from the current PC 9 bits allows the offset rad to be 256 s offsets 255 LD Load Data LD O O 1 O Dst PCoffset9


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