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Class Note for COSC 6385 with Professor Gabriel at UH


Class Note for COSC 6385 with Professor Gabriel at UH

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This 8 page Class Notes was uploaded by an elite notetaker on Friday February 6, 2015. The Class Notes belongs to a course at University of Houston taught by a professor in Fall. Since its upload, it has received 18 views.

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Date Created: 02/06/15
Ill Computer Architecture COSC 6385 Memory Hierarchy Design III Edgar Gabriel Fall 2006 05 m5 Computer Armitemure i saw as Reducing cache miss penalty Five techniques Multilevel caches Critical word rst and earty restart Iill Giving priority to read misses over writes Merging write buffer Victim caches 05 m5 Computer Armitemure my Gabriel CS39UH Reducing miss rate Five techniques to reduce the miss rate Larger cache block size Larger caches Higher associativity Way prediction and pseudoassociative caches Compiler optimization cos m5 Computer Armitemure my Gabriel 3 Reducing Cache Miss penaltyrate via Parallelism Nonblocking caches Hardware prefetch of Instructions and Data Compiler controlled prefetching Nonblocking caches Allow data cache to continue to supply cache hits during a cache miss Reduces effective miss penalty Further optimization allow overlap of multiple misses Only useful if the memory system can service multiple misses Increases complexity of cache controller cos m5 Computer Armitemure my Gabriel ill Hardware prefetching Prefetch items before they are requested by the processor Eg processor prefetches two blocks on a miss assuming that the block following the missing data item will also be requested Requested block is placed in the instruction cache Prefetched block is placed in an instruction stream buffer In case of a request to the prefetched block the original cache request is cancelled by the hardware and the block is read from the stream buffer Downside wasting memory bandwidth if block is not required cos m5 Computer Armitemure my Gabriel Compilercontrolled prefetch Register prefetch load value into register Cache prefetch load data into cache Faulty and nonfaulting prefetches a nonfaulting prefetch turns into a noop in case of a virtual address faulthrotection violation cos m5 Computer Armitemure my Gabriel 3 Compilercontrolled prefetch II Example for 10 1lt3 1 l for 30 jlt1oo j i all j blj 0 bljtl 0 l l Assumptions Each element of a b are 8 byte double precision fp 8 KB direct mapped cache with 16 byte blocks Each block can hold 2 consecutive values of either a or Compiler controlled prefetching Ill No of cache misses for a Since a block contains aij aii1 every even value of will lead to a cache miss and every odd value of will be a cache hit gt 3 x 1002 150 cache misses because of a No of cache misses because of b b does not bene t from spatial locality Each element of b can be used 3 times for i012 Ignoring cache conflicts this leads to a Cache miss for b00 for i0 cache miss for every bj10 when i0 1 100 101 cache misses cbsc m5 Computer Armitemure my Gabriel 1 Compiler controlled prefetching IV Assuming that a cache miss takes 7 clock cycles Assuming that we are dealing with nonfaulting prefetches Does not prevent cache misses for the rst 7 iterations for 30 jltlOO j prefetch bj7 O prefetch aO 37 alollj bljllol blj rlMO l for 11 1lt3 1 l for 30 jltlOO j prefetch a1 37 allllj bljllol blj rlMO l cbsc m5 Computer Armitemure my Gabriel Compiler controlled prefetching V New number of cache misses 7 misses for b00 b10 in the rst loop 72 4 misses for a00 a02 in the first loop 72 4 misses for a10 a12 in the second loop 72 4 misses for a20 a22 in the second loop gt total number of misses 19 gt reducing the number of cache misses by 232 A write hint could tell the cache I need the elements of a in the cache for speeding up the writes But since I do not read the element don t bother to load the data really into the cache it will be overwritten anyway cos m5 Computer Armitemure my Gabriel 1 Reducing Hit time Small and simple caches Avoiding address translation Pipelined cache access Trace caches Small and simple caches Cache hit time depends on Comparison of the tag and compare it to the address No of comparisons having to be executed Clockcycle of the cache Onchip vs offchip caches Smaller and simpler caches are faster by nature cos m5 Computer Armitemure my Gabriel 1 Avoiding address translation Translation ofvirtual address to physical address required to access memorycaches Can a cache use virtual addresses In practice no Page protection has to be enforced even if cache would use virtual addresses Cache has to be ushed for every process switch Two processes might use the same virtual address without meaning the same physical address Adding ofa process identi er tag PID to the cache address tag would solve parts of this problem Operating systems might use different virtual addresses for the same physical address aliases Could lead to duplicate copies ofthe same data in the cache cos m5 Computer Armitemure my Gabriel Ill Pipelined cache access and trace caches Pipelined cache access Reduce latency of first level cache access by pipelining Trace caches Find a dynamic sequence of instructions to load into a instruction cache block The cache gets dynamic traces of the executed instructions of the CPU and is not bound the spatial locality in the memory Works well on taken branches Used eg by Pentium 4 cos m5 Computer Armitemure my Gabriel Memory organization How can you improve memory bandwidth Mder main memory bus Interleaved main memory Try to take advantage ofthe fact that readingwriting multiple words use multiple chips banks Banks are typically one word wide Memory interleaving tries to utilize all chips in the system Independent memory banks Allow independent access to different memory chipsbanks Multiple memory controllers allow banks to operate independently Might required separate data buses address lines Usually required by nonblocking caches cos m5 Computer Armitemure my Gabriel


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