Class Note for EECS 700 at KU
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X XILINX SpartanHE 18V FPGA Family Functional Description DSO772 v21 July 9 2003 Product Specification Architectural Description SpartanHE Array The SpartanIIE userprogrammable gate array shown in Figure 1 is composed of five major configurable elements IOBs provide the interface between the package pins and the internal logic CLBs provide the functional elements for constructing most logic Dedicated block RAM memories of 4096 bits each Clock DLLs for clockdistribution delay compensation and clock domain control Versatile multilevel interconnect structure As can be seen in Figure 1 the CLBs form the central logic structure with easy access to all support and routing struc tures The IOBs are located around all the logic and mem ory elements for easy and quick routing of signals on and off the chip Values stored in static memory cells control all the config urable logic elements and interconnect resources These values load into the memory cells on powerup and can reload if necessary to change the function of the device Each ofthese elements will be discussed in detail in the fol lowing sections lnputOutput Block The SpartanIIE IOB as seen in Figure 2 features inputs and outputs that support a wide variety of O signaling stan dards These highspeed inputs and outputs are capable of supporting various state of the art memory and bus inter faces Table 1 lists several of the standards which are sup ported along with the required reference output and termination voltages needed to meet the standard The three IOB registers function either as edgetriggered Dtype flipflops or as levelsensitive latches Each IOB has a clock signal CLK shared by the three registers and inde pendent Clock Enable CE signals for each register mm llll llll ll lll 39 Ull ll llll ll mm EEI E DDDDD DDDDD E g g DDEQDDELDD g g IDLILID DLIIJDD a 3g DDDDI DDDDD a E DDDDI DDDDD E E a DDDQDDEQDD g a DELHI DLIIJDD a g a DDDDD DDDDD a llllllllllllllll DSEITLEILEISZl 2 Figure 1 Basic SpartanHE Family FPGA Block Diagram EIEIEIEIEIEIEIEIEIEIEIEI EIEIEIEIEIEIEIEIEIEIEIEI 2003 Xilinx Inc All rights reserved All Xilinx trademarks registered trademarks patents and disclaimers are as listed at httpwwwxilinxcomllegalhtm All other trademarks and registered trademarks are the property of heir respective owners All speci cations are subject to change without notice DSO772 v21 July 9 2003 Product Specification wwwxiinxcom 18002557778 SpaitanllE 18V FPGA Family Functional Description X XILINX T l L SR Vcco D TFF Q Package P CLK CK quotquot V TCE EC OE CC lO Programmable SR 1 Bias and Package Pin 1 l ESD Network SR 0 D Q Programmable OFF Output Buffer CK Internal Reference OCE EC VCCU Programmable Delay 390 lO vREF SR I I D Q Programmable Package P IFF Input Buffer CK 7 To Next lO ICE EC To Other External VREF Inputs Notes of Bank 1 For some IIO standards D5077727017051501 Figure 2 SpartanllE InputOutput Block IOB Table 1 Standards Supported by IIO Typical Values In addition to the CLK and CE control signals the three reg lnput Output Board isters share a SetReset SR For each register this signal Ref Input Source Term can be independently configured as a synchronous Set a Volt Volt Volt Volt synchronous Reset an asynchronous Preset or an asyn IIo Standard VREF Vcco Vcco VTT chronous C39ear LVTTL 224 mA NA 33 33 WA A feature not shown in the block diagram but controlled by LVCMOSZ NA 2 5 2 5 NA the software is polarity control The input and output buffers 39 39 and all of the IOB control signals have independent polarity LVCMOS18 NA 18 18 NA controls gLESV KEG MH NA 3393 3393 NA Optional pullup and pulldown resistors and an optional 2 z weakkeeper circuit are attached to each user O pad Prior GTL 08 NA NA 12 to configuration all outputs not involved in configuration are GTL 10 NA NA 15 forced into their highimpedance state The pulldown resis HSTL Classl 0 75 NA 1 5 0 75 tors and the weakkeeper circuits are inactive but inputs 39 39 39 may optionally be pulled up The activation of pullup resis HSTL Class I 0399 NA 1395 1395 tors prior to configuration is controlled on a global basis by HSTL Class IV 09 NA 15 15 the configuration mode pins If the pullup resistors are not SSTL3 Class land II 15 NA 33 15 activated all the pins will float Consequently external SSTL2 Class I and H 1 25 NA 2 5 1 25 pullup or pulldown resistors must be provided on pins 39 39 39 required to be at a welldefined logic level priorto configura CTT 15 NA 33 15 non AGP 13932 NA 3393 NA All pads are protected against damage from electrostatic LVDSv BUS LVDS NA NA 25 NA discharge ESD and from overvoltage transients After LVPECL NA NA 33 NA configuration clamping diodes are connected to VCCO for LVTTL PCI HSTL SSTL CTT and AGP standards 2 wwwxilinxcom DSO772 v21 July 9 2003 18002557778 Prod uct Specification X XILINX SpartanIIE 18V FPGA Family Functional Description All SpartanIIE IOBs support IEEE 11491compatible boundary scan testing Input Path A buffer in the SpartanIIE IOB input path routes the input signal directly to internal logic and through an optional input flipflop An optional delay element at the Dinput ofthis flipflop elim inates padtopad hold time The delay is matched to the internal clockdistribution delay of the FPGA and when used assures that the padtopad hold time is zero Each input buffer can be configured to conform to any ofthe lowvoltage signaling standards supported In some of these standards the input buffer utilizes a usersupplied threshold voltage VREF The need to supply VREF imposes constraints on which standards can used in close proximity to each other See ll0 Banking There are optional pullup and pulldown resistors at each input for use after configuration Output Path The output path includes a 3state output buffer that drives the output signal onto the pad The output signal can be routed to the buffer directly from the internal logic or through an optional IOB output flipflop The 3state control ofthe output can also be routed directly from the internal logic orthrough a flipflip that provides syn chronous enable and disable Each output driver can be individually programmed for a wide range of lowvoltage signaling standards Each output buffer can source up to 24 mA and sink up to 48 mA Drive strength and slew rate controls minimize bus transients In most signaling standards the output high voltage depends on an externally supplied VCCO voltage The need to supply VCCO imposes constraints on which standards can be used in close proximity to each other See ll0 Bank ing An optional weakkeeper circuit is connected to each out put When selected the circuit monitors the voltage on the pad and weakly drives the pin High or Low to match the input signal lfthe pin is connected to a multiplesource sig nal the weak keeper holds the signal in its last state if all drivers are disabled Maintaining a valid logic level in this way helps eliminate bus chatter Because the weakkeeper circuit uses the IOB input buffer to monitor the input level an appropriate VREF voltage must be provided ifthe signaling standard requires one The pro vision of this voltage must comply with the IO banking rules 0 Banking Some of the IO standards described above require VCCO andor VREF voltages These voltages are externally sup plied and connected to device pins that serve groups of IOBs called banks Consequently restrictions exist about which IO standards can be combined within a given bank Eight IO banks result from separating each edge of the FPGA into two banks see Figure 3 The pinout tables show the bank affiliation of each IO see SpartanHE Pinout Tables Module 4 Each bank has multiple VCCO pins which must be connected to the same voltage Voltage requirements are determined by the output standards in use Bank 0 V V Bank 1 l i GCLK3 GCLK2 i m m m m SpartanIIE Device O 0 i i 3 GCLKI GCLKO 3 Bank 5 A A Bank 4 DSEI77727EI27EI515EII Figure 3 SpartanIIE I0 Banks In the TQ144 and PQ208 packages the eight banks have VCCO connected together Thus only one VCCO level is allowed in these packages although different VREF values are allowed in each ofthe eight banks Within a bank standards may be mixed only ifthey use the same VCCO Compatible standards are shown in Table 2 GTL and GTL appear under all voltages because their opendrain outputs do not depend on VCCO Note that VCCO is required for most output standards and for LVTTL LVCMOS and PCI inputs Table 2 Compatible Standards Vcco Compatible Standards 33V PCI LVTTL SSTL3 I SSTL3 II CTT AGP LVPECL GTL GTL 25V SSTL2 I SSTL2 II LVCMOSZ LVDS Bus LVDS GTL GTL 18V LVCM0818GTLGTL 15V HSTL I HSTL III HSTL IV GTL GTL Some input standards require a usersupplied threshold voltage VREF In this case certain userIO pins are auto matically configured as inputs for the VREF voltage About one in six ofthe IO pins in the bank assume this role DSO772 v21 July 9 2003 Product Specification wwwxilinxcom 3 18002557778 SpartanIIE 18V FPGA Family Functional Description X XILINX VREF pins within a bank are interconnected internally and consequently only one VREF voltage can be used within each bank AII VREF pins in the bank however must be con nected to the external voltage source for correct operation In a bank inputs requiring VREF can be mixed with those that do not but only one VREF voltage may be used within a bank The V000 and VREF pins for each bank appear in the device pinout tables Within a given package the number of VREF and VCCO pins can vary depending on the size of device In larger devices more IO pins convert to VREF pins Since these are always a superset of the VREF pins used for smaller devices it is possible to design a PCB that permits migration to a larger device AII VREF pins forthe largest device anticipated must be connected to the VREF voltage and not used for IO Table 3 HO Banking FT256 F6456 Package TQ144 P0208 F6676 VCCO Banks Interconnected as 1 8 independent VREF Banks 8 independent 8 independent See Xilinx Application Note XAPP179 for more information on IO resources Hot Swap Hot Insertion Hot Socketing Support The IO pins support hot swap also called hot insertion and hot socketing and are considered CompactPCI Friendly according to the PCI Bus v22 Specification Con sequently an unpowered SpartanIIE FPGA can be plugged directly into a powered system or backplane with out affecting or damaging the system or the FPGA The hot swap functionality is built into every XC2S150E XC2S400E and XC2S600E device All other SpartanIIE devices built after Product Change Notice PCN200205 also include hot swap functionality To support hot swap SpartanIIE devices include the follow ing IO features Signals can be applied to SpartanIIE IO pins before powering the FPGA s VCCINT or VCCO supply inputs SpartanIIE IO pins are highimpedance ie threestated before and throughout the powerup and configuration processes when employing a configuration mode that does not enable the preconfiguration weak pullup resistors see Table 9 page 13 There is no current path from the IO pin back to the VCCINT or VCCO voltage supplies SpartanIIE FPGAs are immuneto latchup during hot swap Once connected to the system each pin adds a small amount of capacitance CIN Likewise each IO consumes a small amount of DC current equivalent to the input leak age specification IL There also may be a small amount of temporary AC current IHSPO when the pin input voltage exceeds VCCO plus 04V which lasts less than 10 ns A weakkeeper circuit within each userIO pin is enabled during the last frame of configuration data and has no noticeable effect on robust system signals driven by an active driver or a strong pullup or pulldown resistor Undriven or floating system signals may be affected The specific effect depends on how the IO pin is configured UserIO pins configured as outputs or enabled outputs have a weak pullup resistor to VCCO during the last config uration frame UserIO pins configured as inputs or bidirec tional IOs have weak pulldown resistors The weakkeeper circuit turns off when the DONE pin goes High provided that it is not used in the configured application Configurable Logic Block The basic building block of the SpartanIIE CLB is the logic cell LC An LC includes a 4input function generator carry logic and storage element The output from the function generator in each LC drivesthe CLB output orthe D input of the flipflop Each SpartanIIE CLB contains four LCs orga nized in two similar slices a single slice is shown in Figure 4 In addition to the four basic LCs the SpartanIIE CLB con tains logic that combines function generators to provide functions of five or six inputs LookUp Tables SpartanIIE function generators are implemented as 4input lookup tables LUTs In addition to operating as a function generator each LUT can provide a 16 x 1bit synchronous RAM Furthermore the two LUTs within a slice can be com bined to create a 16 x 2bit or 32 x 1bit synchronous RAM or a 16 x 1bit dualport synchronous RAM The SpartanIIE LUT can also provide a 16bit shift register that is ideal for capturing highspeed or burstmode data This mode can also be used to store data in applications such as Digital Signal Processing Storage Elements Storage elements in the SpartanIIE slice can be configured either as edgetriggered Dtype flipflops or as levelsensi tive latches The D inputs can be driven either by function generators within the slice or directly from slice inputs bypassing the function generators In addition to Clock and Clock Enable signals each slice has synchronous set and reset signals SR and BY SR forces a storage element into the initialization state speci fied for it in the configuration BY forces it into the opposite state Alternatively these signals may be configured to operate asynchronously AII control signals are independently invertible and are shared by the two flipflops within the slice 4 wwwxilinxcom 18002557778 DSO772 v21 July 9 2003 Prod uct Specification X XILINX SpartanIIE 18V FPGA Family Functional Description COUT YB Y G4 l4 LookUp D YQ 33 I3 Tab39e Carry O and CK G2 47 l2 Control Logic 7 EC G1 777 l1 F5N BY k SR XB i x F4 LookUp D XQ F3 393 Table Carry o and CK F2 47m Control Logic F EC F1 7TH BX CIN CLK CE DSDDLDAiDQMDD Figure 4 SpartanIIE CLB Slice two identical slices in each CLB Additional Logic The F5 multiplexer in each slice combines the function gen erator outputs Figure 5 This combination provides either a function generator that can implement any 5input func tion a 41 multiplexer or selected functions of up to nine inputs Similarly the F6 multiplexer combines the outputs of all four function generators in the CLB by selecting one of the two F5multiplexer outputs This permits the implementation of any 6 input function an 81 multiplexer or selected func tions of up to 19 inputs DSO772 v21 July 9 2003 Product Specification 1800 2557778 wwwxiinxcom SpartanIIE 18V FPGA Family Functional Description X XILINX DSD77727D571115D1 Figure 5 F5 and F6 Multiplexers Each CLB has four direct feedthrough paths one per LC These paths provide extra data input lines or additional local routing that does not consume logic resources Arithmetic Logic Dedicated carry logic provides fast arithmetic carry capabil ity for highspeed arithmetic functions The SpartanHE CLB supports two separate carry chains one per slice The height ofthe carry chains is two bits per CLB The arithmetic logic includes an XOR gate that allows a 1bit full adder to be implemented within an LC In addition a dedicated AND gate improves the efficiency of multiplier implementations The dedicated carry path can also be used to cascade func tion generators for implementing wide logic functions BUF Ts Each SpartanHE CLB contains two 3state drivers BUFTs that can drive onchip busses The IOBs on the left and right sides can also drive the onchip busses See Dedicated Routing page 8 Each SpartanHE BUFT has an indepen dent 3state control pin and an independent input pin The 3state control pin is an activeLow enable T When all BUFTs on a net are disabled the net is High There is no need to instantiate a pullup unless desired for simulation purposes Simultaneously driving BUFTs onto the same net will not cause contention f driven both High and Low the net will be Low Block RAM SpartanHE FPGAs incorporate several large block RAM memories These complement the distributed RAM LookUp Tables LUTs that provide shallow memory struc tures implemented in CLBs Block RAM memory blocks are organized in columns Most SpartanHE devices contain two such columns one along each vertical edge The XC2S400E has four block RAM col umns and the XC2S600E has six block RAM columns These columns extend the full height of the chip Each memory block is four CLBs high and consequently a SpartanHE device 16 CLBs high will contain four memory blocks per column and a total of eight blocks Table 4 SpartanIIE Block RAM Amounts SpartanIIE Total Block RAM Device of Blocks Bits XCZSSOE 8 32K XCZS100E 10 40K XCZS150E 12 48K XCZSZOOE 14 56K XCZS300E 16 64K XCZS400E 40 160K XCZS600E 72 288K Each block RAM cell as illustrated in Figure 6 is afully syn chronous dualported 4096bit RAM with independent con trol signals for each port The data widths of the two ports can be configured independently providing builtin buswidth conversion RAMB4SS 7WEA iENA 7 RSTA DOA0 7 CLKA ADD0 DA0 l I 7 WEB 7 ENE 7 RSTB 7 CLKB ADDRB0 DB0 DOB0 DSEIEILEIEJIEEHEIEI Figure 6 DualPort Block RAM 6 wwwxilinxcom 18002557778 DSO772 v21 July 9 2003 Prod uct Specification ZXILINX SpartanIIE 18V FPGA Family Functional Description Table 5 shows the depth and width aspect ratios for the block RAM Table 5 Block RAM Port Aspect Ratios Width Depth ADDR Bus Data Bus 1 4096 ADDRlt1120gt DATAltOgt 2 2048 ADDRlt1020gt DATAlt1Ogt 4 1024 ADDRlt92Ogt DATAlt320gt 8 512 ADDRlt820gt DATAlt7Ogt 16 256 ADDRlt720gt DATAlt1520gt The SpartanIIE block RAM also includes dedicated routing to provide an efficient interface with both CLBs and other block RAMs See Xilinx Application Note XAPP173 for more information on block RAM Programmable Routing It is the longest delay path that limits the speed of any design Consequently the SpartanIIE routing architecture and its placeandroute software were defined jointly to min imize longpath delays and yield the best system perfor mance The joint optimization also reduces design compilation times because the architecture is softwarefriendly Design cycles are correspondingly reduced due to shorter design iteration times The software automatically uses the best available routing based on user timing requirements The details are pro vided here for reference Local Routing The local routing resources as shown in Figure 7 provide the following three types of connections Interconnections among the LUTs flipflops and General Routing Matrix GRM described below Internal CLB feedback paths that provide highspeed connections to LUTs within the same CLB chaining them together with minimal routing delay Direct paths that provide highspeed connections between horizontally adjacent CLBs eliminating the delay ofthe GRM To Adjacent GRM To AdjacenH h lt gtTo Adjacent GRM GRM GRM To Adjacent GRM Direct Connection Direct To Adjacent CLB Connection CLB To Adjacent CLB DSEIEILEIEJBZBEIEI Figure 7 SpartanIIE Local Routing General Purpose Routing Most SpartanIIE signals are routed on the general purpose routing and consequently the majority of interconnect resources are associated with this level of the routing hier archy The general routing resources are located in horizon tal and vertical routing channels associated with the rows and columns of CLBs The generalpurpose routing resources are listed below Adjacent to each CLB is a General Routing Matrix GRM The GRM isthe switch matrix through which horizontal and vertical routing resources connect and is also the means by which the CLB gains access to the general purpose routing 24 singlelength lines route GRM signals to adjacent GRMs in each of the four directions 96 buffered Hex lines route GRM signals to other GRMs six blocks away in each one of the four directions Organized in a staggered pattern Hex lines may be driven only at their endpoints Hexline signals can be accessed either at the endpoints or at the midpoint three blocks from the source One third of the Hex lines are bidirectional while the remaining ones are unidirectional 12 Longlines are buffered bidirectional wires that distribute signals across the device quickly and efficiently Vertical Longlines span the full height of the device and horizontal ones span the full width ofthe device 0 Routing SpartanIIE devices have additional routing resources around their periphery that form an interface between the CLB array and the IOBs This additional routing called the VersaRingTM routing facilitates pinswapping and pinlock ing such that logic redesigns can adapt to existing PCB lay outs Timetomarket is reduced since PCBs and other system components can be manufactured while the logic design is still in progress DSO772 v21 July 9 2003 Product Specification wwwxilinxcom 7 18002557778 SpartanIIE 18V FPGA Family Functional Description X XILINX Dedicated Routing Some classes of signal require dedicated routing resources to maximize performance In the SpartanIIE architecture dedicated routing resources are provided for two classes of Horizontal routing resources are provided for onchip 3state busses Four partitionable bus lines are provided per CLB row permitting multiple busses within a row as shown in Figure 8 Two dedicated nets per CLB propagate carry signals signal vertically to the adjacent CLB i i i j 239 i 3 St t ae Vii g H i Lines CLB CLB CLB CLB DSEIEILEITJBEIEEIEI Figure 8 BUFT Connections to Dedicated Horizontal Bus Lines Global Routing selected either from these pads or from signals in the gen Global Routing resources distribute clocks and other sig nals with very high fanout throughout the device Spar tanIIE devices include two tiers of global routing resources referred to as primary and secondary global routing resources The primary global routing resources are four dedicated global nets with dedicated input pins that are designed to distribute highfanout clock signals with minimal skew Each global clock net can drive all CLB IOB and block RAM clock pins The primary global nets may only be driven by global buffers There are four global buffers one for each global net The secondary global routing resources consist of 24 backbone lines 12 across the top of the chip and 12 across the bottom From these lines up to 12 unique signals per column can be distributed via the 12 Ionglines in the column These secondary resources are more flexible than the primary resources since they are not restricted to routing only to clock pins Clock Distribution The SpartanIIE family provides highspeed lowskew clock distribution through the primary global routing resources described above A typical clock distribution net is shown in Figure 9 Four global buffers are provided two at the top center ofthe device and two at the bottom center These drive the four primary global nets that in turn drive any clock pin Four dedicated clock pads are provided one adjacent to each of the global buffers The input to the global buffer is eral purpose routing Global Clock Rows Global Clock GCLKPAD3 GCLKPADZ GCLKBUF3 GCLKBUF2 Column 4 Global Clock Spine GCLKBUF1 GCLKBUFO GCLKPAD1 GCLKPADO DSEIEILEIEJIEEITEIEI Figure 9 Global Clock Distribution Network DelayLocked Loop DLL Associated with each global clock input buffer is a fully digi tal DelayLocked Loop DLL that can eliminate skew between the clock input pad and internal clockinput pins throughout the device Each DLL can drive two global clock networks The DLL monitors the input clock and the distrib uted clock and automatically adjusts a clock delay element Figure 10 Additional delay is introduced such that clock edges reach internal flipflops exactly one clock period after they arrive at the input This closedloop system effectively eliminates clockdistribution delay by ensuring that clock 8 wwwxiinxcom 18002557778 DSO772 v21 July 9 2003 Prod uct Specification X XILINX SpartanHE 18V FPGA Family Functional Description edges arrive at internal flipflops in synchronism with clock edges arriving at the input Clock Distribution Network Variable CLKOUT CLKIN Delay Line 05077727107070203 Figure 10 DelayLocked Loop Block Diagram In addition to eliminating clockdistribution delay the DLL provides advanced control of multiple clock domains The DLL provides four quadrature phases of the source clock can double the clock or divide the clock by 15 2 25 3 4 5 8 or 16 The phaseshifted output have optional dutycycle correction Figure 11 0 90 180 270 0 t 90 180 270 CLKIN CLK2X CLKDVDVDE2 DLL can delay the completion of the configuration process until after it has achieved lock Ifthe DLL uses external feed back apply a reset after startup to ensure consistent lock ing to the external signal See Xilinx Application Note XAPP174 for more information on DLLs Boundary Scan SpartanIIE devices support all the mandatory bound aryscan instructions specified in the IEEE standard 11491 A Test Access Port TAP and registers are provided that implement the EXTEST INTEST SAMPLEPRELOAD BYPASS IDCODE and HIGHZ instructions The TAP also supports two USERCODE instructions internal scan chains and configurationreadback ofthe device The TAP uses dedicated package pins that always operate using LVTTL For TDO to operate using LVTTL the V000 for Bank 2 must be 33V Otherwise TDO switches railtorail between ground and VCCO The boundaryscan input pins TDI TMS TCK do not have a VCCO requirement and oper ate with either 25V or 33V input signalling levels Boundaryscan operation is independent of individual IOB configurations and unaffected by package type All IOBs including unbonded ones are treated as independent 3state bidirectional pins in a single scan chain Retention of the bidirectional test capability after configuration facilitates the testing of external interconnections Tabe6 lists the boundaryscan instructions supported in SpartanIIE FPGAs Internal signals can be captured during CLKDV i i i i i 39 EXTEST by connecting them to unbonded or unused IOBs i i i I I I They may also be connected to the unused outputs of IOBs DUTycycEcoRRECT0NFALSE defined as unidirectional input pins CLKO I Table 6 BoundaryScan Instructions CLKQQ I I BoundaryScan Binary Command Code40 Description CLK130 i I EXTEST 00000 Enables boundaryscan CLK270 I I L EXTEST operation SAMPLE 00001 Enables boundaryscan DUTYCYCLECORRECTIONTRUE PRELOAD SAMPLEPRELOAD CLKO operation CLKQQ USER1 00010 Access userdefined register 1 CWBO USER2 00011 Access userdefined CLK270 register 2 CFGOUT 00100 Access the 327077092599 configuration bus for Figure 11 DLL Output Characteristics Readback CFGN 00101 Access the The DLL also operates as a clock mirror By driving the out configuration bus for put from a DLL offchip and then back on again the DLL can Configuration be used to deskew a board level clock among multiple Spar INTEST 00111 Enables boundaryscan tam deV39CeS INTEST operation In order to guarantee thatthe system clock is operating cor rectly prior to the FPGA starting up after configuration the DSO772 v21 July 9 2003 wwwxilinxcom 9 Product Specification 18002557778 SpartanIIE 18V FPGA Family Functional Description X XILINX Table 6 BoundaryScan Instructions Continued The public boundaryscan instructions are available priorto Boundary3can Binary configuration except for DSER1 and USIER2 After configu COmmand c de4o Description ratioG tllzieRguoblgEinsttructions rehlaIIn Lailablet ogetherWIth any ins rucionsinsa e uring econ igura USERCODE 01000 Enables Sh39 m 0L tion While the SAMPLEPRELOAD and BYPASS instruc USER code tions are available during configuration it is recommended 39DCODE 01001 Enables Sh39 39ng OUt Of that boundaryscan operations not be performed during this D cede transitional period HIGHZ 01010 D39sables OUtPUt p39ns In addition to the test instructions outlined above the Wh39le enab39mFJ the boundaryscan circuitry can be used to configure the Bypass Reg39Ster FPGA and also to read back the configuration data JSTART 01100 CIOCk the StaLt39Up To facilitate internal scan chains the User Register provides Sje iueg EWTe K three outputs Reset Update and Shift that represent the ar up IS corresponding states in the boundaryscan internal state BYPASS 11111 Enables BYPASS machine RESERVED A Other Xllinx reserved Figure 12 is a diagram of the SpartanIIE family boundary COdeS 39nStrUCt39onS scan logic It includes three bits of Data Register per IOB the IEEE 11491 Test Access Port controller and the Instruction Registerwith decodes DATA IN IOBT L I 1 5d J D O D O P P P P P of ICE IOB IOB IOB IOB 39 H H LE i IOB ICE 1 777777777777777J 7777777777 W D O D O i IOB IOB 43 By E i IOB IOB IOBI g I IOB ICE 4 in d L i IOB ICE 1 D o D o I IOB IOB i H F LE l 0 4 CF 3903 Bypass 3903 IOB39Q E 7 Register IOBJ l I 7 0 TDI Instruction Register X 0 D O D O l r7 If LE 7777777777777 7 1 Ed D O D O 0 p7 7 LE 1 IOB 0 DATAOUT UPDATE EXTEST SHIFT CLOCK DATA DSEIEILEIBjIBZBEIEI Figure 12 SpartanIIE Family Boundary Scan Logic 10 wwwxiinxcom DSO772 v21 July 9 2003 18002557778 Prod uct Specification X XILINX SpartanIIE 18V FPGA Family Functional Description Bit Sequence The bit sequence within each IOB is In Out 3State The inputonly pins contribute only the In bit to the boundary scan IO data register while the outputonly pins contributes all three bits From a cavityup view of the chip as shown in the FPGA Editor starting in the upper right chip corner the boundary scan dataregister bits are ordered as shown in Figure 13 BSDL Boundary Scan Description Language files for SpartanIIE family devices are available on the Xilinx web site at httDIlwwwxilinxcomlsupportlsw bsdlhtm SpartanIIE boundary scan IDCODE values are shown in Table 7 Table 7 SpartanIIE IDCODE Values Bit 0 TDO end TDOT Bit 1 TD00 Bit 2 Topedge IOBs Right to Lelt Le edge IOBs Top to Bottom MODEJ Bottomedge IOBs Le to Right Rightedge IOBs Bottom to Top TD39 end BSCANTUPD DSEIEILIELEIBZBEIEI Figure 13 Boundary Scan Bit Sequence IDCODE Device Version Family Array Size Manufacturer Required XC250E XXXX 0000 101 0 0001 0000 0000 1001 001 1 XC2100E XXXX 0000 101 0 0001 0100 0000 1001 001 1 XC2150E XXXX 0000 101 0 0001 1000 0000 1001 001 1 XC2200E XXXX 0000 101 0 0001 1100 0000 1001 001 1 XC2300E XXXX 0000 101 0 0010 0000 0000 1001 001 1 XC2400E XXXX 0000 101 0 0010 1000 0000 1001 001 1 XCZSGOOE XXXX 0000 101 0 0011 0000 0000 1001 001 1 Development System SpartanIIE FPGAs are supported by the Xilinx ISE Foun dation and Alliance CAE tools The basic methodology for SpartanIIE design consists of three interrelated steps design entry implementation and verification Industrystandard tools are used for design entry and simu lation while Xilinx provides proprietary architecturespecific tools for implementation The Xilinx development system is integrated under the Xilinx Project Navigatorsoftware providing designers with a common user interface regardless of their choice of entry and verification tools The software simplifies the selection of implementation options with pulldown menus and onIine help Application programs ranging from schematic capture to placement and routing can be accessed through the soft ware The program command sequence is generated prior to execution and stored for documentation Several advanced software features facilitate SpartanIIE design CORE GeneratorTM functions for example include macros with relative location constraints to guide their placement They help ensure optimal implementation of common functions For HDL design entry the Xilinx FPGA development system provides interfaces to several synthesis design environ ments A standard interfacefile specification Electronic Design Interchange Format EDIF simplifies file transfers into and out of the development system SpartanIIE FPGAs are supported by a unified library of standard functions This library contains over 400 primitives and macros ranging from 2input AND gates to 16bit accu mulators and includes arithmetic functions comparators counters data registers decoders encoders IO functions latches Boolean functions multiplexers shift registers and barrel shifters DSO772 v21 July 9 2003 Product Specification wwwxilinxcom 11 18002557778 SpartanHE 18V FPGA Family Functional Description X XILINX The design environment supports hierarchical design entry with highlevel designs that comprise major functional blocks while lowerlevel designs define the logic in these blocks These hierarchical design elements are automati cally combined by the implementation tools Different design entry tools can be combined within a hierarchical design thus allowing the most convenient entry method to be used for each portion ofthe design Design Implementation The placeandroute tools automatically provide the imple mentation flow described in this section The partitioner takes the EDIF netlist forthe design and mapsthe logic into the architectural resources of the FPGA CLBs and IOBs for example The placerthen determinesthe best locations for these blocks based on their interconnections and the desired performance Finally the router interconnects the blocks The algorithms support fully automatic implementation of most designs For demanding applications however the user can exercise various degrees of control over the pro cess User partitioning placement and routing information is optionally specified during the designentry process The implementation of highly structured designs can benefit greatly from basic floorplanning The implementation software incorporates timingdriven placement and routing Designers specify timing require ments along entire paths during design entry The timing path analysis routines then recognize these userspecified requirements and accommodate them Timing requirements are entered in a form directly relating to the system requirements such as the targeted clock fre quency or the maximum allowable delay between two reg isters In this way the overall performance of the system along entire signal paths is automatically tailored to usergenerated specifications Specific timing information for individual nets is unnecessary Design Verification In addition to conventional software simulation FPGA users can use incircuit debugging techniques Because Xilinx devices are infinitely reprogram mable designs can be veri fied in real time without the need for extensive sets of soft ware simulation vectors The development system supports both software simulation and incircuit debugging techniques For simulation the system extracts the postlayout timing information from the design database and backannotates this information into the netlist for use by the simulator Alternatively the user can verify timingcritical portions of the design using the static timing analyzer For incircuit debugging Xilinx offers a download and read back cable which connects the FPGA in the target system to a PC or workstation After downloading the design into the FPGA the designer can singlestep the logic readback the contents of the flipflops and so observe the internal logic state Simple modifications can be downloaded into the system in a matter of minutes Configuration Configuration is the process by which the bitstream of a design as generated by the Xilinx development software is loaded into the internal configuration memory of the FPGA SpartanIIE devices support both serial configuration using the masterslave serial and JTAG modes as well as bytewide configuration employing the Slave Parallel mode Configuration File SpartanIIE devices are configured by sequentially loading frames of data that have been concatenated into a configu ration file Tabe8 shows how much nonvolatile storage space is needed for SpartanIIE devices It is important to note that while a PROM is commonly used to store configuration data before loading them into the FPGA it is by no means required Any ofa number of differ ent kinds of under populated nonvolatile storage already available either on or offthe board for example hard drives FLASH cards and so on can be used Table 8 SpartanHE Configuration File Size Device Configuration File Size Bits XC2S50E 630048 XC2S100E 863840 XC2S150E 1134496 XC2S200E 1442016 XC2S300E 1875648 XC2S400E 2693440 XC2S600E 3961632 Modes SpartanIIE devices support the following four configuration modes Slave Serial mode Master Serial mode Slave Parallel mode Boundaryscan mode The Configuration mode pins M2 M1 M0 select among these configuration modes with the option in each case of having the IOB pins either pulled up or left floating prior to configuration The selection codes are listed in Table 9 Configuration through the boundaryscan port is always available independent of the mode selection Selecting the boundaryscan mode simply turns offthe other modes The three mode pins have internal pullup resistors and default to a logic High if left unconnected 12 wwwxilinxcom 1800 2557778 DSO772 v21 July 9 2003 Prod uct Specification X XILINX SpartanIIE 18V FPGA Family Functional Description Table 9 Configuration Modes Preconfiguration CCLK Configuration Mode Pullups M0 M1 M2 Direction Data Width Serial DOUT Master Serial mode No 0 0 0 Out 1 Yes Yes 0 0 1 Slave Parallel mode Yes 0 1 0 In 8 No SelectMAP No 0 1 1 BoundaryScan mode Yes 1 0 0 NA 1 No No 1 0 1 Slave Serial mode Yes 1 1 0 In 1 Yes No 1 1 1 Signals Initiating configuration There are two kinds of pins that are used to configure SpartanIIE devices Dedicated pins perform only specific configurationrelated functions the other pins can serve as general purpose IOs once user operation has begun The dedicated pins comprise the mode pins M2 M1 M0 the configuration clock pin CCLK the PROGRAM pin the DONE pin and the boundaryscan pins TDI TDO TMS TOK Depending on the selected configuration mode CCLK may be an output generated bythe FPGA or may be generated externally and provided to the FPGA as an input Note that some configuration pins can act as outputs For correct operation these pins require a VCCO of 33V to drive an LVTTL signal or 25V to drive an LVOMOS signal All the relevant pins fall in banks 2 or3 The E and WRITE pins for Slave Parallel mode are located in bank 1 For a more detailed description than that given below see DSO774 SpartanHE 18V FPGA Family Pinout Tables and XAPP176 Spartanll FPGA Series Con guration and Readback The Process The sequence of steps necessary to configure SpartanIIE devices are shown in Figure 14 The overall flow can be divided into three different phases Configuration memory clear Loading data frames Startup The memory clearing and startup phases are the same for all configuration modes however the steps for the loading of data frames are different Thus the details for data frame loading are described separately in the sections devoted to each mode Initiating Con guration There are two different ways to initiate the configuration pro cess applying power to the device or asserting the PRO GRAM input Configuration on powerup occurs automatically unless it is delayed by the user as described in a separate section below The waveform for configuration on powerup is shown in DSO773 SpartanHE 18V FPGA Family DC and Switching Characteristics Before configuration can begin VCCO Bank 2 must be greater than 10V Furthermore all VCCINT power pins must be connected to a 18V supply For more information on delaying configuration see Clearing Configuration Memory page 14 Once in user operation the device can be reconfigured simply by pulling the PROGRAM pin Low The device acknowledgesthe beginning ofthe configuration process by driving DONE Low then entersthe memoryclearing phase DSO772 v21 July 9 2003 Product Specification wwwxilinxcom 13 18002557778 SpartanIIE 18V FPGA Family Functional Description X XILINX Con guration at Powerup Con guration During User Opera ion User Pulls PROGRAM Low F PGA Drives W and DONE Low Clear Delay con guratlon Con guration Memory UserHolding PROGRAM Low Delay Con guration FPGA Samples Mode Pins l Load Con guration Data Frames l No FP Drives INIT Low Abort Startup Yes Startup Sequence FPGA Drives DONE High Activates Os Releases GSR net User Operation nsnmmmiam Figure 14 Configuration Flow Diagram Clearing Con guration Memory The device indicates that clearing the configuration memory is in progress by driving INIT Low Delaying Configuration At this time the user can delay configuration by holding either PROGRAM or W Low which causes the device to remain in the memory clearing phase Note that the bidirec tional W line is driving a Low logic level during memory clearing Thus to avoid contention use an opendrain driver to keep W Low With no delay in force the device indicates that the memory is completely clear by driving INIT High The FPGA samples its mode pins on this LowtoHigh transition Loading Con guration Data Once W is High the user can begin loading configuration data frames into the device The details of loading the con figuration data are discussed in the sections treating the configuration modes individually The sequence of opera tions necessary to load configuration data using the serial modes is shown in Figure 16 Loading data using the Slave Parallel mode is shown in Figure 19 page 19 CRC Error Checking After the loading of configuration data a CRC value embed ded in the configuration file is checked against a CRC value calculated within the FPGA If the CRC values do not match the FPGA drives W Low to indicate that an error has occurred and configuration is aborted Note that attempting to load an incorrect bitstream causes configura tion to fail and can damage the device To reconfigure the device the PROGRAM pin should be asserted to reset the configuration logic Recycling power also resets the FPGA for configuration See Clearing Con figuration Memory 5 tartup The startup sequence oversees the transition of the FPGA from the configuration state to full user operation A match of CRC values indicating a successful loading ofthe config uration data initiates the sequence 14 wwwxilinxcom 18002557778 DSO772 v21 July 9 2003 Prod uct Specification X XILINX SpaitanllE 18V FPGA Family Functional Description During startup the device performs four operations 1 The assertion of DONE The failure of DONE to go High may indicate the unsuccessful loading of configuration data 2 The release of the Global Three State GTS This activates all the IOs 3 The release of the Global Set Reset GSR This allows all flipflops to change state 4 The assertion of Global Write Enable GWE This allows all RAMs and flipflops to change state By default these operations are synchronized to OOLK The entire startup sequence lasts eight cycles called OOO7 afterwhich the loaded design is fully functional The four operations can be selected to switch on any OOLK cycle 0106 through settings in the Xilinx Development Software The default timing for startup is shown in the top half of Figure 15 heavy lines show default settings The default Startup sequence is that one OOLK cycle after DONE goes High the global 3state signal GTS is released This permits device outputs to turn on as neces sary One OOLK cycle later the Global SetReset GSR and Glo bal Write Enable GWE signals are released This permits the internal storage elements to begin changing state in response to the logic and the user clock The bottom half of Figure 15 shows another commonly used version of the startup timing known as SynctoDONE This version makes the GTS GSR and GWE events conditional upon the DONE pin going High This timing is important for a daisy chain of multiple FPGAs in serial mode since it ensures that all FPGAs go through startup together after all their DONE pins have gone High SynctoDONE timing is selected by setting the GTS GSR and GWE cycles to a value of DONE in the configuration options This causes these signals to transition one clock cycle after DONE externally transitions High The sequence can also be paused at any stage until lock has been achieved on any or all DLLs Default Cycles Startup CLK LLLLILLILILIL DONE EDI as m esre GWE Sync to DONE StartupCLK Phase BBB DONE High 1 GT8 I l GSR I l GWE I I DSEIEILILEIBEIEEIEI Figure 15 StartUp Waveforms Serial Modes There are two serial configuration modes In Master Serial mode the FPGA controls the configuration process by driv ing OOLK as an output In Slave Serial mode the FPGA passively receives OOLK as an input from an external agent eg a microprocessor OPLD or second FPGA in master mode that is controlling the configuration process In both modes the FPGA is configured by loading one bit per OOLK cycle The MSB of each configuration data byte is always written to the DIN pin first See Figure 16 for the sequence for loading data into the SpartanIIE FPGA serially This is an expansion of the quotLoad Configuration Data Framesquot block in Figure14 page 14 DSO772 v21 July 9 2003 Product Specification wwwxilinxcom 15 18002557778 SpartanIIE 18V FPGA Family Functional Description X XILINX After INIT Goes High User Load One Con guration Bit on Next CCLK Rising Edge I I I I I I l l I I I I I I End of Con guration Data File No To CRC Check Dmm fl 4932mm Figure 16 Loading Serial Mode Con guration Data Slave Serial Mode In Slave Serial mode the FPGA s CCLK pin is driven by an external source allowing the FPGA to be configured from other logic devices such as microprocessors or in a daisychain configuration Figure 17 shows connections for a Master Serial FPGA configuring a Slave Serial FPGA from a PROM A SpartanIIE device in slave serial mode should be connected as shown forthe third device from the left Slave Serial mode is selected by a lt11xgt on the mode pins M0 M1 M2 The weak pullups on the mode pins make slave serial the default mode ifthe pins are left uncon nected The serial bitstream must be setup at the DIN input pin a short time before each rising edge of an externally gener ated CCLK Timing for Slave Serial mode is shown in DS0773 SpartanHE 18V FPGA Family DC and Switching Charac teristics Daisy Chain Multiple FPGAs in Slave Serial mode can be daisychained for configuration from a single source After an FPGA is configured data forthe next device is sentto the DOUT pin Data on the DOUT pin changes on the rising edge of CCLK Note that DOUT changes on the falling edge of CCLK for some Xilinx families but mixed daisy chains are allowed Configuration must be delayed until W pins of all daisychained FPGAs are High For more information see Startup page 14 33V 18V 33y 37gv 33V 18V MO NH VCCO 333 K M0 M1 Vcco M2 Vcc NT M2 Vcc NT 39 DOUT DIN DOUT gt SpartanIIE CCLK Master Serial Spanan39IIE Vcc Slave XIIInx CCLK CLK PROM DIN DATA m a 7 PROGW DONE W WOE 7 DONE W GND GND GND PROGRAM Notes DSEI77727EI47EI7EI2EI3 1 If the DriveDone configuration option is not active for any of the FPGAs pull up DONE with a 33KQresistor or lower Figure 17 MasterSlave Serial Configuration Circuit Diagram 16 wwwxilinxcom 18002557778 DSO772 v21 July 9 2003 Prod uct Specification X XILINX SpartanHE 18V FPGA Family Functional Description Master Serial Mode In Master Serial mode the OOLK output ofthe FPGA drives a Xilinx PROM which feeds a serial stream of configuration data to the FPGA s DIN input Figure 17 shows a Master Serial FPGA configuring a Slave Serial FPGA from a PROM A SpartanllE device in Master Serial mode should be connected as shown forthe device on the left side Mas ter Serial mode is selected by a lt00xgt on the mode pins M0 M1 M2 The PROM RESET pin is driven by W and the OE input is driven by DONE For more information on serial PROMs see the Xilinx Configuration PROM data sheets at http39llwww X39 X QleX IXIXJNEDIX39 pub 39Qat39QHS 39lldex 3955 The interface is identical to the slave serial mode except that an oscillator internal to the FPGA is used to generate the configuration clock OOLK Any of a numberof different frequencies ranging from 4 to 60 MHz can be set using the ConfigRate option in the Xilinx development software When selecting a OOLK frequency ensure that the serial PROM and any daisychained FPGAs are fast enough to support the clock rate On powerup while the first 60 bytes of the configuration data are being loaded the OOLK fre quency is always 25 MHz This frequency is used until the ConfigRate bits part of the configuration file have been loaded into the FPGA at which point the frequency changes to the selected ConfigRate Unless a different fre quency is specified in the design the default ConfigRate is 4 MHz The FPGA accepts one bit of configuration data on each ris ing OOLK edge After the FPGA has been loaded the data for the next device in a daisychain is presented on the DOUT pin afterthe rising OOLK edge The timing for Master Serial mode is shown in DSO773 SpartanHE 18VFPGA Family DC and Switching Characteristics Slave Parallel Mode SelectMAP The Slave Parallel mode also known as SelectMAP is the fastest configuration option Bytewide data is written into the FPGA on the D0D7 pins Note that D0 is the MSB of each byte forconfiguration A BUSY flag is provided for con trolling the flow of data at a clock frequency above 50 MHz Figure 18 page 18 shows the connections for two SpartanllE devices using the Slave Parallel mode Slave Parallel mode is selected by a lt011gt on the mode pins M0 M1 M2 The agent controlling configuration is not shown Typically a processor a microcontroller or OPLD controls the Slave Parallel interface The controlling agent provides bytewide configuration data OOLK a Chip Select a signal and a Write signal WRITE f BUSY is asserted High by the FPGA the data must be held until BUSY goes Low After configuration the pins of the Slave Parallel port DOD7 can be used as additional user O Alternatively the port may be retained to permit highspeed 8bit read back Then data can be read by deasserting WRITE f retention is selected prohibit the D0D7 pins from being used as user O See Readback page 19 DSO772 v21 July 9 2003 Product Specification wwwxilinxcom 17 18002557778 SpartanIIE 18V FPGA Family Functional Description X XILINX DATA70 CCLK WRITE BUSY M1 M2 M1 M2 I MO I W SpartanHE SpartanHE D0D7 D0D7 O 0 0 gt CCLK CCLK WRITE WRITE BUSY BUSY OS0 Cis CS1 Cis PROGRAM PROGRAM DONE W DONE W GND GND l l DONE E m I PROGRAM DSEI77727EI6711EI1EI2 Figure 18 Slave Parallel Configuration Circuit Diagram Multiple SpartanIIE FPGAS can be configured using the Slave Parallel mode and be made to startUp simUlta neously To configure multiple devices in this way wire the individual CCLK Data WRITE and BUSY pins of all the devices in parallel The individual devices are loaded sepa rately by asserting the a pin of each device in turn and writing the appropriate data SynctoDONE startUp timing is used to ensure that the startUp sequence does not begin until all the FPGAS have been loaded See Startup page 14 Write When using the Slave Parallel Mode write operations send packets of bytewide configuration data into the FPGA Figure 19 page 19 shows a flowchart ofthe write sequence used to load data into the SpartanIIE FPGA This is an expansion of the quotLoad Configuration Data Framesquot block in Figure 14 page 14 The timing for Slave Parallel mode is shown in DSO773 SpartanHE 18V FPGA Family DC and Switching Charac teristics For the present example the user holds WRITE and a Low throughout the sequence of write operations Note that when a is asserted on successive CCLKs WRITE must remain either asserted or deasserted Otherwise an abort will be initiated as in the next section 1 Drive data onto D0D7 Note that to avoid contention the data source should not be enabled while E is Low and WRITE is High Similarly while WRITE is High no more than one device s should be asserted 2 On the rising edge of CCLK If BUSY is Low the data is accepted on this clock If BUSY is High from a previous write the data is not accepted Acceptance will instead occur on the first clock after BUSY goes Low and the data must be held until this happens 3 Repeat steps 1 and 2 until all the data has been sent 4 Deassert and WRITE 18 wwwxilinxcom 18002557778 DSO772 v21 July 9 2003 Prod uct Specification ZMUNX SpartanHE 18V FPGA Family Functional Description If CCLK is slower than FCCNH the FPGA will never assert BUSY In this case the above handshake is unnecessary and data can simply be entered into the FPGA every CCLK cycle After INIT Goes High User Drivei WRITE and CS Low Load One Configuration Byte on Next CCLK Rising Edge FPGA Driving BUSY High Yes End of Con guration Data File No User Drivei WRITE and CS High I To CRC Check I DSEIEHJBiEISZSEIEI Figure 19 Loading Configuration Data for the Slave Parallel Mode A configuration packet does not have to be written in one continuous stretch rather it can be split into many vLite sequences Each sequence would involve assertion of CS In applications where multiple clock cycles may be required to access the configuration data before each byte can be loaded into the Slave Parallel interface a new byte of data may not be ready for each consecutive CCLK edge In such a case the a signal may be deasserted until the next byte is valid on D0D7 While E is High the Slave Parallel inter face does not expect any data and ignores all CCLK transi tions However to avoid aborting configuration WRITE must continue to be asserted while a is asserted during CCLK transitions Abort To abort configuration during a write sequence deassert WRITE while holding a Low The abort operation is initi ated at the rising edge of CCLK The device will remain BUSY until the aborted operation is complete After aborting configuration data is assumed to be unaligned to word boundaries and the FPGA requires a new synchronization word priorto accepting any new packets BoundaryScan Configuration Mode In the boundaryscan mode no nondedicated pins are required configuration being done entirely through the IEEE 11491 Test Access Port TAP Configuration through the TAP uses the special CFGIN instruction This instruction allows data input on TDI to be converted into data packets for the internal configuration bus The following steps are required to configure the FPGA through the boundaryscan port 1 Load the CFGIN instruction into the boundaryscan instruction register IR Enter the ShiftDR SDR state Shift a standard configuration bitstream into TDI Return to RunTestIdle RTI Load the JSTART instruction into IR Enter the SDR state Clock TCK if selected through the startup sequence the length is programmable 8 Return to RTI Configuration and readback via the TAP is always available The boundaryscan mode simply locks out the other modes The boundaryscan mode is selected by a lt10xgt on the mode pins M0 M1 M2 Note thatthe PROGRAM pin must be pulled High prior to reconfiguration A Low on the PRO GRAM pin resets the TAP controller and no boundary scan operations can be performed See Xilinx Application Note mmr more information on boundaryscan configu ration Readback The configuration data stored in the SpartanIIE configura tion memory can be read back for verification Along with the configuration data it is possible to read back the con tents of all flipflopsIatches LUT RAMs and block RAMs This capability is used for realtime debugging For more detailed information see Xilinx Application Note XAPP176 Spartanll FPGA Series Configuration and Readback NOF IPWN DSO772 v21 July 9 2003 Product Specification wwwxilinxcom 19 18002557778 SpartanIIE 18V FPGA Family Functional Description Revision History X XILINX Version No Date Description 10 111501 Initial Xilinx release 20 111802 Added XCZS400E and X028600E Removed Preliminary designation Clarified details of O standards boundary scan and configuration 21 070903 Added hot swap description see Hot Swap Hot Insertion Hot Socketing Support Added Table 7 containing JTAG IDCODE values Clarified configuration PROM support The SpartanIIE Family Data Sheet DS0771 SpartanIE 18V FPGA Family Introduction and Orderina Information Module 1 DS0772 SpartanIE 18V FPGA Family Functional Description Module 2 DS0773 SpartanIE 18V FPGA Family DC and Switching Characteristics Module 3 DS0774 SpartanIE 18V FPGA Family Pinout Tables Module 4 20 wwwxilinxcom 18002557778 DSO772 v21 July 9 2003 Prod uct Specification
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