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by: Corina Serna

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# Chapter 3 - Sequential Logic ECE 274A

Corina Serna
UA
GPA 3.1
Digital Logic
Ali Akoglu

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This is this week's notes and are pretty straight forward. The last couple of sections are short because the work is done mostly through the online book with the exercises provided.
COURSE
Digital Logic
PROF.
Ali Akoglu
TYPE
Class Notes
PAGES
2
WORDS
KARMA
25 ?

## Popular in ELECTRICAL AND COMPUTER ENGINEERING

This 2 page Class Notes was uploaded by Corina Serna on Thursday February 19, 2015. The Class Notes belongs to ECE 274A at University of Arizona taught by Ali Akoglu in Spring2015. Since its upload, it has received 83 views. For similar materials see Digital Logic in ELECTRICAL AND COMPUTER ENGINEERING at University of Arizona.

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Date Created: 02/19/15
Chapter 3 Sequential Logic Section 1 SR Latches 0 Sequential circuit output dependent on present and previous inputs stores at least 1bit 0 Combinational circuit output only dependent on present inputs 0 Latch simple circuit that stores a bit 0 SR latch s set r reset q Previouslystored bit 0 Reset 1 C Set Unknown r w xoorn HOb toH 0 Oscillate change from 1 to 0 to l repeatedly Section 2 FlipFlops o D Latch input 1 for bit to be stored and input e that enables storing bit 1 data e enable q Previouslystored bit dignored Previouslystored bit dignored 0 dstored 1 dstored r tr tOOC39D Hot 09 0 Clock signal a regularoscillating signal used control when to store bits 0 Rising edge bits are stored only at instant a clock signal changes 0 to 1 0 Latch stores a new bit while an enable latch is 1 0 Level sensitive when a latch stores when the enable s latch is l o Flip op stores a new bit only at the instant of an enable signal s rising edge edge triggered Masterservant arrangement ip op implemented by twolatches with first latch enable inverted first latch master second latch servant Section 3 Basic Registers 0 Bits are usually stored in bits 0 Register a circuit that stores a group of bits 0 Example 3bit register stores 3 bits 0 Loading the register strong bits in register Section 4 FSMs FSM computational model capable of describing sequential behavior short for finite state machine State present situation of a digital system ie human 9 eating sleeping working etc starts in initial state Section 5 FSM Stimulator Period FSM s clock period typically set to microseconds or nanoseconds Initial state checkbox makes currentlyselected state the initial state Actions can be added by typing in box Deleting is done by selecting the item then pressing delete button When FSM is executing values cannot be changed The export text only appears in the text box text must be copypasted to a file to be saved Section 6 Capturing Behavior With FSM Capturing behavior With an FSM describing desired system behavior using an FSM FSMs often have enabled functionality Which stops the normal behavior if an enable input is 0 Toggle to change to the opposite situation either from off to on or from on to off After detecting change 0 to 1 FSM waits until change back to 0 so FSM only toggles for each pulse Section 7 FSMs to Circuits Controller an FSM can be converted to a sequential circuit consisting of a register and a logic block State register stores the present state Logic block consists of combinational logic and computes o The output based on present state Architecture a controller s highlevel vieW Section 8 FSM Issues For a given FSM state exactly one outgoing transition should have a true condition at any given time If initial state has different encoding than all 0 s the state register ip ops may be initialized using reset set inputs Section 9 Circuits to FSM A sequential circuit With register and logic can be converted to FSM 0 Through a truth table 0 Lost all inputs and register bits on one side 0 List all outputs and register bits on other side

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