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by: David Meyer

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# CS 2200 Week 3 Notes CS 2200 A3

David Meyer

GPA 3.8

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Discussion of how instructions are run through a computer and the different hardware pieces involved.
COURSE
Systems and Networks
PROF.
Tom Conte
TYPE
Class Notes
PAGES
4
WORDS
KARMA
25 ?

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This 4 page Class Notes was uploaded by David Meyer on Sunday September 11, 2016. The Class Notes belongs to CS 2200 A3 at Georgia Institute of Technology - Main Campus taught by Tom Conte in Fall 2016. Since its upload, it has received 18 views.

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Date Created: 09/11/16
● Styles of ISA’s: # ops per instruction  ○ 3­ operand  ■ LC­3, LC­2200, ARM, v7  ■ ADD Dest, Src1, Src2  ○ 2­ operand  ■ ADD R1, R2: R1 <­ R1 + R2  ● Example: x86  ● “Destructive ISA”  ○ 1­ operand  ■ Implicit calculation requries an assumulator (acc)  ■ ADD R2: ACC <­ Acc + R2  ■ LD B: A <­ B + C  ■ ADD C  ■ ST A  ○ 0­ operand  ■ Polish notation  ■   Polish notation  Reverse Polish  Stack  *  1  PUSH 1  +  2  PUSH 2  1  +  ADD  2  3  PUSH 3  +  4  PUSH 4  3  +  ADD  +  *  MULT  4      ● Instruction Encoding  ○ Why use accumulator or stack ISA in 2016?  ○ Memory or comm b/w is expensive  ● Variable length instructions  ○ Positives  ■ Low memory use  ○ Negatives  ■ Fetch memory xbits  ■ Decode  ■ Execute  ■ Loop the fetch and decode for the variable length can take time  ● ISA restuicts the hardware implementation DOES NOT dictate the implementation s86.  Fixed width easy to decode style. Reuced Instruction Set Computer: RISC  ● ARM: Acorn Risc Machine  ● ISA implementation  ○ Called a microarchitecture  ○ What we want: speed, low energy consumption (battery life), low power  dissipation (cooling), low cost  ○ Speed is the only concern: super computers, data center servers  ○ Embedded: IoT edge; low energy, low cost  ● Logic: time­independent, binary function  ○ Combo: f(x,y,x)=w  ○ Sequential logic: f(x,y,z, past inputs)=w  ○ Use both kinds to build a microarchitecture  ● Memory elements: 2 kinds  ○ Latch and flip flop  ○ Two inverters on a flip flop = positive edge flip­flop  ○ One inverter on a flip flop = negative edge flip­flop  ● Tri State buffer  ○ Allow us to have isolation  ○ That way we do not have any crashes on the bus  ○ 1: Din = Dout  ○ 0: no connection  ● ROM  ○ Affects the DrPC, DrALU, DrREG, LDPC, LDA, LDB, func, regNO, etc  ● IR uses a mux to be able to pull out different registers within the reg file  ● Below is the beginning table of different states for the fetch state of the computer:  ○     pc  alu  reg  mem  off  pc  a  b  mar  ir  z  reg  mem  func  regsel  F1  1  0  0  0  0  0  0  0  1  0  0  0  0  0  0  F2  0  0  0  1  0  0  0  0  0  1  0  0  0  0  0  F3  1  0  0  0  0  0  1  0  0  0  0  0  0  0  0  F4  0  1  0  0  0  1  0  0  0  0  0  0  0  11  0  ● State Machine  ○ Fetch ­> Decode ­> Execute ­> Fetch…  ● Fetch  ○ Fetch 1  ■ Pc ­> Mar  ■ drpc = 1  ■ ldmar = 1  ○ Fetch 2  ■ Mem[Mar] ­> IR  ■ Drpc = 0  ■ Ldmar = 0  ■ Wrmem = 0  ■ Ldir = 1  ■ Drmem = 1  ○ Fetch 3  ■ PC ­> A  ■ Drpc = 1  ■ Lda = 1  ○ Fetch 4  ■ A + 1 ­> PC  ■ Func = 11  ■ Dralu = 1  ■ Ldpc = 1    ● Funcs  ○ 00 = Add  ○ 01 = Nand  ○ 10 = A ­ B  ○ 11 = A + 1

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