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by: Miss Chadrick Doyle


Miss Chadrick Doyle
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Robert Albright

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Robert Albright
Class Notes
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This 19 page Class Notes was uploaded by Miss Chadrick Doyle on Tuesday September 1, 2015. The Class Notes belongs to ECE 510 at Portland State University taught by Robert Albright in Fall. Since its upload, it has received 22 views. For similar materials see /class/168222/ece-510-portland-state-university in ELECTRICAL AND COMPUTER ENGINEERING at Portland State University.

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Date Created: 09/01/15
Between Failure Reliability Yield and IC Layout ECE 510 Device Reliability Spring 2003 Lecture 2 Effects of Scaling Interconnects Malgorzata ChrzanowskaJ e ske Electrical and Computer Engineering Portland State University IC Technology Scaling The horizontal and vertical dimensions are scaled to keep the internal electric fields more or less constant and the hot carrier effects 4 smz 510mmin Lemre 1 SW 1 Scahng Scaling effects on device parameters Pararneter Full Scaling CV Scaling Dimensions width length oxide thickness Us US Voltages Power threshold Us 1 Gate Capacitance Us US Current US s Propagation Delay Us US2 19 510 Rzlialn39lgv mee 13 sm3 Consequences of Scaling Interconnects 0 Resistance 0 Capacitance 0 Inductance 0 Delay 0 Transistors 0 Hot electrons 0 Gate oxide 0 Leakage current 510 litMilo Lu1ure 1 SMA IC Scaling Technology scaling 39Miniaturization of devices scale L W TOX VT Device technology scales well 39 Gate performance increases linearly with decreasing feature size Faster smaller devices gt S07 Smallest feature Lum 035 025 018 012 etc 510 Relz39abmy Leclure 2 Slide 5 IC Scaling Wires scale differently 39 Wire delay function of Wire resistance and capacitance 39 Global interconnects Long Wires getting relatively slower over RC delay IS or IS2 39 Local interconnects short Wires not much change 39 Parasitics a Whole set of signal integrity issues Sl kk39abm Lecture 012 slide 6 The general SIA road map for interconnects 1997 1999 2001 2003 2006 Technologyum 0 25 018 015 013 01 Number ofmetal levels for logic 6 67 7 7 78 Metal contacted pitchQLm 1 0 6 0 5 0 4 0 35 Total length for logicmcl1ip 820 1480 2160 2840 5140 Chip areamm2 2800 400 445 560 790 Metal densitym mmZ 2 9 3 7 4 9 5 1 6 5 Local clock frequencyMHz 750 1250 1500 2100 3500 4 510 Reliab fy Lecture 12 Slide 7 Interconnect Delay Dominates Gate Delay Delay ms N is u o 5 Interconnect 05 D 35 025 018 013 01 Shnnlmg oncess 5mm 5m Tenhnalauy mum 1 510Rell39ah gv Leclum 1112 slide 8 Interconnectdominated Designs Interconnect parasitics dominate delay 7 ofwires oo ofdevices 7 More metal layers 7 RC delay 7 Rising frequencies inductive effects 7 Coupling capacitances noise Hard to predict Wire loads 7 Timing convergence difficult 7 Multiple iterations necessary Accurate models for interconnects needed 510 Reliahluy Lecture 12 SH 9 Wire Resistance Trends R is rising with scaling interconnect dimmensions Reduces the applicability of capacitanceonly models IfR is large the Wire has an intrinsic delay RC delay is the time the Wire takes to charge its own capacitance through its own resistance 39 To reduce R use Widerthicker Wires Wider Wires use more routing space larger design Thicker Wires lead to larger capacitances 7 this leads to noise 51012211211119 Levtwe 12 SHE M Dimensions of Metal Layers Layer Pitch um Thickness Mm Aspect Ratio M1 0 64 0 48 l 5 19 M2 0 93 0 89 l 9 M3 0 93 0 89 l 9 M4 1 60 l 33 l 7 M5 2 56 l 90 l 5 Intel s P856 DI 5101er EEL39ULYE 112 SH 11 190 micrometers pitch of 256 micrometers 4 Wire Delay Scaling Local Wires I cm 2 o For Wire crossing the same amount of circuitry 7 Resistance stays roughly constant 0 L decreases by the same amount as W height stays large or decreases if Cu 7 Capacitance decreases by scaling factor capunit length constant length decreases chonstant C 39 Delay 510 Reliah w lecture 1 SIM 12 Wire Delay Scaling Global Wires I gt For wire crossing whole chip Resistance grows linearly Capacitance stays fixed Wire delay increases relative to gate delay are getting much slower 2 As measured in distance per clock cycle wires Local vs Global No of nets Log Scale 10 100 1000 10000 100000 Length my 2 51a mummy me Lz Slide 14 39 To first order m 51a Revamp Lecture 11 Slide 13 um mas Delay Fan 0 11 4 Luca swam in 7 E m Gm m Rawaters D 3 16 3 f n 01 mm m on 55 u 2 Process Technology Node nm 4 510 Reliahmy Lecturu 12 Slide 15 Wire Capacitance Trends CC M1 M1 C1 C2 amp Sub Sub Present future C Area of overlap 7 C 1 distance Interconnect geometries change with scaling L constant with scaling W and t scale together WSW Capacitance extractor needed Mainly Distance between wires is shrinking Line spacing lt Dielectric thickness Metal thickness gt Metal width 5m Reliab gv Lecture 11 Slide 16 Coupling capacitance dominates interlayer capacitance Ln mu m m it cg I I 1 CC c g own02m 1997 2001 2006 2009 2012 Source 1998 Update ITRS 4 510 Reliab iy Leclure 2 Slide 17 New Wire Material Copper 7 539 3 W 2 TSMC Copper Process oAll 018 pm processes are replacing A1 with Cu 40 lower resistance N100 times longer electromigration lifetime Gives 12 improvement oflifetime over an Al process in a PowerPC design 510 tummy Leclure 2 Slide 18 Copper Interconnects Key advantages 0 better electrical conductivity 0 superior electromigration resistance Key disadvantages 0 contamination during integration 0 difficult to pattern etch 0 high diffusivity in Si and Si02 510 Reh39ahl39lty Lec1ure 412 5MB 19 Lowk Dielectrics for Interlayer Isolation Lower wiring capacitance leads to 0 lower delay and power consumption helps reduce noise in short to intermediate length wires 0 Industry outlook 018 pm and next dielectrics ranging from k 27 to 40 Ultimately aerogels may be used with k N 1 510 mummy Leanne 2 Slide 20 Physical Challenges of DSM Interconnects 39 Signal integrity 39 Electromigration 39 IR drop 39 Antenna Effect 510mmin Lemre 1 SW 21 Coupled Interconnects capacitive coupling 7 induces current 139quot C inductive coupling 7 induces voltage V L 510 Rzmilgv mee 2 SW 23 Signal Integrity Noise Noise sources cause signal integrity problems Cww Cc is dominant When neighboring lines switch a quiet line experiences a glitch due to coupling Can lead to Logic Faults Voltage Overshoot stress forwardbias PN Junctions Coupling capacitance Causes crosstalk and delay degradation Packagelevel inductance L didt voltage drop Power grid IR drop Reduced noise margins slower gates I o Keliabilg mee 1 SW 22 Capacitive Coupling Model Cc C1 Hi lCz Coupled voltage change in V1 gt change in V2 CC dV1 7 dt iCCCzl dt 510 Mung Lu1ure 1 SW 21 Crosstalk and Switching Noise Cross talk is noise induced by one signal that interferes with a nearby signal Onchip cross talk is caused primarily by capacitive coupling of nearby signals A transition on a signal injects charge into adjacent signals causing a transition on an adjacent signal scaled by a voltage divider If the victim line is oating the disturbance persists and may cause switching If the victim line is driven the signal returns to its original with an RC time constant 510 Relz39ab ty Leclure 12 Slide 25 Crosstalk and Switching Noise 0 When neighboring lines switch in opposite direction of victim line delay increases 7 twice as much charge must be transferred across the coupling capacitance comparing to only one line switching 7 Miller effect 0 Cross talk degrades noise margins and increases delay 0 It is particularly damaging in cases where line with a large swing is coupled to a line that has a small signal swing Coupling Capacitance Case 1 Switching in the Same Direction C c ccouple 0 Case 2 One Switching CILD ccouple CC Case 3 Switching in Opposite Direction I Cc ccouple ZCC 1 51011er Leclure 1 Slide 27 510 Rzk39ab ty Lecture 2 SM 26 Crosstalk and Sw1tch1ng NOISe Agra s s or 7 D 77C07 3397 1397797Ai h J39 D Victim CL 75 A Noise Prop agation Agra s s or A Do Vl7 7AVE 39L C V 14gt 1 39f Victim CL Increased Delay 7 510 Remmy Leum 2 SM 28 Crosstalk Noise Inducing Timing Variation Victim With if iS 39 Vdci 2 0pposiie switching direction Same switching dilection IIIII IIII 7 510 Rziiabilty Lecture 11 Slide 29 Electrical Model of CrossTalk Simple Crosstalk Coupling Model Von h V R sVi V l um dvuim m 7 C C T I Maximum Delta Voltage IR Drop The excessive voltage drop at the gates due to the resistance of the power supply lines 1R Drop AVM IgtRI Rx Vs Vg V 510 Reliabilty Lecture 11 Slide 31 1 M VDD CXRV 1 emu f rf RVCX CV AK wai when rf ltlt RACK CV 510 Reliabilty Lecture 1 Slide 30 IR Drop IR Drop in DSM technology 0 Increased current on power DSM supply lines Increased technology IR Drop 0 Increased Wire resistance Effects on circuit performance Weakens the driving capability Increases the overall delay 5 IR Drop can cause 15 increase in the gate delay Reduces the noise margin 510 Rzl39mbilty Lecxure 1 Slide 32 Electromigration Electromigration The electrons from a DC current ow will tend to push metal atoms out of place AC current ow OK The mean time to failure MTF MTF oo J392expEA Main problem is power lines but some kT signal lines have unidirectional current E A activation energy Al 04 05 eV 0 Manufacturers place a current density FESEM microgmph ofalmnmmn limit for metal to guarantee small life exhibiting classi e ectromigration vor rig resistance increase after 10 years operation 5 510 Reliabilty Lecture 12 Slide 34 510 Reliabin Lecture 2 Slide 33 EleCtmmlgraUOn Distribution of Current Stress in 333 MHz Alpha 21164 Wire can tolerate only a certain amount of current density 39 Direct current for a long time causes ion movement breaking the wire over time 0 Contacts are move vulnerable to electromigration as the current tends to run through the perimeter Perimeter of the contact not the area important 0 Use of copper heavier ions have helped in tolerating electromigration TSMC 018pm 3 lmAum metal wires 04um thick 5 E 11 028 mAvia 2 TWS gure 5 derived from Des9n Of HghrPefolma ce Mcopocesso CHEM5 A Chandrakasan W BOWHHL F FOX 85 2001 510 Reliabilty Lecture 12 Slide 36 510 Reiiubilty Lecture 12 Slide 35 Electromigration example Electromigration and Scaling Interconnect dimension current 1 remains the same Current densities J As the number of electrons f the breakdown of the atomic structure of the interconnect metal is more likely 4 v The removal of enough atoms can lead to voids A wire broken off due to A contact via broken up where the atoms have been removed and cause electromigration 11 due to electromigration device failure These figures are derived from Digital ntegrated circuit a design perspective J Rabaey Prentice Hall 510 Reliabilty Lecture 12 Slide 37 510 Reliabilzj Lecture 12 S lide 38 Electromigration EIGCtYOmlgraUOn i 39 i 39 l i i l I Atoms that were moved to new locations are collected and can cause bulging of the interconnect through insulation material that surrounds and separates the interconnect layers electrical 39bridge39 between interconnection layers Hillocks bulges formed in a Cu line during electromigration test 0 o o o o o o o MkMM Electromigration is currently limiting the interconnect Size and current density in today39s IC s 5 510 Reliabilty Lecture 12 Slide 39 510 Reliabilty Lecture 1 2 Slide 40 Current Density Definitions 23 pm quot rid I microscope Image ofthe WW formation ofvoid 1 rtmT 1IDC I W T jw 39 139 Jim 39 r jpmk 1 T 1 7 2 Javg fJtd 1m f1 111 a 1 Wm SM 4 mm mm mm Technolo Scalin Effects Electromigration gy g 39 Electromigration Transport of mass in metals under an applied current density ipkMAlcm o s N a s o m Black s Equation E J kETm I EM stress data Black s Equation a technology limit to the maximum current density javg for arequired Oxide qu Polyimide Air failure rate and a desired lifetime at a reference Dielectric Material temperature Tref jpeak decreasesWith increasing metal layers 39 lower dielectric constants Fractional decrease injpeak With lower values ofk is more for higher metal layers is therefore not self COHSIS en EMlil39etime determined hyi Thisjavg limit does not comprehend self heating and t t u il kzluhhy 4mm SM 43 mummy rLulurrtl SW 44 Metal film structure The formation of voids and accumulations is dependent on the underlying microstructure of the metal lm from Which the interconnect has been patterned b di 39erent width patterned lines a metal lm 11 510 Relith Lecture 12 Slide 45 Bamboo Interconnects Grain boundary clusters the failure sites for real interconnect Under high current stress electromigration causes material transport along the grain boundary paths The resulting flux divergence associated with the grain boundary cluster eventually causes metal grains to erode giving rise to a void 510 Relith Lecture 12 Slide 47 Grain Boundaries grain boundary 39Clumequot grain boundary 39cluster39 4 depletion site accumulation site 39votd39 4gtEgt Egtl4gt atomic ux along grain boundary path accumulation not shown in befme 11 h alter 510 Reliabilty Leititre 12 Slide 46 Bamboo Interconnects Grain growth may be stimulated through annealing microstructure change smaller neighboring grains larger grain order of magnitude improvement If grain distribution increases or line width decreases grain boundaries shrunk to one or two grain boundaries spanning the interconnect width Bamboo or near bamboo interconnects 510 Reliabilty Leititre 12 Slide 48 12 Electromigration EM is very sensitive to technology scaling If one fixes the transistor current and scales the transistor voltage as 539 the current density I Will scale as S2 and so MTTF scales as S394 I I Short lines can remedy EM degradation at the cost of increased layers of processing and design complexity Multilayer metallization has helped improve EM 510mmin Lemre 1 SW 9 Selfheating EM depends on the directionality of the current Selfheating is just proportional to the amount of current the Wire carries Current flow causes the Wire to get heated up and can result in providing enough energy to carriers to make them hot carriers Selfheating can be reduced by Wire sizing as Ell ATM4mg Tm Tm ImeEW Sellihealjng determined by 1quot 510 Kelmilg mee 1 SW 50 Selfheating Thermal effects SH Limits the current density 39 Reliability strongly in uenced by thermal effects 39EM lifetime decreases exponentially with increasing temperature 39 Increasing number of metal layers and lowk dielectrics further worsen thermal effects 39 High current events cause thermal failures inle 510 sz39allilgv mee 2 SW 51 Thermal Effects under High Current ESD Short duration lt 200 ns high current gt 1 A Causes thermal breakdown of interconnects Increasing importance due to scaling Failure current densities are much higher than under normal circuit conditions 51019110171192 Lu1ure 1 SW 52 Thermal Effects under High Current ESD Highcurrent shorttime scale failure model can be applied to design interconnects in 10 Buffers and Antenna Effect antenna problem is a side effect ofvanous plasmabased manufacturing processes such a etching etc ESD protection circuits B t 1 IEEE EDL 97 Plasma etchers or ion implanters can induce a men e a 39 voltage into isolated leads overstressing thin gate Model can also be usedto design Cu interconnects xides Voldman et a1 EOSESD Symp lt97 meme um m 5 mane new 5 Antenna Effect Antenna Effea eets Dry Etching The leads polysilicon or metal act like an Intense E geld antenna to collect charges and the accumulated Accumulation of elec39mstahc charges charges may result in oxide bre down 76m poly and sidewall spams These charges may also have a gmV6 effect on Degradation ofdielectric strength due to current hotcanier device aging lifetime As device scaling goes on the oxides ofnew s 7 devices are getting thinner and thinner l a enna effect to become worse and worse l l l l ml mamak1 um m 55 mamatry new 5 Antenna Effect Electrostatic charge proportional to area of poly Small gates connected to large poly area can cause signi cant damage mm 10 5M Mutiny Lecture 1 Slide 57 Antenna Effect Poly area acts as antenna Effect also seen during ion implantation of the sourcedrain regions 10 Antenna Effect Measurement of effect Magnitude of effect proportional to Exposed Conductor Area Gate Oxide Area Separate area ratios computed for multiple layers Signi cant damage conductor area 3 several hundred gate area 510 Malliltv Lectur 122 Slide 59 5M Rdiabilty Lecmre 12 51142 53 Antenna Effect Prevention Etching of poly and sidewall spacers Insert of metal jumper Escape route for charges Reduces area of the poly connected to gate oxide Removed after etching or implantation 10 510Rdmbilty Lecrure 11 5mg 60 Antenna Effect Prevention Etching of metal layers Layers connected to diffusions provide leak path Jumpers inserted for layers not yet connected to diffusions 5m Kamila Lemre 1 SW 61 Device Degradation Due to Hot Carrier Hot carriers are energetic electrons excited by E field in transistor s drain region Injected into gate oxide cause damage to oxi Hot carrier effect degrades circuit performance Trapped electrons increase VT Degrades saturation current ION Circuit speed is degraded Degradation is timedependent Circuit Will fail at some point 510 Rzlr39aln39lgv mee 13 SW 63 GATES 0 HOT CARRIER EFECTS SHORT CHANNEL EFFECTS LEAKAGE CURRENT 510 Keliabilg mee 1 SW 62 Hot carrier degradation in M OSFETs 8 m 5 at are collected as gate current 239 Va 7V reduce input impedance 5 D VG 3V 39 6 trapped In the gate oxide as xe charges increases the atband voltage and VT the result with stress mu 4 Bahama stress increased Vr E r decrease of slope transconductanEce The solutI 39on lightlydoped drain LDD 13 5 0 75 1 0 VGW 51019110171192 Lu1ure 1 SW 6 Device Degradation Due to Hot Carrier B McGaughy 1998 7 EDA needs Need to estimate lifetime Le time to failure Need to estimate tradeoffs between more reliable and slower design 510mmtu Lecture 12 Slide 65 Decreasing Transistor Length Lgate sou I NMOS 300 750 A PMOS 750 700 I 700 650 K 550 A 600 00 I I g 550 550 3 500 I 500 g 450 450 400 400 A 350 A 350 A 300 ASL 300 250 g A 250 am I I I I I I I I I I 003 010 012 014 018 018 020 022 024 028 Drawn Channel Length pm 7 5m Rtliahtuy mm 012 SHE 66 Decreasing Transistor Length Lgate Much innovation in device engineering in order to preserve a transistor Short channel effects force looking at new transistor structures SOL dual gate transistors FinFETs strained silicon Despite scaling current capabilities are fairly constant Reduction of capacitance is key 510 Reliable Lecture 12 SH 67 Gate Oxide Scaling o2nm physical TOX at 180nm 0 Major concern a huge increase in leakage current density 0 Reliability of oxide is in danger Intel VLSI 2000 7 5m mummy mm 12 SHE 17 Thinner oxides Oxide scaling can be achieved if the following two main issues are addressed 7 Reliability 7 Gate leakage current 8 Reliability Time sequence of the formation of the percolation path in an oxide lm Increase of Leakage Current Ioff Dramatic rise in IOff Gate is unable to turn off conducting channel 0 23 increase in Ioff technology generation 2 E if i 5393 Mumquot 25 250 ma on ma 70 5n quotquot KW lllll TeulmulngyNude Jan Rabaey UCB Temologv loce nrri Intel VLSI 2000 7 2 510 tummy Lacmm 1 Slide 70 510 Reliab ty Leclure 12 Slide 69 Leakage Problem 3 I I 100Acm2quot r NW 3 0 l 5 1quot NTRS Hoadmaps r a 5 0 y C 1 339 LE J 397 l 0 39 9 05 V 05 1 15 20 25 30 35 Oxide Thickness mm As oxide thickness is reduced smaller applied voltage results in a speci ed leakage level 510 Reliahmy Leclure 2 Slide 71 Leakage Power Scaling Generation 0 0m aof T 50 C Block size 50K Due to VT scaling leakage power is becoming a larger portion of the overall power consumption 0 Higher operating temperatures will lead to enhanced static Power dissipation 510 Leclure l2 slide 72 Increase of Gate Tunneling Current Temnozogy Node mm m me 130 110 Due to oxide leakage current through gate Will become comparable to nornlal channel current mm a m 0 Total ILEAKAGE IOFF IGATE n F lt a on m x m a 4 g E m m a Intel VLSI 2000 7 5w Reimbnhy e Laws 1 Slide 73 Reduction of Vdd and VT Vdd and VT reduced by No8 generation 0 Driven by reliability and power concerns 0 Can t reduce VT as much because of high leakage current J 39 Over drive strength VddVT 8 gets smaller Intel VLSI 2000 51 Relmbllny e Ltrnw 2 7 Slide 74 References 1 Steve n quot i up pdf 2 Krste Asanuvic Chris Tennan Wiresquothttp6371105 mit educunentsemesterhanduutsLOS pdf F s r r ECE776 LecturesLectureNutesDay2 pp 4 ht HWW sematech urgpublicpubliDawnsindex mm n hens s JRabaey e quote www eebgu an LlOrlyilabcuursesInkuicuurseShdes meecureozezexmre pp CADquot lt n shsn Gate Oxide Scaling fur sub 100 nm Transistnrsquot users eee gate2h eauesssnn1e13eMshsneomemoascemosmmg pdf 9 E y Wu E T Newak A Vayshenker w L Ls D L Harman cMos scaling beynndme 100mm nude with Silicnnrdmxide ebssea gate dielectrics T VOL 46 NO 2 MarchIda 2002 www research ibm cumJnumalrdAGZwu html 10 Nuah Buydstun Kyle Brawn Ruben Culville Linsy Sunk Wissam Khazem and GeeHyun Yark n Atul Maheshwan Electramigrahun http vsp2 ees umass eauNsmsheshwswvsnaes 12 KaustavBanerJee Axnit Mehrnka Nbertu Sangmenmemneemem and Chenmmg Hu On Thermal Effects in Deep SubeMsemn v151 Intercunnectsquot 13 Ben E s w u 51 Reluzblhy e Ltrnlrt 2 Slide 75


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