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# TOP FOURIER OPTICS ECE 510

PSU

GPA 3.78

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This 24 page Class Notes was uploaded by Miss Chadrick Doyle on Tuesday September 1, 2015. The Class Notes belongs to ECE 510 at Portland State University taught by Richard Campbell in Fall. Since its upload, it has received 12 views. For similar materials see /class/168224/ece-510-portland-state-university in ELECTRICAL AND COMPUTER ENGINEERING at Portland State University.

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Date Created: 09/01/15

Between Failure Reliability Yield and IC Layout ECE 510 Device Reliability Spring 2003 Lecture 22 Yield and Reliability Malgorzata ChrzanowskaJeske Electrical and Computer Engineering Portland State University 510 Leclum 3122 Slide 1 Microelectronic Fabrication lmegralmmrcml lie mm mm 4 150mm mi 13531 3 200 mm 8quot 7 a than 450 mm m y 300 mm 12quot b 8 Relative size of wafers with diameters The same integrated circuit die is ranging from 100 to 450 mm replicated hundreds of times on a Si wafer 510 Leclum 3122 Slide 2 Microelectronic Fabrication t LLUUU l mm mo 1 her or m x lLme has pprnxlm lc nu l mu zoo Jun JUN Wum Lliumewr mum 8 I2 lb 20 Valef diameter in 18 510Reliability Lecture 22 Slide 3 Yield Requirements for VLSI Circuits Be produced in large quantities at low cost OK 0 Perform their mctions throughout their intended lifetime R 0 To lower the cost the optimal size of the IC The optimal size is a compromise between partitioning of the system yield of good circuits 0 packaging and system assembly cost reliability of complete system 510Reliability Lecture 22 Slide 4 Yield Modeling Yield Fraction of manufactured operational chips Y Yield Number of fault free chips Total number of chips Yield enhancement through Defect Tolerance Layout Modi cation C 1 manufacturing Objectives of yield enhancement 0 Reduce wafer cost 0 Allow increased complexity 5112 mummy Lecture 2 Slide 5 Yield Modeling Yield 00 1 Area Size of die in b is 2 times that of in a D0 defect density D0A2 YL22 60 51 L rmn 21 Slide 6 Components of Yield YS and YR YS the Systematic Yield It is limited by defects that affect all the chips or lots and show up again and again in the same places YR the Random Yield It is limited by defects that appear randomly across wafers and chips YYS YR 510 Reliabiligv Latquot 22 Slide 7 Defects that limit YS Affects all die made with that process Process Design Defects Process settings that are not optimized Materials that do not meet technology s needs Equipment that does not work precisely enough Chip Design Defects Error in layout wrong Photolithography mask Cell sensitivity eX ESD Does not meet customer s needs runs too slowly 510 Reliabiligv Latquot 22 Slide 8 Defect that limit YR Particles Particles from process or process gasses Particles from people or Fab environment Handling Dropped wafers or Lots Robot scratching wafers Equipment Failure Overetched wafers Incomplete CMP Misprocessing Wrong or missing process 510 Rell39abill39gv Latquot 22 Slide 9 Defects that can limit both YR amp YS Process Variation Contacts not aligned correctly Poly Critical Dimension s too large or small Spacing Equipment Control Overpolished Overetch or underetch 510 Rell39abill39gv Latquot 22 Slide 10 Yield Design Defects Particles Handling Misprocessing Failure YR Manufacturing 22 Defects 510 Rell39abill39gv Ledquot 4122 Slide 1 1 Yield In a new process Yield is limited by YS Mostly defects of Design In a mature process Yield is limited by YR Mostly defects of Manufacturing 510 Rell39abill39gv Ledquot 4122 Slide 12 Yield Modeling Typical yield components commonly seen in semiconductor manufacturing r 7 ls s gl39FSt l Frant39End E uTafer Asselnhljr Final Grewth Fahricatian I I g Processes Processes I Pr he Package T351 3 1 WTafer Process I Fafer H be 5531 th iF l l TESt munlees I Hquot H Typical Average Yield 9394 Ii 50 quotIn 95 quotii 90 39H 21 510 Reliability Lecture 22 Slide 13 The defect sizes The defect size pdf and related oXide problems Yield failures Infant Mortality failures sx Reliability failures J 150 De fec t s i ze O A Oxide O amp Defect 0 h 21 510 Relmblln y Lecture 22 Slide 14 Critical Area Maps Not all the defects deposited on the chip cause a fault in the circuit 0 A defect that has a radius less than half of the spacing between two metal strips will not cause a short between the two strips l Candutlinll C1Ii lru 1 Line r ml m VIIIIIIIlIIIIIlIIIld mWWWW Duke Nat Causing Faun Cnnduclion Linc V39quot v 271 C llll E 510Re1iabi1ity Lecture 21 Slide 15 Critical Area Ai x the critical area for defects of type i and diameter x The size of the area the center of a defect type i and diameter x must fall in order to cause a circuit fault 0 Assuming that the centers of the defects are uniformly distributed over the chip area then A x pom A Achip Achip area of the whole chip 510 Reiiabijily Lecture 2 Slide 1 6 Interconnect Faults Open Faults Missing material or extra oxide where Via should be formed Short faults Extra material or missing oxide 26 510Reliability Lecture 22 Slide 17 Open vs Short POF 0Ud39 I 1 0018 POF of 007 POF of opens 019 0016 0176115 0014 0012 8 001 m 0008 Shorts 0006 0004 0002 26 U0 5 10 15 20 25 Defect Size Source de Gyvez SLIPOl 510 Reliability Lecture 22 Slide 1 8 Open vs Short Critical Area Opens 25 Source de Gyvez SLIPO1 7 510 Reliablllty Lecture 2 Shde 19 Critical Area vs Defect Radius 020 w M t 4E 115 any 3 quot D 3 ITJ39 a I r D39 g 2 a 27 5 005 d mm m U I d 39 5 Critical area pts d A l wo line tit I I l g l I T I I l l l l I I l V l I V ITWT l l l 0 7 2 3 4 5 Defect Radius um CA 0f the circuit increases with the defect radius and saturates Bigger radius defects will definitely cause a failure no matter where it is centered 510 Reliabzln y Lecture 22 Slide 20 10 Poisson Distribution Evenly distributed defectsfaults D0 7 average defect density A 71 7number of defects N7number of dice P Ak equotA k k Pk 30 is the probability ofk 0 faults A in chip Po e A 7 chip area 7 probability that defect A DOAE will cause a fault A 6 7 critical area Y e D0A 510 Rell39abill39gv Latquot 22 Slide 21 Yield of DefectTolerant Chips Defect tolerance can be introduced through Redundancy Adding space circuit blocks Without defecttolerance Chip Yield YO P0 With defecttolerance Chip Yield YO YC Yuc YO gross yield factor YC yield of correctable part Yuc yield of uncorrectable part 510 Rell39abill39gv Latquot 22 Slide 22 Yield of DefectTolerant Chips If chip is capable of tolerating up to n defects Y6 Pkkfaults k0 Redundancy requires extra space on wafer Y Y Area without redundancy e m ve Area with redundancy 510 Rell39abill39gv Latquot 22 Slide 23 Probability Distribution Function n gt 1 amp large die area Poisson model tends to underestimate die yield defects tend to cluster Possible solution Assume D varies according to a probability distribution KB The expected die yield in this case is expressed as Y fe DAfDdD 0 510 Rell39abill39gv Latquot 22 Slide 24 Ifdi Uniform Density Function stributionfD has mean D0 and is distributed uniformly between 0 and 2Dg i f1 Dal 2AD0 ll 2nH mH Dulucldonsny I 13 394 quot Mummy 44an smz Negative Binomial Distribution 1quotak Aak WW 1Aa k Pkk faults Po faults 1 Aa39 x average number of faults per chips cc clustering parameter D A Y 1 A 05 mme 711011li 5 26 Effect of Clustering on Chip Yield III III Nnnrclustered faults Clustered faults mp 3 mp n Higher Clustering gt Higher Yield Compound Poisson Distribution 7 more clustered kaeiit Pk f 71200617 0 fL normalized distribution of chip defect densities imnetiabim 1mm 21 Slide 27 Murphy s Model Triangle approximation to a Gaussian density 1 ADD 2 ADO DY Probaber dcnslr fl 1 18 in mm dcnsHy n Given a die yield Y and die size A one can numerically solve for the implicit mean defect density D0 that satis es the equation 1 39 39 39 slakzzimiizy erm 21 Slide 28 Seed s Model If D has an exponential distribution ie D LDT fD DOe I Y7 IAD0 A variant of the Seed s model BoseEinstein model Y I ADO 510 mummy Lemm 22 Slide 29 IOU on Ml 39 Pmsson Sn Binomial 4 ni orm 30 Zn 39 I A W quot5 l0 T 3 H gt4 3 5 4 3 7 cxptenum Z uxw DwH DU l H 2 4 17 8 l0 l2 Number ofDefecm DOA l8 39 510Rtliahtldy 12mm 2 Slide 30 Yield Modeling Summary Seed s yield model give the highest projected yields 0 The Poisson yield model gives the lowest projected yields 0 The negative Binomial yield model with x 5 approach the exponential function 510 Leclum 122 Slide 31 Example Yield Histogram Q gt 0 39 b39 39 3 uth LGPESQ Z WLbQ Yield 22 510 Rtliahtmy Leclum 22 Slide 32 Reliability Reliability is the probability that a deVice a module or an assembly will not fail under operational conditions in service before the end of its lifetime The longer the required lifetime the greater the demands on reliability since the probability of failure increase with time Reliability is a measure of goodness subject to time dependent mechanisms that cause failures in components during eld use 510Rzliajzi1 g Lecture 22 SM 33 Bathtub Curve I L Expected or Observed Failure Rate Failure Rate gaqv Period T 0 Time gt 25 510Rzlia17ili9 Lecture 22 SM 34 Reliability of Layout Components Reliability of the Interconnect System The electromigration of Al and Cu interconnects The mechanical stress driven metal voiding The proposed use of low k materials as interlayer dielectrics and their impact on electromigration and the thermomechanical integrity of the interconnects Transistor Reliability Dielectric Breakdown Hot Carriers and Parametric Stability 510 Rell39abill39gv Latquot 22 Slide 35 Yield and Reliability Parameters that significantly affect Yield amp Reliability Design related parameters chip area interconnect design gate oxide width Process related parameters defect distribution and density Reliability Operation parameters temperature voltage 510 Rell39abill39gv Latquot 22 Slide 36 Yield and Reliability Reliability Operation related Reliability amp Yield Design and process related 510 Reliab l39gv Latquot 22 Slide 37 Yield Reliability Relation Model Yield and reliability are correlated with each other Yield contains a part of the information needed to predict reliability We can try to predict reliability based on yield 510 Rell39abill39gv Latquot 22 Slide 38 Yield Reliability Relation Model Different types of models Model that describes the defect level or the reliable fraction of products as a function of yield Drawback of such model These models can only be used to estimate the defect level after a final test Reliability model needs to be based on defect reliability physics and be a function of yield 510 Rell39abill39gv Latquot 22 Slide 39 Yield Reliability Relation Model Huston and Clarke s Model 1 Uses yield and reliability critical areas A RY4 Ar reliability critical area AC yield critical areas The reliability critical area needs to be calculated based on defect reliability physics 510 Rell39abill39gv Latquot 22 Slide 40 20 Yield Reliability Relation Model Kuper and Van der Pol Model 2 RYM Mgt09 M clustering effects and edge exclusions a By Dr density of reliability defects D Dy density of yield defects y The model is verified experimentally Strong relationship between yield and failure occurring in the early life time 510 Rell39abill39gv Latquot 22 Slide 41 Yield Reliability Relation Model Reliability is defined as the cumulative probability function at time t for a given time under the operating conditions But Model 1 aamp 2 are not related to time t Kuo and Kim Model 3 defined at time I based on the POF Physics of failure concept Rt gYt W Rt reliability at time t ct timedependent constant 510 Rell39abill39gv Latquot 22 Slide 42 21 Yield Reliability Relation Model Model 3 concentrates on the gate oxide reliability Provides a possible way to interrelate yield and burnin The decision to burnin or not burnin can be made by observing yield This is another way to avoid timeconsuming burnin 510 Rell39abill39gv Latquot 22 Slide 43 Bumin For mature products the initial reliability studies would have identified and eliminated failure processes so that steadystate failure rate meets or exceeds design goal However the manufactured devices still show existence of continuing early failure Generally manufacturing defects cause the infant mortality failures e g pinholes photoresist or etching defects resulting in nearopens or shorts 510 Rell39abill39gv Latquot 22 Slide 44 22 Burnin Contamination on the chip of the packages scratches weak chips or wire bonds partially cracked chips or packages The purpose of the burnin procedure is to operate the deVices for a time period during which most of the deVices that are defective will fail Infantmortality will decrease 510 Rell39abill39gv Latquot 22 Slide 45 Burnin The conditions during burnin presumably accelerate the failure mechanisms that contribute to infant mortality failure Studies of infant mortality under increased T conditions show that infant mortality have an activation energy of 037 to 042 eV 510 Rell39abill39gv Latquot 22 Slide 46 23 Yield and Reliability Modeling Yield Reliability Yo 21 Manufacturing process Field 39Observation 0 t Time b products that have a lower yield than products of a at the completion of the manufacturing process 0 a high reliability after the eld observation time t 510 Rellabllny Lecture 22 Slide 47 References 20 I A Wanger and I Koren An Interactive VLSI CAD Tool for Yield Estimation IEEE Trans On Semiconductor Manufacturing Vol 8 Special Issue on Defect Fault and Yield Modeling pp 130 138 May 1995 21 W Kuo and T Kim quotAn Overview of Manufacturing Yield and Reliability Modeling for Semiconductor Products Proceedings ofthe IEEE Vol 87 August 1999 22 Yield By Syed A Raza LSI LOGIC 23 Leachman Yield Modelling WWW ieor berkeley eduieor130yieldmodels pdf 24 Dr Charles Surya Reliaiblity and Failure Analysis of Electronic Components httpWWW eie polyu edu hkensuryalectnotesReliFailReliFailnotes htm 25 Paul A Tobias amp David C Trindade Applied Reliability CRC Press 2nd edition January 1 1995 26 A B Kahng B Liu I I Mandoiu Non Tree routing for reliability and yield Improvement vlsicad ucsd eduPublicationsConferencesc142 ppt 27 Karthik Subramanian Hamish Swaminathan Defect Modeling in Integrated Circuits WWW uta eduicdesign lesdefects doc 28 Khare J B Maly W Thomas M E Extraction of defect size distributions in an IC layer using Test Structure Data Dept of Electr amp Computer Eng Carnegie Mellon Univ IEEE Transactions on Semiconductor Manufacturing On pp 354 368 Aug 1994 29 Khare J B Daniels B J Campbell D M Thomas M E Maly W Extraction of Defect Characteristics for yield estimation using the double bridge test structure VLSI Technology Systems and Applications 1991 Proceedings of Technical Papers 1991 International Symposium on pp 428 432 510 Reliablluy Lecture 22 Slide 48 24

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