POWER ELEC SYS DE II
POWER ELEC SYS DE II ECE 446
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86 Part II Impedance Interactions in DC Distributed Power Systems E3 6RFgtKWL BIKE 87 Chapter 5 Impedance Interactions An Overview 51 Introduction In this chapter interconnections among DC power distribution subsystems are analyzed and an investigation is launched into how the performance of the global interconnection differs from that predicted by the analysis of each independent sub system Typical examples of these interconnections are a power converter with a dynamic load a power converter with an input line lter power converters connected in parallel or cascade and combinations of the above Most of the literature on the subject is focused on the problem of a power con 88 verter in the presence of an input lter but more recently the same ideas are being applied in the context of DC Distributed Power Systems DPS Every interface in any interconnection of power converters lters andor loads is subject to impedance interactions This is the case of DPS in particular the Intermediate Bus Architecture NBA in which an off line converter provides a mildly regulated DC line that is dis tributed among subsystems with Point Of Load POL converters providing voltage regulation in close proximity to the loads Typical applications for this architecture are communications systems data centers motherboards and even on chip power distribution networks A typical diagram for a DPS is shown in Fig 51 One or more ACDC converters with Power Factor Correction provide an intermediate DC voltage from the same or potentially different AC sources A battery can be present for power backup Many POL converters with their respective EMI lters feed independent or shared loads Some loads could even be connected to the intermediate bus directly In this diagram it can be appreciated that interfaces marked as A B and C are prone to impedance interactions and potential performance degradation The state of the art is such that it is very simple to check the overall performance and stability of an already engineered system by simulation or experimentation This is usually a system integrators job If a problem is encountered there is little possibil ity of modifying the internal dynamics of the converters As a consequence the most 89 Filter ACDC PFC I I Filter I DCDC Load ACDC PFC Figure 51 Typical DPS diagram likely outcome of this process is that the lters become oversized7 by the addition of capacitors7 inductors7 damping7 or some combination of these A literature review as well as an exposition of the most important aspects of this subject are presented rst in this chapter In the following chapter7 a contribution to the understanding of this problem using fundamentals of control systems theory is developed and the feasibility of reducing impedance interactions by control methods instead of physical design is explored 90 52 Literature review It was observed early in the development of the discipline of Power Electronics that certain power converters showed unstable behavior in the presence of an input lter 30 This problem was analyzed using newly derived averaged models in the mid seventies 31 A theoretical understanding of the phenomenon was consolidated and design guidelines were derived in order to guarantee the eradication ofthe problem in voltage programmed regulators 32 This contribution is usually referred to as the Middlebrook criterion Results were extended for current programmed regulators in 33 The solution proposed was based on adding damping to the input lter Op timization procedures were derived in order to minimize the size of the lter the power dissipation or some other quantity of interest while still achieving the desired damping 3435 In the eighties an input voltage feedforward scheme was proposed in order to mitigate the effects of the input lter 3637 This method is based on a zero pole cancellation that is dif cult to achieve in practice even using adaptive methods 38 This was however the rst attempt to solve the problem using control methods instead of modifying the physical design of the lter A practical overview of the problem of impedance interactions in the context of input lter interactions with a timeline of key papers can be found in 39 91 As scaling in IC technology increased density and speed7 DPS were proposed to meet the new power demands 10 This created new topologies of interconnected power converters and line lters in which impedance interactions at every interface could potentially degrade the performance of the system Analysis methods were extended and new design guidelines developed for this type of system 40744 Recent efforts have been made to measure the impedances online for the sake of analyzing stability and performance degradation due to the interconnection of power modules 4546 These methods allow users to analyze the systems and subsystems without knowledge of internal components It has been observed that a power converter is immune to impedance interactions at its input and output ports if it has both an output impedance and a forward voltage transfer function equal to zero 47 These conditions are not possible to achieve in practice A system level approach has to be undertaken to guarantee an overall stability and performance objective 53 Problem description Traditionally a power converter is designed under the assumption that there exists an ideal voltage source at the input7 as shown in Fig 52 In this case7 it is clear that variations in the input current in due to7 for example7 load variations will not affect the input voltage Vm It can be said that the input and the output of the converter 92 Load Input V Load Vs Filter Vm D C Figure 53 DCDC converter with an input lter are decoupled Now consider the system in Fig 537 in which an input lter is added This input lter can be an EMl lter or the output impedance of another power converter When in changes7 a perturbation in the input voltage Vm will occur due to the output impedance ofthe input lter This creates a new feedback loop that can affect signi cantly the dynamics of the converter7 in some cases degrading its performance or even resulting in instability The interaction between the impedances can be analyzed by using as an illustrative example the model shown in Fig 547 where Z is the output impedance of the input lter7 and Zl is the input impedance of the power converter The effect of a 93 Figure 54 Equivalent circuit of a power converter connected to an input lter perturbation in the input voltage Vm as a function of a change in the load current re ected to the input of the converter LT is WW I L39r Zo 7 52 1ZOYi where K is the input adrnittance This means that a new feedback loop7 sometimes called the small loop 7 is established The stability of this loop can be analyzed by applying the Nyquist criterion to ZoYi ln general7 the feedback loop created by the connection of two n ports systems can be analyzed as a MIMO dynarnic feedback system This interpretation is presented in 48 in the context of the small gain theorern7 which gives a suf cient condition for the stability of the feedback system Necessary and suf cient stability conditions for dynamic feedback systems are given in 49 In the special case of the interconnection of two one ports which are stable7 the feedback system is stable if and only if the zeros of 1 Z1Y2 have negative or zero real part7 where Z1 and Y2 are the impedance and 94 admittance of the two one ports respectively In conclusion the Nyquist criterion applied to ZOYZ as in 52 is a necessary and suf cient condition for stability of the interconnection of stable one ports This is a very useful result because in practice most of the circuits interconnected in a DPS are stable Stability of the interconnection is critical but from an engineering perspective performance should also be analyzed Even if the loop is stable it can still affect signi cantly the dynamics of the power converter and degrade its performance The analytical tools for analyzing the performance will be given in the next section Example Buck converter with LC input lter The ideas exposed above are illustrated here with a simple but important example Assume a buck converter is controlled such that the output power is constant This could be the case for example if the load is resistive and the converter regulates the output voltage The closed loop input impedance over the controller bandwidth is then computed as follows First the input power is expressed as a function of the output power and the ef ciency 53 95 VMIM const 1m Figure 55 Negative input impedance of a constant power converter Then the small signal input impedance is computed as the partial derivative of the input voltage with respect to the input current V010 V 771m 5394 an V010 7 55 gt6i 771 Finally by substituting m D10 buck converter and 14 BL resistive load the following result is obtained RL Z 7 56 W lt gt This negative input impedance can be seen graphically in Fig 55 as the slope of the Vimfm curve The impedance depends on the operating point Now assume the converter is connected with an LC input lter like the one depicted 96 Lf Rd Figure 56 Input lter in Fig 56 The output impedance of this lter is Z Lfs RdcResOf 1 0 LfOf82RdCR55OfS139 The stability of the system can be analyzed by computing explicitly the transfer function 52 For simplicity of notation7 77 is assumed to be equal to unity Then Vm Zo 7 58 IL ZOYl39 7 Lfs RdchesOfS 1 E 9 7 DZRES D2RESR C D2L D2R CU lt17 RL gtLf0f82ltRdcResiR Ldgt0fi RLfls17R Ld Applying the Routh Hurwitz criterion to the denominator of this expression7 a stability condition can be derived Usually lt1 7 D2112 and lt1 7 D2L4gt are positive Assuming the latter7 the stability condition can be written as R Rd L R0 R597D2gtO iDZ f 0 510 lt d RL f RL gt BL 23 RBSRC Z 511 gt D2gt lldResRdc QC where Z3 3 and Q RZTCRd This is equivalent to say that the magnitude of 97 the input impedance of the converter has to be larger than the peak of the output impedance of the LC lter at the resonance frequency This is consistent with the Nyquist criterion7 because at that frequency the term ZOYZ has an angle of 180 and needs to have a magnitude less than unity in order not to encircle the 10 point This example is valid as long as the controller bandwidth of the converter is high enough such that the constant power assumption holds for the resonant frequency of the LC lter More exact7 but also more complicated results can be obtained by computing the closed loop input impedance of the converter based on a small signal model 54 Middlebrook criterion The Middlebrook criterion is a suf cient condition for guaranteeing the stability of two interconnected systems Moreover7 the criterion also guarantees that no per formance degradation occurs due to the interconnection Following this criterion7 the designer can effectively decouple one module from its source or load impedance The derivation of the criterion can be better understood by applying the Extra Element Theorem EET 50 The EET is used when a transfer function for a system is known and an additional element is connected to one port of the system7 modifying the original transfer function The setup is shown in Fig 57 Suppose the transfer function Tuny is known when there is no impedance Z connected to the port in system 98 Z Figure 57 The Extra Element Theorem G either Z 00 or Z 0 When the impedance is connected7 this will naturally affect the transfer function The EET postulates that the new transfer function will be 1 Tuaylz Tuaylzgx 1gzi 53912 1 21 Twylm 513 where Z Zmlyno 514 515 and Zd Zinluo The two new quantities that need to be computed are the input impedance of the port under special circumstances For computing Z the input variable u has to be set such that the output variable y vanishes notice that this is not the same as shorting the output For computing Zd the input variable u has to be set to zero In the case of a converter with an input lter7 the port would be the input port of 99 the converter and the impedance to add would be the output impedance of the input lter Z0 Since this impedance is usually assumed to be zero the effect of a non zero impedance can be analyzed by using form 513 of the BET The transfer functions of interest would usually be the output impedance of the converter the duty cycle to output voltage or the audio susceptibility transfer functions The duty cycle to output voltage transfer function Tdnvo will be analyzed next as an example To compute Z the duty cycle has to be set such that the small signal output voltage vanishes This is usually the control objective voltage regulation so it can be concluded that Z is the ideal closed loop input impedance ofthe converter ZicL ideal in the sense that would achieve perfect regulation over all frequencies To compute Zd the duty cycle has to be set to zero which means that the converter operates in open loop Therefore Zd is the open loop input impedance of the converter ZiOL By substituting into 513 the following result is obtained 1Zr 200 1 ZZO i TdH Lo lzo TdH39Lol This result is exact and predicts the effect of the input lter in the dynamics of the converter Based on this result Middlebrook established the simple although conservative design rule that is today known as the Middlebrook criterion and can be stated as follows The dynamics of the converter will not be signi cantly affected by an input lter if lZOl ltlt lZle and lZOl lt Zle 100 1 C v0 ltgt RL Figure 58 Small signal model of a buck converter with resistive load This criterion can be immediately understood by looking at 516 the conditions imply that the multiplying term that affects the transfer function is close to unity If the dynamics are not affected7 then clearly stability and performance of the converter are preserved It is also evident that the criterion is a suf cient condition that can potentially be very conservative Example Applying the BET to a buck converter with input lter In the case of a buck converter7 whose small signal model is shown in Fig 587 the duty cycle to output voltage transfer function is 110 1 TH Vm d 0 dwo L052RA51 L 517 In order to apply the EET7 it is necessary to compute the open loop and ideal closed loop input impedances The former is 2 L ZOL 2 L 05 1375 H 518 l 2 H D2 RLOs 1 101 while the latter needs to be computed by setting the duty cycle such that it cancels the output voltage7 namely d 7 Um Then CL in RL in d D mum Finally7 we can apply the BET as stated in 513 to obtain the duty cycle to output voltage transfer function when we connect the input lter of Fig 56 1 7 13 2 L SRdcREsC 1 RL Lfcf92RdcRESCfs1 TdH V 520 M m 2 A 13 2 R09 M L05 f EL 1 HM Lfcfsu dcmgucfs After some algebra the expression can be reduced to MS Thu Vm 521 d 0 MS where Res Restc Lf Rdc N 17D2 gtL o 2 120 R597D2 gtO iDZ l 17D2 5 lt BL f f5 d BL f BL 5 BL 522 and Ds LfofLOs4 L Lfof PL L D2R550gt Rdc R59 OfLol 53 R LO 1 D2 59 l f flt BL Rchesgt RL gtLoLofw L DZLfo DszcResoof 52 ltRes i Rdc i D2 Rdc RL 39 L DZL g DZRdCO 5 RL 1 D2 523 102 Although the denominator of the expression does not add much insight into the problem7 the numerator shows an interesting fact Comparing 522 with the de nominator in 597 it can be concluded that the zeros of the duty cycle to output voltage transfer function are equal to the poles of the closed loop transfer function computed in the previous section under the assumption of perfect regulation This is consistent with control theory results7 namely that under the condition of in nite feedback gain the poles of the closed loop transfer function are equal to the zeros of the plant More importantly7 this example shows that instability of the closed loop system is related to the existence of right half plane zeros in the plant7 and that those zeros are introduced by the input lter An illustration of the effect of an input lter in the dynamics of a buck converter is shown in Fig 59 The top two graphs show the bode plots in the case of a damped input lter Since lZl lt lan lZdl ie7 the Middlebrook criterion is satis ed the plant transfer function Tdnvo presents its characteristic second order shape7 unaffected by the input lter The bottom two graphs show the case of an undamped or lightly damped input lter The plant transfer function shows the effect of the input lter resonance7 leading potentially to a degradation of performance and even instability 103 20 Zn 30 Tdav u 10 20 o 10 1o 0 2o 30 Z 10 40 2o 103 10 1o5 106 107 1o3 10 1o5 106 107 z 20 n 30 Tdavu 1o 20 o Zd 10 1o 0 20 1o 30 Z 40 20 w av 103 10 1o5 106 107 1o3 10 1o5 106 107 Figure 59 Effect of input lter in buck converter dynamics Top Damped input lter Bottom Undarnped input lter 104 55 Modeling When designing the control system of a power converter it is standard practice to derive a small signal model and from there extract the transfer functions of interest for example the duty cycle to output voltage transfer function duty cycle to inductor current transfer function output impedance etc If the converter is connected to a source or load impedance these transfer functions are not valid any longer as explained in the previous sections There are many ways to deal with this 1 Assume the Middlebrook criterion is valid and ignore impedance interactions 2 Derive the new transfer functions using the extra element theorem 3 Include the impedance in the small signal model and derive the transfer func tions for the new model In the design process the rst option is probably the only feasible one since the complexity of the other approaches is too high for a designer However if the purpose is to simulate and validate a controller design there is no need to recompute the transfer functions A two port model of the converter based on the small signal model can be derived and connected to the impedance for simulation Any type of two port model would work however the nature of DCDC power converters is such that in closed loop it is more useful to see the input voltage and output current as independent variables inputs77 to the system while the input 105 Um tin 2 0 a G 710 d a ZL Figure 510 DCDC converter model current and output voltage are dependent variables outputs77 of the system This leads naturally to a hybrid parameter model In two port models in which one of the ports can be naturally identi ed as input77 and the other as output some authors make the distinction between the two possible types of hybrid models that can arise Following this convention7 the so called inverse hybrid parameter7 or G parameter model was proposed 5152 A derivation of this type of two port model is shown next Suppose the converter has a small signal linear7 multivariable model G depicted in Fig 510 The inputs are the input voltage mm the output or load current 2390 and the duty cycle d The outputs are the input current 2 the output voltage 110 and the inductor current Q The latter is useful in the context of current mode control7 otherwise it could be obviated This system can be completely described by the following set of equations 2 Gi m Gi o Gidd v0 Gavinwmowwd 524 Zr GL m GL o Gde 106 Figure 511 DCDC converter model with feedback controller K Zin Z0 71m Gquot 710 Figure 512 Two port model of a closed loop DCDC converter When a feedback controller K is connected Fig 5117 the closed loop converter becomes a two input7 two output system that can be represented as a two port system Fig 512 Here the system G represents the closed loop converter The system can be described by the following set of equations 2 GfuvinGfi 0 525 10 G2v inG2 0 For simulation purposes7 however7 the transfer functions of the closed loop de scription do not need to be computed An internal description like the one inside the dashed box in Fig 511 can be used A less compact7 but more realistic circuit 107 iin i0 G 120 d a iL Figure 513 DCDC converter with input lter Multivariable model case description7 like the one in Fig 58 can also be used7 although in some systems it could consume more computational resources The advantage of two port models arises when subsystems need to be intercon nected7 in particular when there are many subsystems in series or parallel For example7 consider a converter with an input lter In the multivariable model of Fig 5107 the lter could be accommodated by including a feedback loop with the output impedance of the lter Z07 as depicted in Fig 513 It is assumed that the only small signal perturbation at the input of the converter is due to perturbations in the input current7 interacting with the output impedance of the lter Now7 suppose the input lter is connected to the output of another converter7 for example an ACDC converter To include the effect of this cascaded interconnection7 it would be required to compute the output impedance ofthe lter under the presence of the ACDC converter7 and then to substitute this value instead of Z in the gure For every additional subsystem interconnected to the network7 all impedances need 108 Vst Z 2 0 v0 Figure 514 DCDC converter with input lter Two port model case to be recornputed Compare this scenario with the two port model case The input lter can be included using its own two port rnodel Z as shown in Fig 5147 and its input port connected to a DC voltage source VS7 or equivalently a short circuit If a new converter is connected to the input of the lter7 the voltage source can be replaced by the output port of this new converter and no modi cations are needed to the lter rnodel No matter how complex the interconnections7 the two port model allows for a topological connection that is identical to the circuit without needing to recornpute any of the models Hence7 it can be concluded that two port mod els are more convenient than rnultivariable models for simulation and veri cation of interconnected systems It should be noted7 though7 that the srnall signal model described so far depends on the large signal operating point of the converter Therefore7 when the converter is connected to a load or a source irnpedance that changes the operating point7 the converter rnodel needs to be recornputed The general form of the equations7 though7 does not change because only the values of some parameters are modi ed 109 Figure 515 Srnall signal model of buck converter with parasitic resistances Example Twoport model of a buck converter In the case of a buck converter7 the traditional averaged srnall signal model as shown in Fig 58 without the load resistance BL is simple enough to be used in simulations as a two port model The canonical G pararneter model is derived here for completeness The parasitic resistances of the inductor and the switches Rim and the capacitor R55 are also included in the derivation The srnall signal model of reference is shown in Fig 515 There are nine transfer functions to be derived in accordance with 524 These Zquot 05 Gm D2 526 in dioo L082 Rdw BEST 05 1 Z39m Pumas 1 GM D 53927 20 LoszltRRos1 lt gt 2 L052 Rdcr Rm 05 1 GM Io O d Uinio0 L082 Rdw REST 05 1 10 RESTOS 1 G U U D 39 Um dioo L052 Rdw REST OS 1 Gidd 110 Figure 516 Implementation of the G parameter two port model Open loop case Gui G39ud GL1 GM GLd W0 2 0 W0 3 Zr in Zr Z ZL d um d0 umzoo dio 0 um d0 umzoo i L5 l Rdc39r Ramos l 7 L052 Rm Rm Os 1 7 V Ramos 1 Cs D L052 Rm Rm Os 1 7 Ramos l 1 7 L052 Rm Rm Os 1 05 L052 Rm Rm Os 1 L052 Rum R Us 1 530 531 532 533 534 The circuit representation of this model is shown in Fig 516 The feedback loop can be incorporated with an additional circuit that generates the duty cycle d If current mode control is used7 the current Z39L can be generated using 5327534 This example shows a method to derive a canonical two port model for a DCDC converter ln closed loop operation7 a canonical model can also be obtained by trivial although complicated algebraic manipulations ln practice7 the model could also be extracted from measurements This means that a canonical model for a converter operating in closed loop can be obtained from measurements even when the internal 111 Figure 517 Implementation of the G parameter two port model Closed loop case characteristics are unknown black box The transfer functions to be obtained7 according to 525 are only four7 namely G input admittance 535 lnio0 G inverse current gain 536 0 um0 G voltage gain 537 lnio0 G output impedance 538 0 umo The equivalent circuit is shown in Fig 517 A system integrator could bene t from this approach when all or most of the subsystems in a DPS are modules whose internal behavior is unknown Each one of them can be characterized by measuring these four transfer functions and the overall performance of the system can be predicted by simulation 112 56 Conclusions In this chapter7 the problem of impedance interactions between interconnected power converters andor passive circuits was presented The basic results in this area were described7 as well as the context in which the results were developed A buck converter with an input lter was used as a representative example to illustrate the main ideas The next chapter will address this problem from a different perspective7 exploring the fundamental issues that arise in this area and the feasibility of using control methods to preserve performance and stability of interconnected systems 113 Chapter 6 Mitigation of Impedance Interactions In this chapter7 the possibility of improving the performance of interconnected power converters andor lters by using control methods instead of physical design is explored First7 some fundamental limitations are exposed Different controller design methods are explored and compared Finally7 an example of the use of system level design to mitigate impedance interactions is presented 61 Limits of performance It has been observed that an undamped input lter adds a pair of complex conjugate right half plane zeros to the duty cycle to output transfer function of the 114 converter 35 This observation is in accordance with the example shown in Sec tion 54 A RHP zero in the feedback loop is known to impose serious limits in the achievable performance of the closed loop control system 53 In general the loop bandwidth should be less than half the frequency of the zero in order to preserve stability In many applications the resonant frequency of the input lter is less than the resonant frequency of the output lter which in turn is less than the desired band width As a consequence the RHP zeros introduced by the input lter will invariably cause instability in closed loop operation It can be concluded that under the pres ence of the RHP zeros the performance requirements of the application expressed for example as a high loop gain over the desired bandwidth are not compatible with stable operation It is for this reason that the most common solution to the problem is the addition of damping to the input lter which moves the zeros from the RHP to the LHP When considering a power converter with an input lter the converter7s input voltage changes with its input current as described in the previous chapter This voltage could be used as a controller input In this case the controller would have two inputs output voltage and input voltage and one output duty cycle In a MIMO system like this the role of zeros is not as straightforward as in the SlSO case because there is a spatial direction added to the frequency dimension In particular the limits 115 of performance imposed by RHP zeros are more dif cult to analyze 54 Therefore the RHP zeros in traditional output voltage feedback control impose a fundamental limitation in the performance of the system but more caution should be taken when discussing control with input voltage feedforward In this chapter although no de nitive answer is attempted in this regard an exploration of a large set of controllers with input voltage feedforward seems to indicate that the same limits of performance for SlSO systems are valid in the MlMO case for this application 62 Robust design of controllers In this section a robust design procedure is introduced in order to explore possible control schemes that could meet the performance and stability requirements of a representative VRM application under the presence of an input lter It is shown that there is no stabilizing controller that can achieve high loop gain at the resonant frequency of the input lter The section is organized as follows First a model of the plant a buck converter with an input lter is presented in Section 621 The model includes uncertainty in the characteristics of the input lter In Section 622 the plant is analyzed using the Middlebrook criterion introduced in Section 54 revealing that for some parameter values the criterion is not satis ed and RHP zeros are introduced A traditional PlD control design is presented in Section 623 and its stability is analyzed In 116 Section 624 input voltage feedforward is introduced7 showing stable operation with nominal parameters but instability for some parameter values A p synthesis design is presented in Section 625 that aims to nd a controller that could achieve both stability and good performance under the presence of uncertain parameters in the input lter Finally7 in Section 6267 conclusions are presented 621 The plant A diagram of the control system of a DCDC converter using voltage mode control is shown in Fig 61 The box labeled G represents the dynamics of the converter The small signal input voltage is generated by the presence of an input lter of output impedance Z0 Adaptive Voltage Positioning AVP is achieved by subtracting the reference impedance Zref times the output current 2390 from the reference voltage UT As an example7 the generalized output impedance approach as de ned in 9 is used7 meaning that Ramos l 1 275 R 39 f LL RLLOS1 61 The box labeled K corresponds to the controller that generates the duty cycle command d based on the error voltage 15 An input voltage feedforward path is included also in order to explore a richer set of controllers The converter7s model can be obtained based on 5267531 However7 in this chapter a resistive load BL is also included in order to explore different operating 117 Figure 61 Voltage mode control of a DCDC converter with load line and input voltage feedforward7 in the presence of an input lter conditions This generates a terrninated77 rnodel7 in which the following transfer functions de ne block G according to Fig 62 D2 1359708 1 6 2 Rdw RL L052 RdCTRL f REISa VdRlefis erCT CLs 1 39 RL RWOS1 6 3 Rdw RL 231 L052 RdmRL l REsrRlefiserm CLs 1 39 Dm 1 Rm BL Os 1 Rdw RL 231 L052 RdCTRLRE TdIEij IIESTRdCT 0LS 1 39 D RL RWOS1 6 5 Rim BL gzigi L052 W5 1 39 BL Ls Rm Pumas 1 6 6 Rdm BL L052 RdCTRLRE dfTLjI IfsTRdCT CLs 1 39 R R5970 1 Vin L 5 1 67 R R Rmmz 2 RdmRLRmRLRdemCL do L RdmfRL L08 RdmfRL 8 1 For a representative VRM application7 the component and parameter values are 118 Figure 62 Internal structure of block G presented in Table 61 The table also includes the speci cation of the load line RLL and the range of output currents The switching frequency and the desired bandwidth are also speci ed The input lter corresponds to the one shown in Fig 56 Table 62 shows the lter component values In both tables7 the range of variation for selected parameters is also indicated The purpose of this study is to analyze the effect of the input lter on the dynamics of the converter7 therefore only the lter parameters and the operating point are allowed to change7 while the converter parameters are assumed constant In order to simplify the forrnulation7 the frequency and damping of the input LC lter are changed by variations in the capacitors pararneters only 119 Table 61 Representative VRM application values ComponentParameter Nominal Value Range of Variation Vl 12V 10 7 13V Wef 12V 08 713V L 100nH Rdw 17719 O 800uF R55 1m 2 RLL 1257719 IO 100A 1 7 120A fS 1MH2 BW SOkHz Table 62 Input lter values Component Norninal Value Range of Variation Lf SOOnH Rdc 017719 Of SOOMF 200 7 37 OOOMF R55 17719 2 7 207719 120 622 Preliminary analysis Applying the Middlebrook criterion to this system7 it can be seen that the stability conditions are not met for some input lter parameters in the range speci ed This is illustrated in Fig 637 showing the Bode plots ofthe input impedance ofthe converter G121 at a high load condition and the output impedance ofthe input lter Z0 A set of plots for Z are shown corresponding to a representative set of input lter parameter variations The input lter resonance is not damped enough in some cases and the peak becomes larger than the input impedance of the converter It is expected7 from previous analysis7 that the system would be unstable if the bandwidth of the loop is above the input lter resonance for those particular sets of parameters This problem formulation is a good candidate to explore to what extent the use of input voltage feedforward and robust design techniques could overcome the funda mental limit of performance observed in the traditional SlSO controller design 623 PID feedback design In this design7 the controller K shown in Fig6l has the feedforward path from Um to d equal to zero7 and the feedback path from Us to d is designed using standard control techniques The input lter is assumed to be absent7 implying that the loop to be designed is formed by the series connection of the controller K and the duty cycle to output voltage transfer function Gm which will be referred to as the plant The 121 Bode Diagram Magnitude dB M xm ii i i i i i i i i i m 105 10 107 Frequency radsec Figure 63 Magnitude of the input impedance of the converter G121 compared with the magnitude ofthe output impedance of the lter Z for a set of different parameter values 122 Bode Diagram Magnitude dB Phase deg A m I go o L o m L as a l 1oE Frequency radsec Figure 64 Feedback PlD design Bode plot of the controller dashed line7 the plant dash dotted line7 and the resulting loop gain solid line design is performed under the most demanding situation7 which is at high load The PlD controller has one pole at the origin7 two zeros located in the proximity of the plants double pole7 and an additional pole located in proximity to the ESR zero introduced by the output capacitor The Bode plot of the controller7 the plant7 and the loop are shown in Fig 64 The bandwidth is around 85kHz and the phase margin 80 The design appears to be adequate7 however when the input lter is connected 123 Nqust Diagram Fiom ve To v0 l ya aquot A 9 3 imaginary Axis A l 5 Real N s Figure 65 Set of Nyquist plots of the feedback PlD design for different input lter parameters and the new loop gain computed for example using the extra element theorem instability is revealed in the set of Nyquist plots of Fig 65 For each input lter parameter value set a different Nyquist plot is shown Some of the plots encircle the 710 point revealing instability This is not surprising since it was predicted in the previous section 124 624 Input voltage feedforward This design is based on that in 36 The feedback controller is the same PlD as in the previous section7 but an input voltage feedforward path equal to 7V3 is added The controller K7 as shown in Fig 61 has now two inputs and one output This ideally cancels out the effect of any input lter in the loop gain However7 this is equivalent to a RHP zero pole cancellation that hides the instability such that it is not observed at the output A slight deviation from the ideal conditions reveals the instability in the output of the system The Nyquist plot ofthe loop under variations in the input lter is shown in Fig 66 Comparing with Fig 65 it can be appreciated that the feedforward term effectively cancels the effect of the input lter in the loop7 which appears now to be stable However7 when the input voltage is allowed to change in addition to the variations in the input lter7 the feedforward term is not ideal anymore and the Nyquist plot of the loop becomes the set shown in Fig 67 In this case it can be seen that the system is unstable for some set of parameters in the range of variation7 as evidenced by the encirclement of the point 717 0 625 u synthesis design The examples in the previous sections illustrate that the RHP zeros impose a fundamental limitation in the conventional design of controllers for DCDC convert Nqust Diagram From ve To v0 imaginary Ms 0 Figure 66 Nyquist plot of the feedforward design under ideal conditions 125 126 Nqust Diagram Fiom ve To v0 imaginary Ms 4 6 Reai N s Figure 67 Nyquist plot ofthe feedforward design with variations in the input voltage 127 ers with an undamped input lter To con rm this7 a larger set of controllers is explored by using the p synthesis algorithm available in the Matlab Robust Control Toolbox 55 The idea is to try to nd out if there exists any controller K that could achieve stability and adequate performance under the constraints of the problem In order to proceed with the controller design7 the problem has to be posed as a norm minimization problem The following setup is based on the methodology described in 56 and 55 The system setup is shown in Fig 68 The inputs to be considered are the voltage reference 1 and the output current 2390 while the main output of interest is the error voltage 05 In order to penalize the amplitude of perturbations in the input voltage and to comply with well posedness conditions7 the input voltage Um and the duty cycle command d are also included as outputs respectively The model is valid up to half the switching frequency7 so the uncertainty due to the switching action is included by adding an extra perturbation input Us at the output of the plant All these signals have to be weighted in order to constrain the problem with realistic speci cations The dashed box indicates the controller location7 to be synthesized by the designer or the control design algorithm The system7 then7 has the form indicated in Fig 69 The controller K has two inputs and one output7 and is to be designed in order to minimize the H00 norm of the transfer function from the inputs 1172390705 to the outputs 1757173 under all 128 Ur 10 USE iv Figure 68 System setup for robust control design Wz39 W5 129 Figure 69 Simpli ed system setup for robust control design parameter variations7 while preserving stability For this application7 the weighting functions used to shape the systems response are shown in Figs 610 and 611 for the inputs and outputs respectively The weights at the reference inputs 1 and 2390 represent the bandwidth of the signals to be tracked The weight in the perturbation Us represents the uncertainty at frequencies above half the switching frequency On the other hand7 the weights at the outputs represent the desired bandwidth of the system as well as the relative importance of the different signals The p synthesis algorithm was run on a system with uncertainties in the input lter and the input voltage The code is presented in Appendix C The Bode plot of the controller synthesized is shown in Fig 6127 compared with the controller of the Magnitude dB Magnitude dB Magnitude dB Wr Bode Plot 80 i i i i 105 10 107 1o 10 1o FregX egg er1IE1tselt 20 i mm 105 106 1o7 10 10 10 FreWSr yd 39Big ec 0 mm i 102 103 104 105 106 107 108 109 10W Frequency radsec Figure 610 Weighting functions for the inputs 130 Magnitude dB Magnitude dB Magnitude dB 6 O i 131 We Bode Plot 10 104 105 106 107 1o 10 1o FrveE fi 39Eigfe 1o7 10 10 10 105 106 Fre e d ec Wd ngyderBIO 1 I N o o 103 104 105 106 107 108 109 10W Frequency radsec Figure 611 Weighting functions for the outputs 132 previous section PlD feedback and input voltage feedforward It can be seen that the M controller has a much lower gain7 especially in the region of the resonant frequency of the input lter The loop transfer function Bode plot is shown in Fig 613 and the Nyquist plot in Fig 614 The loop magnitude is less than OdB for all frequencies7 this means that effectively the feedback loop is not present and performance of the system is very poor As evidenced by the Nyquist plot7 the system is stable One possible interpretation of this result is that the controller tries to suppress the frequencies in which an abrupt phase change occurs due to the undarnped lter As a consequence7 the Nyquist plot does not encircle the point 710 because the magnitude of the loop transfer function is less than unity 626 Conclusions It can be concluded by the previous analysis and the examples shown that there does not seem to be a control strategy that permits a stable operation of a DCDC converter with an undarnped input lter7 while achieving a bandwidth above the resonance of the lter The strategy of damping the input lter that is standard practice at the present seems to be the only feasible solution to the problem The next section proposes an alternative way of damping the input lter without using physical resistors 133 Etude Diagram mm mm me ma To own Magnitude an Phase deg BED wan Ta cum l l lEl w w Um U2 Frequency radsec Figure 612 Bode plot of the u controller solid compared with the PID controller dashed Left error voltage to duty cycle transfer function Right input voltage to duty cycle transfer function Top magnitude Bottom phase 134 Bode Dlagram From ve To v0 Magmtude dB 0 Frequency radsec Figure 613 Set of Bode plots of the loop with the M controller for different input lter parameter values 135 Nqust Dlagram From ve To v0 magmarym Real N s Figure 614 Nyquist plot of the loop with the M controller for different input lter parameter values 136 ACDC Filter DCDC Load PFC Figure 615 Simple DPS architecture 63 Virtual damping of input lter It has been shown in the previous sections that the presence of an input lter in a power converter under certain conditions could affect the stability of the system7 and no control strategy in the converter can solve the problem The most a control system can achieve is to stabilize the system at the expense of performance In this section7 a different approach from a systems perspective is explored Consider the simple DPS architecture shown in Fig 615 A front end converter performs power factor correction PFC and provides a mildly regulated DO bus A point of load POL DODO converter provides a tightly regulated voltage to the load from this intermediate bus An EMl lter is used at the input of the POL converter to reduce the frequency content of its input current It has been shown that the effects of the lter on the dynamics of the POL converter can be reduced by adding damping Instead of adding physical damping7 the output impedance of the front end converter can be adjusted to provide the necessary damping The idea is illustrated in Fig 616 The output impedance of the front end converter can be made resistive R0 over a wide frequency range in 137 T Figure 616 Equivalent circuit of simple DPS architecture order to damp the input lter and counteract the negative input resistance of the POL converter 7RD 7 The system can be viewed as two two ports interconnected one is the lter with impedances ZA and Z3 and the other one is composed by the two independent resistances 7RD and R0 However the system can also be viewed as two stable one ports interconnected one is the lter with resistance R in series and the other is the DCDC converter with impedance 7RD This permits a simpler yet still rigurous analysis because the special case described in Section 53 can be used The location of the zeros of 1 7 ZBYL with YL R determine the stability of the interconnection lmpedance ZB can be computed as 1 ZB Lfs Rdc Bo ll Res 68 Lfs Rdc Bo RESOfS 1 6 9 LfOfSZ Rdc l Res Bo Cfs 1 39 Stability can be analyzed using the Routh Hurwitz criterion on the numerator of 138 1 7 ZBYLT7 which is Res R59Rdc Bo Lf Rdc R0 17 LC 2 R0 R0 R597 07 177 lt RLTgt f f8 d RL f BLT 8 RL 610 The coef cient lt1 7 52 is positive for representative values of the parameters7 but the term lt1 7 g i R may not be always positive depending on the value of R0 The stability conditions can be written as R 0 R0 lt17 L gt 0 and 611 RL 1110 R0 Res 7 w Of 7 Lfl gt 0 612 RL RL These conditions impose bounds on the values of R0 Z 7 RBSRL 7RCltR0ltRT7RC 613 RLTiRBS d L d Under the usual assumptions that BL gtgt 13551110 the expressions can be simpli ed to the following 25 RL 7 Res Rdc lt R0 lt BLT Notice that the most constrained case is given by the lowest value of BLT ie7 under a high load condition For the typical values reported in Tables 61 and 627 the assumptions are valid and the worst case value for BLT is 64077197 then the bounds would be 147719 lt R lt 6407719 615 139 The designer has a wide range of options for selecting R0 The circuit in Fig 616 was simulated using LTspiceSwCADlll 57 The value for BLT used was 6407719 and the input lter values were taken from 62 A voltage step was introduced at the input and the capacitor voltage was observed Several values of R0 were used7 spanning the range indicated in 615 The results are shown in Fig 617 and corroborate the theoretical results For R0 17719 the system is unstable For R0 147719 it is marginally stable For R0 2207 and 5007719 the system is stable with different damping characteristics For R0 6407719 and above the system becomes unstable These results are in agreement with the range predicted in 615 64 Conclusions This chapter has analyzed the input lter problem from the fundamentals of con trol system theory It has been illustrated by examples that there exist fundamental limits to the performance of a DCDC converter in the presence of an undamped input lter The only stabilizing controller that could be found using an optimizing algorithm was shown to have poor performance due to the fact that it suppresses the frequency range in which the input lter resonance occurs A virtual damping technique has been proposed that allows for stable operation without compromising the performance of the system The technique is based on 140 1mQ 14mQ i I 0 WI II39IWIVI IVIWIVI W WIW WI 0 0001 0002 0003 0004 0005 0006 0007 0008 0009 001 5 i i i i i i i i ZmQ A A A u vvv v v V Y i i i i i i i i 0001 0002 0003 0004 0005 0006 0007 0008 0009 001 i i i i i i i i i ZOmQ n V i i i i i i i i i i 0 0001 0002 0003 0004 0005 0006 0007 0008 0009 001 E i i SOOmQ n i i i i i i i i i i i 0 0001 0002 0003 0004 0005 0006 0007 0008 0009 001 an i i i i i i i i i 640m0 n 0 1 700m 100 50 n i i i i i i i 0 0001 0002 0003 0004 0005 0006 0007 0008 0009 001 5 Figure 617 Simulation of the Virtual damping example with different values of R0 Response to an input voltage step 141 a system level design in which the system interconnected to the input of the input lter has a resistive output impedance Simulations corroborate the design equations derived analytically ln DPS designs techniques like the one described above could be used to guarantee stability and performance of the interconnection without adding physical components that increment the size weight and cost of the system 149 Bibliography 3 U K F 1 E Stanford Power technology roadmap for microprocessor voltage regulators77 in Applied Power Electronics Conference 7 Plenary Session 2004 G E Moore 1965 Moore7s law Intel Corporation Online Available httpwwwintelcomtechnologymooreslaw 2005 Executive summary International Technology Roadmap for Semiconduc tors Online Available httpwwwitrsnetLinks2005lTRSExecSum2005 pdf 2006 Energy Star US Environmental Protection Agency and Us Department of Energy Online Available httpwwwenergystargov X Zhou P L Wong P Xu E Lee and A Q Huang Investigation of candidate VRM topologies for future microprocessors IEEE Tran on Power Electronics vol 15 no 6 Nov 2000 6 R Redl B Erisman and Z Zansky Optimizing the load transient response E E E l10l l11l l12l l13l 150 of the buck converter in Proc IEEE Applied Power Electronics Conference vol 1 1998 pp 1707176 2005 Apr Voltage Regulator Down VRD 101 Design Guide Intel Corp Online Available httpdeveloperintelcomdesignPentium4guides 302356htm E Stanford Power delivery challenges in computer platforms in Applied Power Electronics Conference 7 Plenary Session 2006 A Peterchev and S Sanders Load line regulation with estimated load current feedforward Application to Voltage Regulation Modules in Proc IEEE Power Electronics Specialists Conference 2004 S Luo and l Batarseh A review of Distributed Power Systems part 1 DC Distributed Power System IEEE Aerospace and Electronic Systems Magazine vol 20 no 8 pp 5716 Aug 2005 J D Shepard Power electronics futures in Proc Applied Power Electronics Conference 2004 N Andrews The global market for power supply and power management le in Proc Applied Power Electronics Conference 2002 H Forghani Zadeh and G Rincon Mora Current sensing techniques for DC ll4l l H E ll6l ll7l ll8l ll9l 151 DC converters7 in Proc IEEE International Midwest Symposium on Circuits 55 Systems7 2002 R Lenk 1999 Application Bulletin AB 20 Optimum Current Sensing Techniques in CPU Converters Fairchild Semiconductor Online Available httpwwwfairchildsemicomanABAB 20pdf Y Zhang7 R Zane7 A Prodic 7 R Erickson7 and D Maksimovic 7 Online calibra tion of MOSFET on state resistance for precise current sensing7 IEEE Power Electronics Letters7 vol 27 no 37 Sept 2004 J Luo7 N Pongratananukul7 J Abu Qahouq7 and l Batarseh7 Time varying current observer with parameter estimation for multiphase low voltage high current voltage regulator modules7 in Proc IEEE Applied Power Electronics Conference7 2003 R Erickson and D Maksimovic 7 Fundamentals of Power Electronics7 2nd ed Kluwer Academic Publishers7 2000 MAX8524 MAX8525 Datasheet Maxim Online Available httppdfserv maxim iccomendsMAX8524 MAX8525pdf NCP5318 Datasheet ON Semiconductor Online Available httpwww onsemicompubCollateralNCP5318 DPDF 20l 21l 22l 23l 24l 25l 26l ml 152 lSL6316 Datasheet lntersil Online Available httpwwwintersilcomdata fnfn9227pdf FAN5019 Datasheet Fairchild Semiconductor Online Available http wwwfairchildsemicomdsFAFAN5019pdf ADP3168 Datasheet Analog Devices Online Available httpwwwanalog comUploadedFilesDataSheets97146375ADP3168bpdf lSL6592 Datasheet lntersil Online Available httpwwwintersilcomdata fnfn9163pdf C B Umminger7 Circuits and methods for providing multiple phase switching regulators which employ the input capacitor voltage signal for current sensing7 US Patent 6 940 261 131 Sept 6 2005 J G Proakis and D G Manolakis7 Digital Signal Processing Principles Algo rithms and Applications7 3rd ed Prentice Hall7 1996 R Redl and N Sokal7 Near optimum dynamic regulation of dc dc converters us ing feedforward of output current and input voltage with current mode control77 IEEE Trail on Power Electronics7 vol 4 no 17 pp 18171917 July 1986 G K Schoneman and D M Mitchell7 Output impedance considerations for l28l l29l l30l l31l l32l l33l 153 switching regulators with current injected control77 IEEE Tran on Power Elec tronics7 vol 4 no 17 pp 257357 Jan 1989 K J Astrom and B Wittenmark7 Adaptive Control Addison Wesley7 1989 J Zhang and S Sanders7 A digital multi mode 4 phase lC controller for VR applications7 in Proc Applied Power Electronics Conference7 20077 submitted at the time of writing this thesis N O Sokal7 System oscillations from negative input resistance at power in put port of switching mode regulator7 ampli er7 DCDC converter7 or DCAC inverter77 in Proc IEEE Power Electronics Specialists Conference7 19737 pp 1387140 R Middlebrook and S Cuk7 A generalized uni ed approach to modeling switch ing converter power stages7 in Proc IEEE Power Electronics Specialists Con ference7 19767 pp 18734 R Middlebrook7 Design techniques for preventing input lter oscillations in switched mode regulators77 in Proc POWERCON 57 19787 pp A3717A3716 Y Jang and R W Erickson7 Physical origins of input lter oscillations in current programmed converters7 IEEE Tran on Power Electronics7 vol 7 no 4 pp 7257733 Oct 1992 1341 1351 1361 1371 1381 1391 1401 1411 154 T Phelps and W Tate7 Optimizing passive input lter design7 in Proc POW EROON 6 1979 pp G1717G1710 R W Erickson7 Optimal single resistor damping of input lters7 in Proc Applied Power Electronics Conference7 1999 S Kelkar and F Lee7 A novel feedforward compensation canceling input lter regulator interaction77 IEEE Tran on Aerospace and Electronic Systems7 vol 197 no 27 pp 25872687 Mar 1983 7 Stability analysis of a buck regulator employing input lter compensa tion7 IEEE Tran on Aerospace and Electronic Systems7 vol 207 no 17 pp 677777 Jan 1984 7 Adaptive input lter compensation for switching regulators77 IEEE Tran on Aerospace and Electronic Systems7 vol 207 no 17 pp 577667 Jan 1984 J Foutz 1995 lnput lter interaction SMPS Technology Online Available httpwwwsmpstechcom lter00htm L Lewis7 B Cho7 F Lee7 and B Carpenter7 Modeling7 analysis and design of Distributed Power Systems7 in Proc IEEE Power Electronics Specialists Con ference7 19897 pp 1527159 B Choi and B H Cho7 lntermediate line lter design to meet both impedance l42l l43l l44l l45l l46l 155 compatibility and EMl speci cations IEEE Tran on Power Electronics7 vol 107 no 57 pp 583758537 Sept 1995 M FloreZ Lizarraga and A F Witulski7 lnput lter design for multiple module DC power system7 IEEE Tran on Power Electronics7 vol 117 no 37 pp 47274797 May 1996 E Gholdlston7 K Karirni7 F Lee7 J Rajagopalan7 Y li anov7 and B Manners7 Stability of large DC power systems using switching converters7 with applica tions to the International Space Station7 in Proc Energy Conversion Engineer ing Conference7 19967 pp 1667171 S Abe7 T Ninorniya7 M Hirokawa7 and T Zaitsu7 Stability comparison of three control schemes for bus converter in Distributed Power System7 in Proc International Conference on Power Electronics and Drives Systems7 vol 27 20057 pp 124471249 X Feng7 J Liu7 and F C Lee7 lrnpedance speci cations for stable DC Dis tributed Power Systems7 IEEE Tran on Power Electronics7 vol 177 no 27 pp 15771627 Mar 2002 P Li and B Lehrnan7 Accurate loop gain prediction for DC DC converter due to the impact of sourceinput lter7 IEEE Tran on Power Electronics7 vol 207 no 4 pp 75477617 July 2005 l47l l48l l49l l50l l51l l52l l53l l54l 156 M Karppanen7 T Suntio7 and J Kelkka7 Load and supply invariance in a regulated converter7 in Proc IEEE Power Electroriics Specialists C39orifererice7 2006 C Desoer and M Vidlyasagar7 Feedback Systems Input Output Properties Aca demic Press7 1975 F M Callier and C A Desoer7 Liriear System Theory Springer Verlag7 1991 R Midldllebrook7 Null double injection and the Extra Element Theorem77 IEEE Trari ori Education7 vol 327 no 37 pp 16771807 Aug 1989 T Suntio and l Gadloura7 Use of unterminated modeling technique in analysis of input lter interactions in telecom DPS systems7 in Proc IEEE INTELEC397 2002 pp 5607565 A Hentunen7 K Zenger7 and T Suntio7 A systemic approach to analyze the stability of Distributed Power Supply and Systems7 in Proc IEEE NORPIE7 2004 J C Doyle7 B A Francis7 and A R Tannenbaum7 Feedback Coritrol Theory Macmillan Publishing Company7 1992 J Chen7 Logarithmic integrals7 interpolation boundls7 and performance limita l55l l56l l57l 157 tions in rnirno feedback systems7 IEEE Tran on Automatic Control7 vol 457 no 67 pp 1098711157 June 2000 A Packard7 G Balas7 M Safonov7 R Chiang7 P Gahinet7 and A Nernirovski 2006 Robust control toolbox 31 The Mathworks Online Available httpwwwrnathworksCornproductsrobust U Mackenroth7 Robust Control Systems Theory and Case Studies Springer7 2004 M Engelhardt 2006 LTspiceSwitcherCAD lll version 217V Linear Tech nology Corporation Online Available httpwwwlinearCorndesigntools softwareRegistrationjsp 165 Appendix C Robust design Matlab code Z Robust design of buck converter controller with input filter Z nominal parameters Vinnom 12 Z input voltage Vrefnom 12 X reference voltage N 4 X number of phases Lnom 400e 9N Z total inductance Rdcrnom 4e 3N Z inductor DC resistance Cnom 800e 6 Z output cap Resrnom 1e 3 Z cap series resistance lonom 100 Z output current Rref 125e 3 Z droop Z actual values Vin ureal Vin Vinnom Range 10 13 Vref Vrefnom L Lnom Rdcr Rdcrnom C Cnom Resr Resrnom 10 Ionom Z derived values
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