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# DIGITAL CIRCUITS ECE 171

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This 75 page Class Notes was uploaded by Miss Chadrick Doyle on Tuesday September 1, 2015. The Class Notes belongs to ECE 171 at Portland State University taught by Staff in Fall. Since its upload, it has received 81 views. For similar materials see /class/168257/ece-171-portland-state-university in ELECTRICAL AND COMPUTER ENGINEERING at Portland State University.

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ECE171 Digital Circuits r April 6th 2004 Tuesday Boolean Algebra Truth Tables Karnaugh Maps Carno Carnau Haiqiao Xiao ECE Portland State April 6th 2004 Tue University haiqiaoxecepdxedu Purpose of Boolean Algebra Representing binary bits with logic functions Bridge between Number Theory Operations and digital logic circuit Layers from a computer to integrated cirucits Haiqiao Xiao ECE Portland State April 6th 2004 Tue University haiqiaoxecepdxedu Fundamentals Space of Variable Values TRUE T gt 1 FALSE F gt 0 2State Events A Door Closedquot YN no ajar 3State Events B Traffic Light Color RGB Analog Events T Air Temperaturequot 0 K to oo Boolean Expression Constant 1 0 Single Variable X Y Z Complements of X More operationsvariables X YZ Haiqiao Xiao ECE Portland State April 6th 2004 Tue University haiqiaoxecepdxedu 3 Fundamentals continued Literal Single variable or its complements X X Order of Precedence Parenthesis gt Complement gt AND gt OR r AB ABC Operations AND ltigt o Boolean Multiplication 001 0 OR gt Boolean Addition 11 1 NOT gt Complement Negation Haiqiao Xiao ECE Portland State April 6th 2004 Tue University haiqiaoxecepdxedu 4 Examples of Operations Imaginary Gear Shift Lever Interlocking Logic in an AutomaticTransmission Automobile P Parking Brake Set FB Hydraulic Foot Brake Deployedquot D All Doors Are Fully Closed B Breath Analyzer Alcohol Detection Positive S Gear Shift Lever Latch Released True 1 False 0 SPFBD Haiqiao Xiao ECE Portland State April 6th 2004 Tue University haiqiaoxecepdxedu Primary Properties XYYX XYzYX XYZXYXZ XYZXYXZ XX1 XX0 X11 X00 Haiqiao Xiao ECE Portland State April 6th 2004 Tue University haiqiaoxecepdxedu Principle of Duality When AND and OR operators are swapped Examples XY ltgt XY XYZltgtYZ Haiqiao Xiao ECE Portland State April 6th 2004 Tue University haiqiaoxecepdxedu Truth Tables X 7 0 1 1 0 OR operator AND operator Complement operator a b c Figure 222 Operator de nitions a or OR operator b or AND operator C or complement operator Input Output Exhaust Input Possibilities Haiqiao Xiao ECE Portland State April 6th 2004 Tue University haiqiaoxecepdxedu Logic Symbols e Logic Model of physical components Show signal relationship and flow I E 2 input AND 3 input AND 4 input AND Figure 224 Graphic symbols for the AND operation Haiqiao Xiao ECE Portland State April 6th 2004 Tue University haiqiaoxecepdxedu Logic Symbols Continued 2inpul OR 3inpul OR 4inpul OR Figure 223 Graphic symbols for the OR operation Inverter Figure 225 A graphic symbol for the complement operation usually called an Inverter Haiqiao Xiao ECE Portland State April 6th 2004 Tue University haiqiaoxecepdxedu 10 NAND T External Invcrtcr Internal Inverter Equivalent Circuit that 2 inpul NAND performs the NAND operation Figure 227 Equivalent Circuit and graphic symbol for a 2 input NAND operation Haiqiao Xiao ECE Portland State April 6th 2004 Tue University haiqiaoxecepdxedu 11 NOR T External Inverter Internal Inverter Equivalent circuit that Z inpui NOR performs the NOR Operation Figure 226 Equivalent Circuit and graphic symbol for a 2 input NOR operation Haiqiao Xiao ECE Portland State April 6th 2004 Tue University haiqiaoxecepdxedu 12 Exclusive OR XOR X YXYXY X Y XOR I LI LOO I LOI LO OI LI LO April 6th 2004 Tue Haiqiao Xiao ECE Portland State University haiqiaoxecepdxedu 13 r Exclusive OR XOR 13 XOR Equivalent circuit that performs the XOR operation Figure 228 Equivalent Circuit and graphic symbol for the XOR operation Haiqiao Xiao ECE Portland State April 6th 2004 Tue University haiqiaoxecepdxedu 14 r Literal Count Reduction To make things simpler Example of OP 3 gt 2 FXYXZXYZ X Y 2input OR X F 2 input AND 2 input OR 2inpul AND 2inpu1 OR a b Figure 231 1 Given function b reduced function Haiqiao Xiao ECE Portland State University haiqiaoxecepdxedu 15 April 6th 2004 Tue Q All Boolean Expressions in the end results of the Exams and Homeworks should be maximallysimplified unless further simplifications are Equivalent or very Obscure Q v Jargons SOP Sum of Products POS Product of Sums Combinational Logic If Exist Salmon and Lemon Pepper then Broil Sequential Logic If Yesterday Snowed and Today Rained then Road Closure RC0 54130 If Yesterday Road Closure and Today Snowed the Road Closure toda Y RC0 RC1 so Haiqiao Xiao ECE Portland State April 6th 2004 Tue University haiqiaoxecepdxedu 17 7 Theorem Theorem name lef X Double omplcmcnmlion or Double Ncgulion Theorem T2a X X X ldempoluncy Theorem TZb XX X T3azX1 1 Idcnlily Element Theorem T313 XvO 0 T43 X X y X T4b XvX Y z X T53XYZXYZ T5hXYZXYZ T6aIXAY X37 X T6h X YX 7 X T7a X Y Ez YZ X Y X Z T7b X YX no Z X hX 2 T8a2XXYxX Y T8bXYXY T1021 X1 X X X Eff TlOb XlXZTX37 7Xquot X X A73 QM Absorption 39Ihcurum Associulivc Theorem Adjuccncy Theorem Consensux Theorem Simplificaliun Hworem DcMUrgan s Theorem muvurial lc form De Morgan s Theorem generalind l nrm 18 Figure 232 Boolean algebra theorems Proving the Boolean Theorems T Via Boolean Algebra Using Truth Tables A Mixture of Both Example Consensus Theorem XYXZYZXYXZ Haiqiao Xiao ECE Portland State April 6th 2004 Tue University haiqiaoxecepdxedu 19 From Truth Table to Boolean Expression A B C F FZBCAF AB O 0 0 0 ZBCA 0 0 1 0 0 1 0 0 F2135 EEC 1 1 1 B A CABC 1 0 0 1 1 0 1 0 ABABCAC 1 1 0 1 Sum of Standard Product 1 1 1 0 Terms Minterms mi Haiqiao Xiao ECE Portland State April 6th 2004 Tue University haiqiaoxecepdxedu 20 Product of Standard Sum Terms Maxterms A B FAB o o o F00 o 1 1 F01 1 o 1 F10 1 1 o F11 FA B F00 A B F01 A 1 o F10 2 B F11 2 F mA B Haiqiao Xiao ECE Portland State April 6th 2004 Tue University haiqiaoxecepdxedu 21 Function Minimization Expand to SOP POSes do not work well Shrink em by ABAB A Consensus Theorem XyXZYZXYZ r Haiqiao Xiao ECE Portland State April 6th 2004 Tue University haiqiaoxecepdxedu 22 Karnaugh Map or KMap Only one variable changes for adjacent cells Reflective Gray Code RGC Boolean Function ltigt Truth Table ltgt K Map Values Filled in 1 0 or x don t care wx YZ X YZ XY FWXYZ RXw K2 2 ill I ll 10 Fwy m m 11 m U I 4 7 b C a Figure 251 K maps drawn in number form a 2 Variable K map b 3 variable K map and c 4 variable K map Haiqiao Xiao ECE Portland State 23 April 6th 2004 Tue University haiqiaoxecepdxedu K Maps in Variable Form r w X Y z X YZ X Y i Y W X39 Y Z X X X Y z W FX y X X iA I i w N N N i a b Figure 252 Kmaps drawn in variable form a 2 variable Kmap b 3variable Kmap and c 4variable Kmap Haiqiao Xiao ECE Portland State April 6th 2004 Tue University haiqiaoxecepdxedu 24 KMap Organization AB C CD AB FAB C D I ll a b C Figure 253 Different Kmap organizations a 2 variable Kmaps b 3variable Kmaps and c 4 va1iabie Kmap Haiqiao Xiao ECE Portland State April 6th 2004 Tue University haiqiaoxecepdxedu 25 XK Map Example X YZ F1XYZ 00 01 11 10 0 0 0 O 1 10111 Example 253 How to derive its Boolean Expression Haiqiao Xiao ECE Portland State April 6th 2004 Tue University haiqiaoxecepdxedu 26 Homework 3 Q Write the Truth Table for the Gear Shift Lever Interlocking example in today s class 210 223 225 a d 234 237 242 247 A Wise Wife installed a M S Homestyles Bathroom Controller with the necessary sensors the door will only unlock UL after the hands have been washed HW or Hand Sanitizer has been applied HS and the toilet seat must be in the down position SD The door will also unlock if the red emergency button RE is depressed Haiqiao Xiao ECE Portland State University haiqiaoxecepdxedu 27 April 6th 2004 Tue r Homework Continued Write the Truth Table of UL as a function of HW HS SD and RE Write the Boolean function in minterm format then simplify it Plot the Karnaugh map and fill in all data Haiqiao Xiao ECE Portland State University haiqiaoxecepdxedu 28 April 6th 2004 Tue r ECE171 Digital Circuits April 26th 2004 Monday Programmable Logic Devices Haiqiao Xiao ECE Portland State April 26th 2004 Mon University haiqiaoxecepdxedu Consensus Theorem revisited ABZCBCABZC ABBC CAFE Q How to remember it Q How to apply it in real situations Silt the variables one by one It should NOT be necessary to apply any simplification to the math after a correct Karnaugh map has been done r Haiqiao Xiao ECE Portland State April 26th 2004 Mon University haiqiaoxecepdxedu 2 r Shannon s Expansion Theorem 7 FABF00A B FO1A BF10AB F11 AB An arbitrary function can always be expressed in terms of its minterms Minterms can be written when you treat the input variables as an array of binary bits 000 001 010 111 To be useful all minterms are needed A decoder gives us a complete collection of minterms Haiqiao Xiao ECE Portland State April 26th 2004 Mon University haiqiaoxecepdxedu 3 A Decoder is a Minterm Generator f Bl BO T7 39739 l T 130 Decoder 0 F0 1 U F2BLBO BO o i 0 F1 B F B 1 2 0 F2 D 823130 3 D F 3 a b Figure 353 Decoder a gate level circuit diagram b logic symbol Haiqiao Xiao ECE Portland State April 26th 2004 Mon University haiqiaoxecepdxedu and Can be Used to Generate Arbitrary Functions DMUX 9C EN 0 0 quot GND Y o 0 F B 213 o X hm Q How to generate multiple output functions using the same decoder o How many different functions can be generated Haiqiao Xiao ECE Portland State April 26th 2004 Mon University haiqiaoxecepdxedu Concept of Programmable Logic Devices PLDs AND array connections OR array connections Device Outputs Device Inputs tllllz iiiW WP Inverter AND OR Buffer Army Array Array Figure 361 Template or generalized ANDOR gate form architecture for PLDs Q Standardized way of generating arbitrary multiple output functions 5 Programmable the user can change its functions Haiqiao Xiao ECE Portland State April 26th 2004 Mon University haiqiaoxecepdxedu r Acronyms of Different PLDs PROM PLA PAL amp GAL Refer to Page 169 in the book FPGAs Page 650 Volatile programming lost when the device is powered down Nonvolatile programming intact when the device is powered down Haiqiao Xiao ECE Portland State University haiqiaoxecepdxedu 7 April 26th 2004 Mon Symbof enventionampinnRLDmPregramming No Intact Intact Blown Blown fuse fuse f fuse fuse fuse Fixed connection Programmable Simplified Connection broken Simplified at factory connection representation after programming representation Multiple input Pull up resistors Multiple input Pull down resistors AND gate not shown OR gate not shown Inpuitemi Product terms A A B B Pri zPsPtu AABB0 l D pp2p3p4m All fuses intact An X placed inside All fuses intact An Xplaced inside an AND gate also an OR gate also represents all fuses intact represents all fuses intact Inpuitem Product terms AA BB plp2p3p4 1 Due to pullup Due to pulldown resistors resistors All fuses blown All fuses blown Figure 362 Programmable symbology summary for the different types of PLDs le II LULI I LUU39I I39IUI I UI IIVCI DILy IIanIaUKKEJCampCPUKCUU PROM is like when you are using a decoder Inputs Zto4 Decoder circuit inputs two in this case two in this case B A B A K a K 0R armyconnections i i i i R army connections V4 Vt prngrznnnmhc Vt Vt pmgrmnnwhlc quot D m0 ll m0 quot 1 ll III 0 j quot72 fl 1713 039 4 u u 4 quot3 1713 4 g 39 L 39z 39 AND zirrzi L AnnnDccllrilnli connections xud itich F1 Fl 393 F4 Fl 2 F3 F4 Outputs Outputs four in this case four in this case H b Figure 363 PROM circuit a circuit representation using gates b simpli ed circuit representation using gates Haiqiao Xiao ECE Portland State April 26th 2004 Mon University haiqiaoxecepdxedu 9 The Catch of PROM and the Rise of PLAs e 2 inputs dictate 4 AND gates e M inputs need 2M AND gates Just a few are actually used Make the Chip unnecessarily large 4 PLAs Also programmable at the AND array More inputs less chip area gt cost Slower two programmable array More expensive to program two patches to work on Haiqiao Xiao ECE Portland State April 26th 2004 Mon University haiqiaoxecepdxedu 10 quotquotquotquotquotquotquotquotquotquot quotquotPlesNlowmthemProgrammmgmofquotBothmANDMandMGRquotmmmmmm Arrays IPPUFS Inputs three 1 11115 5358 three in this case A B C Try A B C OR army 39onn minus k t n a r rngrzmnltlhlr vquot vquot 53322121 P l p1 P3 lm P2 3 I p J P4 1m 4 p5 II quot P5 AN D nrruy L unnecliuns AND army Connections pr0grznnmnhc pmgrnmmzibc F1 F2 F3 F1 F2 F3 Outputs Outputs three in this case three in this case a b Figure 364 PLA circuit a circuit representation using gates b simpli ed circuit A representation using gates PALs or GALs Inputs Inputs three in this case three in this case A B C A B C OR army connections R army connections iiixed 39i39ed Outputs Outputs two in this case p two in this case F2 114 AND array AND array connections connections iprogrnmmziblc progmmmahle a b Figure 365 PAL circuit a circuit representation using gates b simpli ed circuit representation using gates Haiqiao Xiao ECE Portland State April 26th 2004 Mon University haiqiaoxecepdxedu 12 Function Reuse in PALs Inverter with a 3state output K K 2 R Z P 10 Note If OEi 1 then Fi is an output if OH 0 then Pi is an input fori 12 quot P2 lO l39m l39uncliun sharing or i39nr additional inputs Connections hack into AF I I 474 lhc AND urruy lllill allow Figure 366 A PAL circuit which provides either function sharing or additional inputs Haiqiao Xiao ECE Portland State April 26th 2004 Mon University haiqiaoxecepdxedu 13 Example P 174 PROM Fixed A B Programmed 1 connections connections A B F1 F2 F3 F4 3 55 0 0 1 0 1 0 AB 00 39 mo 0 1 1 1 1 1 AB 01 m 1 0 0 1 1 1 AB 10 mg 1 1 0 1 O 0 AB 11 quot13 Add r Data HEX HEX 0 A Figure 367 PROM impleiiiegrtlzgiSgagingggerter an OR gate a NAND gate 1 F 2 7 MASK MAP or Fuse Map 3 4 Haiqiao Xiao ECE Portland State April 26th 2004 Mon University haiqiaoxecepdxedu 14 Fl t Example P E 176 MultIFunc Minimization A B 11 p A B pl 4 00 01 1 11quot 10 It on 011 11 101quot 22p2p3 1 32plp4 11394p2p4 ZBA EqE Z HAE AB 23 2A B A Figure 369 Multiple function minimization for PLA implementation Q Need Inv OR NAND XOR 6 Only 4 AND gates are available maximum 4 minterms Q You want to maximally share them by looking at the Karnaugh map Typically done by computer programs April 26th 2004 Mon Haiqiao Xiao ECE Portland State University haiqiaoxecepdxedu 15 Example P 176 write down the function of the PLA A B Programmed connections 4 2 AI Programmed connections Figure 368 PLA implementation for an Inverter an OR gate a NAND gate and an XOR gate Haiqiao Xiao ECE Portland State April 26th 2004 Mon University haiqiaoxecepdxedu 16 i U U U Homework 7 Exercises 346 347 350 on Page 211 Read Page 173 PAL or GAL classification nomenclature No submission necessary for Homework 7 Haiqiao Xiao ECE Portland State April 26th 2004 Mon University haiqiaoxecepdxedu 17 ECE171 Digital Circuits 7 June lst 2004 Tuesday Recitation for Final Exam June lst 2004 Tue Cardinal Rules sirOpenbook you can use your homeworks notes books No books notes calculator swapping Including contents before the midterm with concentration on the course contents in the 2nd half of the term June lst 2004 Tue Study Guideline will also be available at wwwecepdxeduece425 June lst 2004 Tue Totem Pole and TriStateTM VCC Q How to operate it normally PNP Q1 How to make It HIZ Front End Output about of IC CIrCUIt Circuit Q2 More details in May 10 NPN lecture June lst 2004 Tue TriStateTM Gate Symbol 7 74L8125A 0EL0 0EH1 H1 OE is active OE is inactive OE TE is inactive B i F B F B F or B F Qualifying symbol F B to indicate a 3stute output F Z F Z normal Zstnte lriastatlcd output operation a b C lri stzttcd output 61 Figure 423 74LS 125A a Bus Buffer with 3 state output b normal 2 state operation 0 output in disconnect state and d open switch representation of a tristated output How to implement a 2input data selector with it June lst 2004 Tue WiredAND w OpenCollector 8 tran 0 Wu 0 gt V4 NPN PULSE5 o o 10p 10p 4u 8u June lst 2004 Tue NPN PULSE5 o o 10p 10p 2u 4u o o gt R1 5K NPN PULSE5 o o 10p 10p 1u 2u Decoder Operation Dem0138 Circuit Active high active low Gate enableselect What makes all output high June lst 2004 Tue FullAdder HW104 How to solve the given problem What happens if the input data are A and B How to interpret it n Use magnitude only n Use 2 s Complement June lst 2004 Tue R S Latch DLatch DFlipflop 3 Extra lecture material it Basic principle in constructing Dlatch and Dflipflop it Basic properties of them How to do it with OR or NOR gates at Completing timing plots June lst 2004 Tue Switching Network Example 6 gt L 395 Q X F 2 EF N Y E gt 4 June lst 2004 Tue 10 Address Decoding with 3to8 Decoder A0 to Awhat aMSBs are used for decoding n Why not LSBs June lst 2004 Tue 11 Constructing Larger MuxDemuxes iv Multiplexer or Demultiplexer a How large a What is the size of available MuxesDemuxes June lst 2004 Tue 12 ECE171 Digital Circuits May 18th 2004 Tuesday Call for Homework J S amp M S Late on 6 J V misses 5 6 J R misses 1 D C S D M Di M Du D Gr D H E W are assumed to have dropped the class H T changed to Audit Latches FlipFlops May 18th 2004 Tue Latches i A latch is a mechanism that can keep its state n But the state can change with input control n The light switches can keep their states n The projection screen switch cannot keep its state Latches are used in digital circuits primarily for n Building memory devices w Small memory only w Usually not a replacement for RAMROM n Synchronizing signals n Latching data for outputinterfacing t Latches are built using feedbacks n Feedback is the act of routing outputs to input ports May 18th 2004 Tue Memory Example POS quot1pm Data 16BitFullAdder 16 Output 16 16 16Bit Memory to Store Previous Results Point of Sale POS Cashier Machine n For calculating sum of prices 11 A memory is needed to remember previous n1 state no further memory is needed no need to remember more than 1 state n This memory can be implemented by latches You cannot use latches to store British Encyclopedia 11 Capacity too limited or too expensive with the right capacity May 18th 2004 Tue Synchronizing Data Signals CLK Sampling Moment I I I a I o l 39 I l Data change become Data do not change CLK Data change become valid at the same become valid at the valid at the same moment same moment moment May 18th 2004 Tue A For Building Output Ports The Data Bus from CPU is used for many purposes it cannot hold a state To output a state and keep it there you must use a latch The latch relay the data only when all conditions are met n The chip is enabled via address decoding n The WRite signal is active the CPU is in the mood for writing Example 74LS373 May 18th 2004 Tue D0 l Output Control Signals D1 i D2 for LED indicators D3 Chip Enable Ah D WRite Simple OR Gate Latch o BEIGE HXXX 3 Ul 39 39 Circuit DemolORLatch The Latch is a Latch because of Feedback it can remember its own state a You can set the state but you cannot rese quotits state i Set means changing to Logic 1 i Reset means changing to Logic 0 The state of the Latch is externally observable 11 Not always true in digital circuits May 18th 2004 Tue Simple NORGate Latch E Linear Technology LTSpicefSwitcherCAD DemoNORLath asc Eile Edit Hierarchy Mew gimulate Iools window elp J l l1 la a l la lat EM LE P lt 332 DemoNGRLaiuh139asc xii his Bus gus May 18th 2004 Tue Simple NORGate Latch sitCircuit DemoNorLatchl The Second OR Gate is connected as an Inverter af The Capacitor sets the initial condition for Node Q during simulation May 18th 2004 Tue Adding Reset Capability to NOR Gate Latch m Linear Technology LTspicefSwitcherCAD DemoNORLatehZasc Eile Eiew ElotSettings gimulation Iools window elp J lelcel wlaotetmgtelaeelaeml lbeei e 3 3 DemoNORLateh2asc lps 2m 3113 rips Ens Bus his Bus Clickto manually enter Horizontal Axis Limits x7 May 18th 2004 Tue Plot the NORGate Latch in the Traditional Way A1 The is called RS or SR Latch because of its Set and Reset inputs The present state is fed back to its input so you do not have to do A2 anything to keep its state Q R and S are both normally 0 but Q can 0 be either 0 or 1 What if both R and S are 1 S Q n Q 0 Qbar 0 gt reset dominant n The circuit is not stable 8 Qbar May 18th 2004 Tue 10 The Delay Model of R S Latch used to illustrate a different problem Set Input 9 Feedback present d state output Q is fed back to input At R delay Reset Input Next State Present State Output Output a WhenR1andS 1wehaveQQbar0 5 What will be the next state if we release R and S from 1 to 0 at the exact same moment n The signal paths for Q and Qbar are not created equal n The fast path changes to 1 May 18th 2004 Tue 11 KIN m Linear Technology LTspiCBISwitcherCAD Ill r DemnRSButh1asc Elle Edit Hierarchy Miew imulate Iouls window elp 39 Qtrain imu m s I I ZLIS i tips Ems Bus 1ng Releasing both R and S from 1 to 0 jelelwxweqqmgmgem asemeluymz 3 zneeoemam DemoRSButh1asc May 18th 2004 Tue 4 12 State Diagram Description of R S Latch May 18th 2004 Tue Reset S R 0 1 I 1 SRSR R Holdl SR 00 10 0139 31 ER SR jg 5 Set S R Si 2 E S R l 0 a b Figure 5112 State diagram for the SR Latch Circuit a detailed Classical form b simpli ed form with Boolean expressions 13 DLatch and DFlipflops is D stands for Data is DLatch is level sensitive to clock DFlipflop is edge sensitive to clock DFlipflop is also known as DRegister 2 DFlipflop can be constructed from DLatch May 18th 2004 Tue 14 rlw Constructing a DLatch m Linear Technology LTspiceJ SwitcherCAD l DemuDLatchasc Elle Edit Hjevamhy yiew imulate Iouls Jmmmxmaqq d i la fl tEMHB LVEvIE 3 inwweofm mnp window elp mdDL tchase Alps mus May 18th 2004 Tue From a Data Selector r CLK 0 the input of the data selector is the output Q so the latch keeps its current state CLK 1 the input of the data selector is the Data Input so the latch is a transparent gate n Also called transparent latch May 18th 2004 Tue 16 Constructing a DFlipflop from DLatches Use two DLatches One as Master one as Slave May 18th 2004 Tue 17 Homework Review class material Work on project May 18th 2004 Tue 18

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