COMPUTER SYSTEMS PROG
COMPUTER SYSTEMS PROG CS 201
Popular in Course
Popular in ComputerScienence
This 64 page Class Notes was uploaded by Orrin Rutherford on Wednesday September 2, 2015. The Class Notes belongs to CS 201 at Portland State University taught by Staff in Fall. Since its upload, it has received 14 views. For similar materials see /class/168300/cs-201-portland-state-university in ComputerScienence at Portland State University.
Reviews for COMPUTER SYSTEMS PROG
Report this Material
What is Karma?
Karma is the currency of StudySoup.
You can buy or earn more Karma at anytime and redeem it for class notes, study guides, flashcards, and more!
Date Created: 09/02/15
sAIL Memory Management From Absolute Addresses to Demand Paging Joel Emer Computer Science and Artificial Intelligence Laboratory MIT Based on the material prepared by Arvind and Krste Asanovic Memory Management 6823 L92 Emer o The Fifties Absolute Addresses Dynamic address translation 0 The Sixties Paged memory systems and TLBs Atlas Demand paging 0 Modern Virtual Memory Systems October 12 2005 6823 L93 Emer Names for Memory Locations virtual address machine language address address 0 Machine language address as specified in machine code 0 Virtual address ISA specifies translation of machine code address into virtual address of program variable sometime called effective address 0 Physical address gt operating system specifies mapping of virtual address into name for a physical memory location October 12 2005 cull 6823 L94 Emer Absolute Addresses EDSAC early 50 s l virtual address physical memory address l 0 Only one program ran at a time with unrestricted access to entire machine RAM IO devices 0 Addresses in a program depended upon where the program was to be loaded in memory 0 But it was more convenient for programmers to write location independent subroutines How could location independence be achieved October 12 2005 in Dynamic Address Translation 6823 L95 Emer Motivation In the early machines IO operations were slow and each word transferred involved the CPU Higher throughput if CPU and IO of 2 or more programs were overlapped How gt multiprogramming Location independent programs Programming and storage management ease gt need for a base register Protection Independent programs should not affect each other inadvertently gt need for a bound register October 12 2005 Physical Memory 6823 L96 Emer Simple Base and Bound Translation I I Segment Length Bounds Violation a 0 Physical GE Load X Effective Address 2 Address 2 Base Physical Address Program Address Space Base and bounds registers are visibleaccessible only when processor is running in the supervisor mode October 12 2005 cull 6823 L97 Emer Separate Areas for Program and Data Bounds Violation Eff 39 A Load X ectlyeteddr gt L O E D 2 Program A E Bounds g Address Violation Space What is an advantage of this separation Scheme still used today on Cray vector supercomputers October 12 2005 SAIL 6823 L98 Emer Memory Fragmentation Users 4 amp 5 Users 2 amp 5 arrive 05 leave user 1 5ii i user 2 7 As users come and go the storage is fragmented Therefore at some stage programs have to be moved around to compact the storage October 12 2005 EAIL Paged Memory Systems 6823 L99 Emer 0 Processor generated address can be interpreted as a pair ltpage number offsetgt niuiimiber oi at o A page table contains the p ysical address of the base of each page wNI O O 1 2 3 3 Address Space Page Table of User1 of User 1 2 Page tabes make it possible to store the pages of a program noncontiguously October 12 2005 Affier i iglw SAIL 6823 L910 Emer Private Address Space per User User 1 Page Table Physical Memory User 2 User 3 Page Table 0 Each user has a page table 0 Page table contains an entry for each user page October 12 2005 cull 6823 L911 Emer Where Should Page Tables Reside 0 Space required by the page tables PT is proportional to the address space number of users gt Space requirement is large gt Too expensive to keep in registers o Idea Keep PT of the current user in special registers may not be feasible for large page tables Increases the cost of context swap 0 Idea Keep PTs in the main memory needs one reference to retrieve the page base address and another to access the data word gt doubles the number of memory references October 12 2005 gigolo 6823 L912 Emer Page Tables in Physical Memory 3 PT User 1 er2 I X October 12 2005 EL SAIL 6823 L913 Emer A Problem in Early Sixties c There were many applications whose data could not fit in the main memory eg payroll Paged memory system reduced fragmentation but still required the whole program to be resident in the main memory 0 Programmers moved the data back and forth from the secondary store by overlaying it repeatedly on the primary store tricky programming lffi October 12 2005 am SAIL 6823 L914 Emer Manual Overlays Assume an instruction can address all the storage on the drum 0 Method 1 programmer keeps track of addresses in the main memory and initiates an IO transfer when required l dim 0 Method 2 automatic initiation of IO Central Store transfers by software address translation Ferrantl Mercury 1956 Brooker s interpretive coding 1960 Problems Methodl Difficult error prone Method2 Inefficient Eff rt rquot l October 12 2005 it E Q u SAIL 6823 L915 Emer Demand Paging in Atlas 1962 A page from secondary storage is brought into the primary storage whenever it is implicitly demanded by the processorquot Tom Kilburn Primary 32 Pages 512 wordspage Primary memory as a cache for secondary memory Secondary central Drum User sees 32 x 6 x 512 words Memory 32x6 pages of storage October 12 2005 SAIL 6823 L916 Emer Hardware Organization of Atlas Effective system code Address Initial J not swapped Address Decode system data PARS not swapped 48bit words 512word pages 8 Tape decks 88 secword 1 Page Address Register PAR per page frame 31 lteffective PN statusgt Compare the effective page address against all 32 PARs match gt normal access no match gt page fault save the state of the partially executed instruction October 12 2005 SAIL 6823 L917 Emer Atlas Demand Paging Scheme o On a page fault Input transfer into a free page is initiated The Page Address Register PAR is updated If no free page is left a page is selected to be replaced based on usage The replaced page is written on the drum 0 to minimize drum latency effect the first empty page on the drum was selected The page table is updated to point to the new location of the page on the drum October 12 2005 554 6823 L918 Emer Caching vs Demand Paging secondary CPU Caching Demand paging cache entry page frame cache block 32 bytes page 4K bytes cache miss 1 to 20 page miss lt0001 o cache hit 1 cycle page hit 100 cycles cache miss 100 cycles page miss5M cycles a miss is handled a miss is handled in hardware mostly in software October 12 2005 SAIL Fiveminute break to stretch your legs 6823 L920 Emer Modern Virtual Memory Systems Illusion of a large private uniform store Protection amp Privacy several users each with their private address space and one or more shared address spaces useri page table a name space S Demand Paging Provides the ability to run programs Primary larger than the primary memory Memory Sto re Hides differences in machine configurations The price is address translation on each memory reference VA mapping PA 39 39m EEK October 12 2005 cu 6823 L921 Emer Linear Page Table o Page Table Entry PTE Page Table contains A bit to indicate if a page exists PPN physical page number for a memory resident page DPN disk page number for a page on the disk Status bits for protection and usage 0 OS sets the Page Table Base Register whenever active user process changes 1 PT Base Register VPN Offset Virtual address l Tn gal CSAIL j October 12 2005 6823 L922 Emer Size of Linear Page Table With 32 bit addresses 4 KB pages amp 4 byte PTEs gt 220 PTEs ie 4 MB page table per user gt 4 GB of swap needed to back up full virtual address space Larger pages 0 Internal fragmentation Not all memory in a page is used 0 Larger page fault penalty more time to read from disk What about 64 bit virtual address space 0 Even 1MB pages would require 244 8 byte PTEs 35 TB What is the saving grace rljlji1 October 12 2005 least 6823 L923 Hierarchical Page Table Virtual Address 31 2221 1211 p1 p2 10bit 13bit L1 index L2 index Root of the Current Page Table 0 offsetl A W Level1 Page Table Processor Register Level2 page in primary memory Page Tables page In secondary memory V l I PTE of a noneXIstent page Data pages October 12 2005 Emer 111 a SAIL 6823 L924 Emer Address Translation amp Protection Virtual Address willli liltlligill KernelUser Mode ReadWrite Exception Physical Address offset Every instruction and data access needs address translation and protection checks A good VM design needs to be fast one cycle and space efficient W October 12 2005 ELEM 6823 L925 Emer Translation Lookaside Buffers Address translation is very expensive In a two level page table each reference becomes several memory accesses Solution Cache translations in TLB TLB hit gt Single Cycle Translation TLB miss gt Page Table Walk to refill virtual address October 12 2005 cuu 6823 L926 Emer TLB Designs 0 Typically 32128 entries usually fully associative Each entry maps a large page hence less spatial locality across pages more likely that two entries conflict Sometimes larger TLBs 256512 entries are 48 way set associative 0 Random or FIFO replacement policy 0 No process information in TLB o TLB Reach Size of largest virtual address space that can be simultaneously mapped by TLB Example 64 TLB entries 4KB pages one page per entry TLB Reach October 12 2005 run 6823 L927 Emer Variable Sized Page Support VHtualAddress 31 2221 1211 0 p1 p2 offsetl 10bit 13bit L1 index L2 index Root of the Current Page Table Processor Leve1 Register Page Table Level2 ii page in primary memory large page in primary memory Page Tables page in secondary memory m PTE of a nonexistent page Data Pages i October 12 2005 cu 6823 L928 Emer Variable Size Page TLB Some systems support multiple page sizes virtual address physical address October 12 2005 6823 L929 Emer Handling A TLB Miss Software MIPS Alpha TLB miss causes an exception and the operating system walks the page tables and reloads TLB A privileged untranslated addressing mode used for walk Hardware SPARC v8 X86 PowerPC A memory management unit MMU walks the page tables and reloads the TLB If a missing data or PT page is encountered during the TLB reloading MMU gives up and signals a Page Fault exception for the original instruction October 12 2005 ng 6823 L930 Emer Hierarchical Page Table Walk SPARC v8 Virtual Address Offset 3 0 Context Table Register Context Ta L1 Table Context Register L2 Table L3 Table Offset Physical Address MMU does this table walk in hardware on a TLB miss m in October 12 2005 5414 6823 L931 Emer Translation for Page Tables 0 Can references to page tables TLB miss 0 Can this go on forever User PTE Base User Page Table in virtual space T System Page Table in physical space System PTE Base Data Pages a m rlcl n October 12 2005 6823 L932 Address Translation putting it all together Virtual Address hardware hardware or software software the pageis g memory permitted Physical Address to cache Where SEGFAULT October 12 2005 cull ESAIL Thank you CS 201 Cache Microarchitecture Gerson Robboy Portland State University Topics I Generic cache memory organization Direct mapped caches Set associative caches What about writing to memory Multiple processors sharing memory locality design goals spatial locality if you fetch data nstruction X Xi is likely to be fetched next true for code in functions true for data in arrays we want to load more than X we want other items nearby register will only take X call this block the cache line temporal locality if you fetch instruction X now you may do it again soon true if code is in a loop 2 15213 F 02 Cache Memories Cache memories are small fast SRAMbased memories managed automatically in hardware I Hold frequently accessed blocks of main memory CPU looks first for data in L1 then in L2 then in main memory Typical bus structure CPU chip register file cache bus 1 bus interface ALU system bus memory bus IO 3 bndge ltigt main memory 15213 F O2 On a cache miss Data is gotten from memory stored in both L1 and L2 The next access will be an L1 hit If evicted from L1 an L2 hit is still likely This is true for both reads and writes 15213 F O2 On a store in case of cache miss 0 Preread the cache line from memory into both L1 and L2 caches 0 Store the data value into L1 0 The data is written through to L2 Written back to memory later Subsequent stores may write more data into the same line in cache 15213 F O2 The problem with cache design Given an instruction movl ltaddressgt ltreggt Search the L1 cache find the address and move the data from L1 to register I All in one clock cycle In case of an L1 miss and L2 hit I Search L1 cache find it s not there I Search the L2 cache find the address and move the data from L2 to register I Also replicate the cache line in L1 I In at most 10 clock cycles You need more than just fast SRAM to do that 15213 F O2 General Organization of a Cache Cache is an array of sets Each set contains one or more lines Each line holds a block of data S 25 setslt 1 valid bit ttag bits perline Per39ine per cache block H r f A N m II E B 2quot bytes E lines set 0 l per set m Illl l set1 set S1 Cache size C B X EX S data bytes 15213 F O2 Addressing Caches Address A t bits s bits b bits I m1 0 J J 1 set 0 Y Y lttaggt ltset Indexgt ltblock offsetgt set1 The word at address A is in the cache if the tag bits in one of the ltvaidgt lines in set ltset indexgt match lttaggt set 81 The word contents begin at offset ltbock offsetgt bytes from the beginning of the block 8 15213 F O2 therefore 1 we have tag set offset break memory 32 bits up into 3 parts set should give us the set 2 the offset gives us a specific word register in a block set of words 3 tag must match all parts must match actually In some cases we may have multiple lines in a set 9 15213 F 02 Exercise For each cache in the table mnumber of address bits Ccache size in bytes Bbock size and Einesset Determine the number of cache sets S tag bits t set index bits s and block offset bits b m C B E b 32 1024 4 1 32 1024 8 4 32 1024 32 32 10 15213 F O2 DirectMapped Cache Simplest kind of cache Characterized by exactly one line per set set 0 m m cache block E1 lines per set set 1 m m cache block 11 15213 F O2 parking lot analogy thanks to umd assume 1000 parking lot spaces each space numbered from 000999 your parking spot based on 1st 3 digits of SSN there can only be one space simple to find however there may be many collisions not very efficient drawbacks poorhashfunc on don t use slots very well don t use a free slot 12 15213 F 02 Accessing DirectMapped Caches Set selection I Use the set index bits to determine the set of interest tbitS sbits bbits I00 001 I sets1 mm m cache block quot 1 tag set index block offset0 selected set set 1 13 15213 F 02 Accessing DirectMapped Caches Line matching and word selection I Line matching Find a valid line in the selected set with a matching tag actually look up set tag makes sure it is right I Word selection Then extract the word 1 1 The valid bit must be set x selectedsetm ll m IIImmmm 2 The tag bits in the cache 3 If 1 and 2then line must match the 02cm tag bIts In the address I and bIOCK offset t bits 3 bits b bits selects 0110 i I 100 I starting byte quot 1 tag set index block offset0 14 15213 F 02 DirectMapped Cache Simulation m4 bitsaddress M16 byte address space B2 bytesblock S4 sets E1 entryset t1 s2 b1 I X I XX I I Address trace reads 0ooooz1ooo12 1311o12 M10002 M00002 0 00002 miss 13 11012 miss v tag data v tag data 8 10002 miss tag data 0 00002 miss v tag data 511 M 121 15 15213 F O2 Why Use Middle Bits as Index 4line Cache HighOrder MiddleOrder Bit lndexi Bit lndexi 00 oo oo 01 01 oo 10 10 oo 11 1 1 O O O O O H O 1 O 1 HighOrder Bit Indexing I Adjacent memory lines would map to same cache entry I Poor use of spatial locality MiddleOrder Bit Indexing I Consecutive memory lines map to different cache lines I Can hold Cbyte region of address space in cache at one time 1 O O 1 OOl l OOH l Ol Ol OH l l l l l l O l l OOOOH 1 O ll ll ll ll ll ll ll ll IO 390 IO 390 IO 390 IO 390 l l l l OOOOI l l l OOOO H H H H lquot lquot lo Iquot lquot lo Iquot lquot lo Iquot lquot I OI OI OI OI OI Ol OI O H H 16 Exercise m4 bitsaddress M16 byte address space B2 bytesblock S4 sets E1 entryset x XX I I Address trace readS 4o1002100012 1311o12 M10002 M00002 5o1o1 Draw a chart showing the cache misses and hits What is the problem with one entry per set 17 15213 F O2 Set Associative Caches Characterized by more than one line per set I This example is a twoway set associative cache 7 cache block 7 E2 lines per set 1 cache block cache block L cache block cache block L cache block 18 15213 F O2 parking lot analogy for Nway set 1000 parking spaces 2digit assigned number 0099 10 slots numbered 00 01 02 99 thus 10 possible places to park in reality you might be assigned lot A with 100 places to park but you can t park in lot B point odds are higher that you can find an acceptable slot nearby 19 15213 F 02 Accessing Set Associative Caches Set selection I identical to directmapped cache mm set 0 m m M m m m Selected set 9 cache block m m m t bits s bits b bits set S1 1 oooo1 quot11 tag set index block offset0 20 15213 F 02 Accessing Set Associative Caches Line matching and word selection I must compare the tag in each valid line in the selected set 1 1 The valid bit must be set 0 1 2 3 4 5 6 7 Ill El IIIII selected set I il Ili39 39 3 If 1 and 2 then cache hit and block offset selects starting byte 2 The tag bits in one of the cache lines must match the tag bits in the address t bits s bits b bits 0110 i 100 l quot11 tag set index block offset0 21 15213 F O2 Exercise m4 bitsaddress M16 byte address space B2 bytesblock S2 sets E2 entriesset i2 s1 b1 XX I X I I Address trace reads 4 0100212 00102 13 11012 3 00112 5 0101 00000 Draw a chart showing the cache misses and hits 22 15213 F 02 Associative Caches A cache with N lines per set is called an Nway set associative cache For example a typical microprocessor might have a 4 way set associative cache 23 15213 F 02 Exercise A processor has 32 bit addresses The L2 cache is 256 Kbytes in size 8way set associative with a block size of 64 bytes How many block offset bits are there how many set index bits and how many tag bits Given an address 0x30004a5c What is the block offset what is the set index and what isthetag 24 15213 F 02 Fully associative caches A cache with exactly one set is called a fully associative cache I All lines in the cache are in that one set I Each line is uniquely identified by the tag bits alone The problem with fully associative caches I There are many cache lines in one set I The CPU must find a matching tag very fast less than one clock cycle I You need logic to compare all the tags in parallel I This can get expensive 25 15213 F 02 parking lot analogy 1 more parking permits than slots 2 student can park in any space 3 in reality hardware has to do a parallel search based on the valid bit AND the tag 26 15213 F 02 Review A direct mapped cache has one line per set I There are as many sets as there are cache lines in the cache I Likelihood of contention o conflict misses o Cache entries get evicted when the cache isn t full A fully associative cache has exactly one set I All lines in the cache belong to that one set I Problem of quick search for a matching tag A set associative cache has several lines per set I An N way associative cache has N lines per set 27 15213 F 02 What about writing to memory Written data is also cached On a cache miss preread the cache line into the cache Then write the data into the cache line Subsequent reads or writes will have a cache hit 28 15213 F 02 Writing to memory How does the data get from the cache to memory Writethrough cache Data is written through to memory at the time of the store instruction Writeback cache New data is stored in the cache and written to memory later What is the problem with a writethrough cache What is the problem with a writeback cache may have 2 write data twice evict dirty and write new With writeback how does the CPU decide when to write the data to memory 29 15213 F 02 What about multiprocessors What s the problem with writeback caches register file 5 bus interface ltgt system bus ALU cache bus lt rei ister file I 39 ALU cache bus memory bus b t f lO ltigt main us In er ace bridge memory 15213 F O2 design rule of thumb for caches if you double the associativity that is about the same as doubling the cache size itself so 2way gt direct 4way gt 2way beyond 4way not so good 31 15213 F 02
Are you sure you want to buy this material for
You're already Subscribed!
Looks like you've already subscribed to StudySoup, you won't need to purchase another subscription to get this material. To access this material simply click 'View Full Document'