CS3280 Week Two Notes
CS3280 Week Two Notes 3280
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MUNM 1113 003
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This 15 page Class Notes was uploaded by Courtney Walker on Friday September 4, 2015. The Class Notes belongs to 3280 at University of Missouri - Columbia taught by Michael Jurczyk in Summer 2015. Since its upload, it has received 70 views. For similar materials see Computer Organization and Assembly Language in ComputerScienence at University of Missouri - Columbia.
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Date Created: 09/04/15
0606 M MUSAV 3 MicrocomputerArchitecture Von NeumannPrinceton 3ch noo f Q Lit M 5 Ofeq 39 m 39 gtcgtr3dcs 0 331mg 72 b 0g 93353 e 3 m r lt e c gt60 c5236 v e v too Coca Faggckm gwm kc A emam kfakxw y I Com lt W Qc ces bus I y Plt c39 CDM39J 39 QCth39hmeA CKC LOOV C OOEY E L 0C a TO SJCUC KQOS 59 391 E CCgcArkxle ecccesa C eXCQ Definitions Processor ALU Controller Computer processor memory lO Computer architecture interconnections of computer modules Instruction register holds a fetched instruction while processor executes this instruction 39 Program counter pointer to next instruction in memory to get Condition code register set of flags that control processor operations eg conditional branch execu on Main disadvantage of von Neumann architecture Harvard Architecture ALU quotquot9 e v N data bus 4 39 Data readwrite if RAM data address bus Controller 4 f e f instruction bus InStrUCtIOH RAM instruction 39 address bus Main disadvantages of Harvard architecture Lne C xcxenx mamocq 036 C efqev oaks 36 bLJAY 6ma Qroowemg DC Soda 63gt a 5396 sea 6ch Coqrsms Two ways to implement controller 1 Finite State Machine Microcontroller 2 Microprogrammed Processor some Pentiums Control signals microinstruction for each step of instruction execution stored in a Micro ROM on processor chip Instructionbyte points to corresponding control signal block in MicroROM f When executing instruction controller reads control signals out of MicroROM one byone and send signals to other units ALU memory etc To minimize size of Micro ROM microinstructions are not stored consecutively in MicroROM each microinstruction contains an address field pointing to the next micro instruction W6Cgt0 C aq I and CISC and RISC CISC complex instruction set computer large instruction set high level operations requires microcode interpreter some more complex instructions are hard to take advantage of examples Intel 80x86 and lA 32 families RISC reduced instruction set computer simple atomic instructions small instruction set directly executed by hardware rely on highly optimizing compilers examples 0 ARM DEC Alpha SUN Sparc Most microcontrollers Instruction Set Group of valid instructions that a processor can execute depends on processor Can be further divided into subgroups Arithmetic operations add subtract multiply divide 2 s complement op Logical operations AND OR XOR Complement LoadStore operations move data from external memory into processor or vice versa move data within processor between registers data movement within memory normally not possible Load memory gt processor Store processor memory InputOutput operations move data from O into processor or vice versa lnput lO processor Output processor lO Instruction Set Can be further divided into subgroups Branch Change the order of instruction execution jump to different program section How By changing contents of PC Unconditional branchesjumps Branch always taken Conditional branch Branch taken depending on condition code register flags Stack operations To implement dynamic data storage Can push registers onto the stack and pull them back off Subroutine operations To implement functionprocedure callsreturns Notation used Decimal number 10 Hex number 10 Binary number 10 Motorola 68HC11 Miorooontroller 8 bit wide data bus 16bit wide address bus 64K memory cells addressable Address range 0000 FFFF Divide memory into 256 byte pages page number MSB of address Page 0 0000 00FF Page 1 0100 01FF Page 255 FF00 FFFF Programming model Processor registers Memory A B 0000 BUB 8mm 5 Igt dga D virtual not real w reEllsters 2 bytes AzB V J X 2bytes 3210 01 Y w 3211 35 2 bytes address SPStaCk DOinter gt Registers 2 bytes pointers PC 2 bytes 39 FFFF Condition code flags 8 bits IR 5 bytes Cc 3CQAVLJ1H Languages Machine Language Assembly Language instruction number code Instruction mnemonics bytes in memory Program source code BB 02 00 Disassembler translates I Assembler translates number codes into mnemonics mnemonics into machine language 0x654 393 b a W See Book Appendix for assemblerdisassembler mcomw N get very familiar with it you will use it in the exams oweaaVs3Hcrr1aewoesav s Instruction operation PC contents of program counter MAB contents of memory cell with address equal to address on address bus DB data on data bus IR instruction register 1 Fetch Phase e a PC QC 300 1 Pl Leodm leu y WW x 53 5W BB c200 m em 0 w We saw Claw m 1 02 0201 processor Skate 9 quot91 10 0202 PCPC Av as czox e IR Cl co e lin mc m J7 9W9 5 bqk quot 55 0210 b PC CZCgt gt7 lagged 53 sxla 1o L we ea memoryi gtugtlt m e a CZ 52m bog IR processor 6W6 06gt quotlMoTQx PC PC PL AH slagOZ e e 0200 C 30 KC ZQZ e at gddf SS beg law me qyig A f memory fo mter B km coke Clara s1 3 IR 02 processor 33mm 06 wko wa 1 Pc gtC 3r C03 BB 02 1 10 55 PC 0200 A 02 0200 C201 0202 0210 After execution PC S 200 A E57 Example 2 Execution Phase ADDA 0210 90 CZKOB a EA SCZIO 9 RW line 256 memory 90 62m 655 00 ltfgt processor rm AVE S S 1 02 A 35 57 5 g FetchDecodeExecute Architecture Addressing Modes Effective address address that processor puts onto address bus to loadstore DATA item fromto memory Addressing mode determines how to obtain effective address 68HC11 Addressing modes Extended Addressing Direct addressing Inherent Addressing Immediate Addressing Indexed Addressing Relative Addressing ovenhooky 1 Extended Addressing Mode EA U o gtlt e s 03quotng ADDA0210 ame czmo s 2e Mme We address range hz whom memsckx 2 Direct Addressing Mode EA 1L9 bi y page s DO 1 LS OXNCO 10 t msmcxxgm ADDA 02 e qeimz s as s 00 oz 5 25 6ka address range Dam O 3 Inherent Addressing Mode No EA to be generated data in processor not in memory 39 or data not needed ABA QM m 0333 52 on address range Mg 4 Immediate Addressing Mode No EA to be generated data m tosxcoesch wADDA02 strata arm Max703 BE CAREFUL ADDA02 ADDAQCZ 4 T 5 8 f 7 am fiecm a so a payeeea
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